1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <linux/thermal.h>
22 #include <linux/reset.h>
23 #include <linux/types.h>
25 #include "../thermal_hwmon.h"
27 /* AUXADC Registers */
28 #define AUXADC_CON1_SET_V 0x008
29 #define AUXADC_CON1_CLR_V 0x00c
30 #define AUXADC_CON2_V 0x010
31 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
33 #define APMIXED_SYS_TS_CON0 0x600
34 #define APMIXED_SYS_TS_CON1 0x604
36 /* Thermal Controller Registers */
37 #define TEMP_MONCTL0 0x000
38 #define TEMP_MONCTL1 0x004
39 #define TEMP_MONCTL2 0x008
40 #define TEMP_MONIDET0 0x014
41 #define TEMP_MONIDET1 0x018
42 #define TEMP_MSRCTL0 0x038
43 #define TEMP_MSRCTL1 0x03c
44 #define TEMP_AHBPOLL 0x040
45 #define TEMP_AHBTO 0x044
46 #define TEMP_ADCPNP0 0x048
47 #define TEMP_ADCPNP1 0x04c
48 #define TEMP_ADCPNP2 0x050
49 #define TEMP_ADCPNP3 0x0b4
51 #define TEMP_ADCMUX 0x054
52 #define TEMP_ADCEN 0x060
53 #define TEMP_PNPMUXADDR 0x064
54 #define TEMP_ADCMUXADDR 0x068
55 #define TEMP_ADCENADDR 0x074
56 #define TEMP_ADCVALIDADDR 0x078
57 #define TEMP_ADCVOLTADDR 0x07c
58 #define TEMP_RDCTRL 0x080
59 #define TEMP_ADCVALIDMASK 0x084
60 #define TEMP_ADCVOLTAGESHIFT 0x088
61 #define TEMP_ADCWRITECTRL 0x08c
62 #define TEMP_MSR0 0x090
63 #define TEMP_MSR1 0x094
64 #define TEMP_MSR2 0x098
65 #define TEMP_MSR3 0x0B8
67 #define TEMP_SPARE0 0x0f0
69 #define TEMP_ADCPNP0_1 0x148
70 #define TEMP_ADCPNP1_1 0x14c
71 #define TEMP_ADCPNP2_1 0x150
72 #define TEMP_MSR0_1 0x190
73 #define TEMP_MSR1_1 0x194
74 #define TEMP_MSR2_1 0x198
75 #define TEMP_ADCPNP3_1 0x1b4
76 #define TEMP_MSR3_1 0x1B8
78 #define PTPCORESEL 0x400
80 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
82 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
83 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
85 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
87 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
88 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
90 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
91 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
93 /* MT8173 thermal sensors */
98 #define MT8173_TSABB 4
100 /* AUXADC channel 11 is used for the temperature sensors */
101 #define MT8173_TEMP_AUXADC_CHANNEL 11
103 /* The total number of temperature sensors in the MT8173 */
104 #define MT8173_NUM_SENSORS 5
106 /* The number of banks in the MT8173 */
107 #define MT8173_NUM_ZONES 4
109 /* The number of sensing points per bank */
110 #define MT8173_NUM_SENSORS_PER_ZONE 4
112 /* The number of controller in the MT8173 */
113 #define MT8173_NUM_CONTROLLER 1
115 /* The calibration coefficient of sensor */
116 #define MT8173_CALIBRATION 165
118 /* Valid temperatures range */
119 #define MT8173_TEMP_MIN -20000
120 #define MT8173_TEMP_MAX 150000
123 * Layout of the fuses providing the calibration data
124 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
125 * MT8183 has 6 sensors and needs 6 VTS calibration data.
126 * MT8173 has 5 sensors and needs 5 VTS calibration data.
127 * MT2701 has 3 sensors and needs 3 VTS calibration data.
128 * MT2712 has 4 sensors and needs 4 VTS calibration data.
130 #define CALIB_BUF0_VALID_V1 BIT(0)
131 #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
132 #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
133 #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
134 #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
135 #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
136 #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
137 #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
138 #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
139 #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
140 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
141 #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
144 * Layout of the fuses providing the calibration data
145 * These macros could be used for MT7622.
147 #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
148 #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
149 #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
150 #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
151 #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
152 #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
153 #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
154 #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
155 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
158 * Layout of the fuses providing the calibration data
159 * These macros can be used for MT7981 and MT7986.
161 #define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
162 #define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
163 #define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
164 #define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
165 #define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
166 #define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
167 #define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
168 #define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
169 #define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
181 enum mtk_thermal_version {
187 /* MT2701 thermal sensors */
190 #define MT2701_TSABB 2
192 /* AUXADC channel 11 is used for the temperature sensors */
193 #define MT2701_TEMP_AUXADC_CHANNEL 11
195 /* The total number of temperature sensors in the MT2701 */
196 #define MT2701_NUM_SENSORS 3
198 /* The number of sensing points per bank */
199 #define MT2701_NUM_SENSORS_PER_ZONE 3
201 /* The number of controller in the MT2701 */
202 #define MT2701_NUM_CONTROLLER 1
204 /* The calibration coefficient of sensor */
205 #define MT2701_CALIBRATION 165
207 /* MT2712 thermal sensors */
213 /* AUXADC channel 11 is used for the temperature sensors */
214 #define MT2712_TEMP_AUXADC_CHANNEL 11
216 /* The total number of temperature sensors in the MT2712 */
217 #define MT2712_NUM_SENSORS 4
219 /* The number of sensing points per bank */
220 #define MT2712_NUM_SENSORS_PER_ZONE 4
222 /* The number of controller in the MT2712 */
223 #define MT2712_NUM_CONTROLLER 1
225 /* The calibration coefficient of sensor */
226 #define MT2712_CALIBRATION 165
228 #define MT7622_TEMP_AUXADC_CHANNEL 11
229 #define MT7622_NUM_SENSORS 1
230 #define MT7622_NUM_ZONES 1
231 #define MT7622_NUM_SENSORS_PER_ZONE 1
233 #define MT7622_NUM_CONTROLLER 1
235 /* The maximum number of banks */
236 #define MAX_NUM_ZONES 8
238 /* The calibration coefficient of sensor */
239 #define MT7622_CALIBRATION 165
241 /* MT8183 thermal sensors */
247 #define MT8183_TSABB 5
249 /* AUXADC channel is used for the temperature sensors */
250 #define MT8183_TEMP_AUXADC_CHANNEL 11
252 /* The total number of temperature sensors in the MT8183 */
253 #define MT8183_NUM_SENSORS 6
255 /* The number of banks in the MT8183 */
256 #define MT8183_NUM_ZONES 1
258 /* The number of sensing points per bank */
259 #define MT8183_NUM_SENSORS_PER_ZONE 6
261 /* The number of controller in the MT8183 */
262 #define MT8183_NUM_CONTROLLER 2
264 /* The calibration coefficient of sensor */
265 #define MT8183_CALIBRATION 153
267 /* AUXADC channel 11 is used for the temperature sensors */
268 #define MT7986_TEMP_AUXADC_CHANNEL 11
270 /* The total number of temperature sensors in the MT7986 */
271 #define MT7986_NUM_SENSORS 1
273 /* The number of banks in the MT7986 */
274 #define MT7986_NUM_ZONES 1
276 /* The number of sensing points per bank */
277 #define MT7986_NUM_SENSORS_PER_ZONE 1
279 /* MT7986 thermal sensors */
282 /* The number of controller in the MT7986 */
283 #define MT7986_NUM_CONTROLLER 1
285 /* The calibration coefficient of sensor */
286 #define MT7986_CALIBRATION 165
289 #define MT8365_TEMP_AUXADC_CHANNEL 11
290 #define MT8365_CALIBRATION 164
291 #define MT8365_NUM_CONTROLLER 1
292 #define MT8365_NUM_BANKS 1
293 #define MT8365_NUM_SENSORS 3
294 #define MT8365_NUM_SENSORS_PER_ZONE 3
301 struct thermal_bank_cfg {
302 unsigned int num_sensors;
306 struct mtk_thermal_bank {
307 struct mtk_thermal *mt;
311 struct mtk_thermal_data {
315 const int *vts_index;
316 const int *sensor_mux_values;
320 const int num_controller;
321 const int *controller_offset;
322 bool need_switch_bank;
323 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
324 enum mtk_thermal_version version;
325 u32 apmixed_buffer_ctl_reg;
326 u32 apmixed_buffer_ctl_mask;
327 u32 apmixed_buffer_ctl_set;
332 void __iomem *thermal_base;
334 struct clk *clk_peri_therm;
335 struct clk *clk_auxadc;
336 /* lock: for getting and putting banks */
339 /* Calibration values */
345 s32 vts[MAX_NUM_VTS];
347 const struct mtk_thermal_data *conf;
348 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
350 int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
353 /* MT8183 thermal sensor data */
354 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
355 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
358 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
359 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
362 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
363 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
364 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
367 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
368 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
370 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
371 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
374 /* MT8173 thermal sensor data */
375 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
376 { MT8173_TS2, MT8173_TS3 },
377 { MT8173_TS2, MT8173_TS4 },
378 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
382 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
383 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
386 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
387 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
390 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
391 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
393 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
394 VTS1, VTS2, VTS3, VTS4, VTSABB
397 /* MT2701 thermal sensor data */
398 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
399 MT2701_TS1, MT2701_TS2, MT2701_TSABB
402 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
403 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
406 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
407 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
410 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
411 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
413 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
417 /* MT2712 thermal sensor data */
418 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
419 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
422 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
423 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
426 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
427 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
430 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
431 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
433 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
434 VTS1, VTS2, VTS3, VTS4
437 /* MT7622 thermal sensor data */
438 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
439 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
440 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
441 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
442 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
443 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
445 /* MT7986 thermal sensor data */
446 static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
447 static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
448 static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
449 static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
450 static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
451 static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
453 /* MT8365 thermal sensor data */
454 static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
455 MT8365_TS1, MT8365_TS2, MT8365_TS3
458 static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
459 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
462 static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
463 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
466 static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
467 static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
469 static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
472 * The MT8173 thermal controller has four banks. Each bank can read up to
473 * four temperature sensors simultaneously. The MT8173 has a total of 5
474 * temperature sensors. We use each bank to measure a certain area of the
475 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
476 * areas, hence is used in different banks.
478 * The thermal core only gets the maximum temperature of all banks, so
479 * the bank concept wouldn't be necessary here. However, the SVS (Smart
480 * Voltage Scaling) unit makes its decisions based on the same bank
481 * data, and this indeed needs the temperatures of the individual banks
482 * for making better decisions.
484 static const struct mtk_thermal_data mt8173_thermal_data = {
485 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
486 .num_banks = MT8173_NUM_ZONES,
487 .num_sensors = MT8173_NUM_SENSORS,
488 .vts_index = mt8173_vts_index,
489 .cali_val = MT8173_CALIBRATION,
490 .num_controller = MT8173_NUM_CONTROLLER,
491 .controller_offset = mt8173_tc_offset,
492 .need_switch_bank = true,
496 .sensors = mt8173_bank_data[0],
499 .sensors = mt8173_bank_data[1],
502 .sensors = mt8173_bank_data[2],
505 .sensors = mt8173_bank_data[3],
509 .adcpnp = mt8173_adcpnp,
510 .sensor_mux_values = mt8173_mux_values,
511 .version = MTK_THERMAL_V1,
515 * The MT2701 thermal controller has one bank, which can read up to
516 * three temperature sensors simultaneously. The MT2701 has a total of 3
517 * temperature sensors.
519 * The thermal core only gets the maximum temperature of this one bank,
520 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
521 * Voltage Scaling) unit makes its decisions based on the same bank
524 static const struct mtk_thermal_data mt2701_thermal_data = {
525 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
527 .num_sensors = MT2701_NUM_SENSORS,
528 .vts_index = mt2701_vts_index,
529 .cali_val = MT2701_CALIBRATION,
530 .num_controller = MT2701_NUM_CONTROLLER,
531 .controller_offset = mt2701_tc_offset,
532 .need_switch_bank = true,
536 .sensors = mt2701_bank_data,
540 .adcpnp = mt2701_adcpnp,
541 .sensor_mux_values = mt2701_mux_values,
542 .version = MTK_THERMAL_V1,
546 * The MT8365 thermal controller has one bank, which can read up to
547 * four temperature sensors simultaneously. The MT8365 has a total of 3
548 * temperature sensors.
550 * The thermal core only gets the maximum temperature of this one bank,
551 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
552 * Voltage Scaling) unit makes its decisions based on the same bank
555 static const struct mtk_thermal_data mt8365_thermal_data = {
556 .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
557 .num_banks = MT8365_NUM_BANKS,
558 .num_sensors = MT8365_NUM_SENSORS,
559 .vts_index = mt8365_vts_index,
560 .cali_val = MT8365_CALIBRATION,
561 .num_controller = MT8365_NUM_CONTROLLER,
562 .controller_offset = mt8365_tc_offset,
563 .need_switch_bank = false,
566 .num_sensors = MT8365_NUM_SENSORS,
567 .sensors = mt8365_bank_data
571 .adcpnp = mt8365_adcpnp,
572 .sensor_mux_values = mt8365_mux_values,
573 .version = MTK_THERMAL_V1,
574 .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
575 .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
576 .apmixed_buffer_ctl_set = 0,
580 * The MT2712 thermal controller has one bank, which can read up to
581 * four temperature sensors simultaneously. The MT2712 has a total of 4
582 * temperature sensors.
584 * The thermal core only gets the maximum temperature of this one bank,
585 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
586 * Voltage Scaling) unit makes its decisions based on the same bank
589 static const struct mtk_thermal_data mt2712_thermal_data = {
590 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
592 .num_sensors = MT2712_NUM_SENSORS,
593 .vts_index = mt2712_vts_index,
594 .cali_val = MT2712_CALIBRATION,
595 .num_controller = MT2712_NUM_CONTROLLER,
596 .controller_offset = mt2712_tc_offset,
597 .need_switch_bank = true,
601 .sensors = mt2712_bank_data,
605 .adcpnp = mt2712_adcpnp,
606 .sensor_mux_values = mt2712_mux_values,
607 .version = MTK_THERMAL_V1,
611 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
614 static const struct mtk_thermal_data mt7622_thermal_data = {
615 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
616 .num_banks = MT7622_NUM_ZONES,
617 .num_sensors = MT7622_NUM_SENSORS,
618 .vts_index = mt7622_vts_index,
619 .cali_val = MT7622_CALIBRATION,
620 .num_controller = MT7622_NUM_CONTROLLER,
621 .controller_offset = mt7622_tc_offset,
622 .need_switch_bank = true,
626 .sensors = mt7622_bank_data,
630 .adcpnp = mt7622_adcpnp,
631 .sensor_mux_values = mt7622_mux_values,
632 .version = MTK_THERMAL_V2,
633 .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
634 .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
635 .apmixed_buffer_ctl_set = BIT(0),
639 * The MT8183 thermal controller has one bank for the current SW framework.
640 * The MT8183 has a total of 6 temperature sensors.
641 * There are two thermal controller to control the six sensor.
642 * The first one bind 2 sensor, and the other bind 4 sensors.
643 * The thermal core only gets the maximum temperature of all sensor, so
644 * the bank concept wouldn't be necessary here. However, the SVS (Smart
645 * Voltage Scaling) unit makes its decisions based on the same bank
646 * data, and this indeed needs the temperatures of the individual banks
647 * for making better decisions.
649 static const struct mtk_thermal_data mt8183_thermal_data = {
650 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
651 .num_banks = MT8183_NUM_ZONES,
652 .num_sensors = MT8183_NUM_SENSORS,
653 .vts_index = mt8183_vts_index,
654 .cali_val = MT8183_CALIBRATION,
655 .num_controller = MT8183_NUM_CONTROLLER,
656 .controller_offset = mt8183_tc_offset,
657 .need_switch_bank = false,
661 .sensors = mt8183_bank_data,
666 .adcpnp = mt8183_adcpnp,
667 .sensor_mux_values = mt8183_mux_values,
668 .version = MTK_THERMAL_V1,
672 * MT7986 uses AUXADC Channel 11 for raw data access.
674 static const struct mtk_thermal_data mt7986_thermal_data = {
675 .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
676 .num_banks = MT7986_NUM_ZONES,
677 .num_sensors = MT7986_NUM_SENSORS,
678 .vts_index = mt7986_vts_index,
679 .cali_val = MT7986_CALIBRATION,
680 .num_controller = MT7986_NUM_CONTROLLER,
681 .controller_offset = mt7986_tc_offset,
682 .need_switch_bank = true,
686 .sensors = mt7986_bank_data,
690 .adcpnp = mt7986_adcpnp,
691 .sensor_mux_values = mt7986_mux_values,
692 .version = MTK_THERMAL_V3,
695 static bool mtk_thermal_temp_is_valid(int temp)
697 return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
701 * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
702 * @mt: The thermal controller
703 * @sensno: sensor number
704 * @raw: raw ADC value
706 * This converts the raw ADC value to mcelsius using the SoC specific
707 * calibration constants
709 static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
715 tmp = 203450520 << 3;
716 tmp /= mt->conf->cali_val + mt->o_slope;
717 tmp /= 10000 + mt->adc_ge;
718 tmp *= raw - mt->vts[sensno] - 3350;
721 return mt->degc_cali * 500 - tmp;
724 static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
737 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
738 g_oe = mt->adc_oe - 512;
739 format_1 = mt->vts[VTS2] + 3105 - g_oe;
740 format_2 = (mt->degc_cali * 10) >> 1;
741 g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
743 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
744 tmp = tmp * 10 * 100 / 11;
746 if (mt->o_slope_sign == 0)
747 tmp = tmp / (165 - mt->o_slope);
749 tmp = tmp / (165 + mt->o_slope);
751 return (format_2 - tmp) * 100;
754 static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
762 tmp = 100000 * 15 / 16 * 10000;
763 tmp /= 4096 - 512 + mt->adc_ge;
765 tmp *= raw - mt->vts[sensno] - 2900;
767 return mt->degc_cali * 500 - tmp;
771 * mtk_thermal_get_bank - get bank
774 * The bank registers are banked, we have to select a bank in the
775 * PTPCORESEL register to access it.
777 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
779 struct mtk_thermal *mt = bank->mt;
782 if (mt->conf->need_switch_bank) {
783 mutex_lock(&mt->lock);
785 val = readl(mt->thermal_base + PTPCORESEL);
788 writel(val, mt->thermal_base + PTPCORESEL);
793 * mtk_thermal_put_bank - release bank
796 * release a bank previously taken with mtk_thermal_get_bank,
798 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
800 struct mtk_thermal *mt = bank->mt;
802 if (mt->conf->need_switch_bank)
803 mutex_unlock(&mt->lock);
807 * mtk_thermal_bank_temperature - get the temperature of a bank
810 * The temperature of a bank is considered the maximum temperature of
811 * the sensors associated to the bank.
813 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
815 struct mtk_thermal *mt = bank->mt;
816 const struct mtk_thermal_data *conf = mt->conf;
817 int i, temp = INT_MIN, max = INT_MIN;
820 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
821 raw = readl(mt->thermal_base + conf->msr[i]);
823 temp = mt->raw_to_mcelsius(
824 mt, conf->bank_data[bank->id].sensors[i], raw);
827 * Depending on the filt/sen intervals and ADC polling time,
828 * we may need up to 60 milliseconds after initialization: this
829 * will result in the first reading containing an out of range
831 * Validate the reading to both address the aforementioned issue
832 * and to eventually avoid bogus readings during runtime in the
833 * event that the AUXADC gets unstable due to high EMI, etc.
835 if (!mtk_thermal_temp_is_valid(temp))
836 temp = THERMAL_TEMP_INVALID;
845 static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
847 struct mtk_thermal *mt = thermal_zone_device_priv(tz);
849 int tempmax = INT_MIN;
851 for (i = 0; i < mt->conf->num_banks; i++) {
852 struct mtk_thermal_bank *bank = &mt->banks[i];
854 mtk_thermal_get_bank(bank);
856 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
858 mtk_thermal_put_bank(bank);
861 *temperature = tempmax;
866 static const struct thermal_zone_device_ops mtk_thermal_ops = {
867 .get_temp = mtk_read_temp,
870 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
871 u32 apmixed_phys_base, u32 auxadc_phys_base,
874 struct mtk_thermal_bank *bank = &mt->banks[num];
875 const struct mtk_thermal_data *conf = mt->conf;
878 int offset = mt->conf->controller_offset[ctrl_id];
879 void __iomem *controller_base = mt->thermal_base + offset;
884 mtk_thermal_get_bank(bank);
886 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
887 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
890 * filt interval is 1 * 46.540us = 46.54us,
891 * sen interval is 429 * 46.540us = 19.96ms
893 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
894 TEMP_MONCTL2_SENSOR_INTERVAL(429),
895 controller_base + TEMP_MONCTL2);
897 /* poll is set to 10u */
898 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
899 controller_base + TEMP_AHBPOLL);
901 /* temperature sampling control, 1 sample */
902 writel(0x0, controller_base + TEMP_MSRCTL0);
904 /* exceed this polling time, IRQ would be inserted */
905 writel(0xffffffff, controller_base + TEMP_AHBTO);
907 /* number of interrupts per event, 1 is enough */
908 writel(0x0, controller_base + TEMP_MONIDET0);
909 writel(0x0, controller_base + TEMP_MONIDET1);
912 * The MT8173 thermal controller does not have its own ADC. Instead it
913 * uses AHB bus accesses to control the AUXADC. To do this the thermal
914 * controller has to be programmed with the physical addresses of the
915 * AUXADC registers and with the various bit positions in the AUXADC.
916 * Also the thermal controller controls a mux in the APMIXEDSYS register
921 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
922 * automatically by hw
924 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
926 /* AHB address for auxadc mux selection */
927 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
928 controller_base + TEMP_ADCMUXADDR);
930 if (mt->conf->version == MTK_THERMAL_V1) {
931 /* AHB address for pnp sensor mux selection */
932 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
933 controller_base + TEMP_PNPMUXADDR);
936 /* AHB value for auxadc enable */
937 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
939 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
940 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
941 controller_base + TEMP_ADCENADDR);
943 /* AHB address for auxadc valid bit */
944 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
945 controller_base + TEMP_ADCVALIDADDR);
947 /* AHB address for auxadc voltage output */
948 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
949 controller_base + TEMP_ADCVOLTADDR);
951 /* read valid & voltage are at the same register */
952 writel(0x0, controller_base + TEMP_RDCTRL);
954 /* indicate where the valid bit is */
955 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
956 controller_base + TEMP_ADCVALIDMASK);
959 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
961 /* enable auxadc mux write transaction */
962 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
963 controller_base + TEMP_ADCWRITECTRL);
965 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
966 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
967 mt->thermal_base + conf->adcpnp[i]);
969 writel((1 << conf->bank_data[num].num_sensors) - 1,
970 controller_base + TEMP_MONCTL0);
972 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
973 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
974 controller_base + TEMP_ADCWRITECTRL);
976 mtk_thermal_put_bank(bank);
979 static u64 of_get_phys_base(struct device_node *np)
983 if (of_address_to_resource(np, 0, &res))
989 static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
993 if (!(buf[0] & CALIB_BUF0_VALID_V1))
996 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
998 for (i = 0; i < mt->conf->num_sensors; i++) {
999 switch (mt->conf->vts_index[i]) {
1001 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
1004 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
1007 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
1010 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
1013 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
1017 CALIB_BUF2_VTS_TSABB_V1(buf[2]);
1024 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
1025 if (CALIB_BUF1_ID_V1(buf[1]) &
1026 CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
1027 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
1029 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
1034 static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
1036 if (!CALIB_BUF1_VALID_V2(buf[1]))
1039 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
1040 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
1041 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
1042 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
1043 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
1044 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
1045 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
1046 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
1051 static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
1053 if (!CALIB_BUF1_VALID_V3(buf[1]))
1056 mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
1057 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
1058 mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
1059 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
1060 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
1061 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
1062 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
1064 if (CALIB_BUF1_ID_V3(buf[1]) == 0)
1070 static int mtk_thermal_get_calibration_data(struct device *dev,
1071 struct mtk_thermal *mt)
1073 struct nvmem_cell *cell;
1078 /* Start with default values */
1081 for (i = 0; i < mt->conf->num_sensors; i++)
1086 cell = nvmem_cell_get(dev, "calibration-data");
1088 if (PTR_ERR(cell) == -EPROBE_DEFER)
1089 return PTR_ERR(cell);
1093 buf = (u32 *)nvmem_cell_read(cell, &len);
1095 nvmem_cell_put(cell);
1098 return PTR_ERR(buf);
1100 if (len < 3 * sizeof(u32)) {
1101 dev_warn(dev, "invalid calibration data\n");
1106 switch (mt->conf->version) {
1107 case MTK_THERMAL_V1:
1108 ret = mtk_thermal_extract_efuse_v1(mt, buf);
1110 case MTK_THERMAL_V2:
1111 ret = mtk_thermal_extract_efuse_v2(mt, buf);
1113 case MTK_THERMAL_V3:
1114 ret = mtk_thermal_extract_efuse_v3(mt, buf);
1122 dev_info(dev, "Device not calibrated, using default calibration values\n");
1132 static const struct of_device_id mtk_thermal_of_match[] = {
1134 .compatible = "mediatek,mt8173-thermal",
1135 .data = (void *)&mt8173_thermal_data,
1138 .compatible = "mediatek,mt2701-thermal",
1139 .data = (void *)&mt2701_thermal_data,
1142 .compatible = "mediatek,mt2712-thermal",
1143 .data = (void *)&mt2712_thermal_data,
1146 .compatible = "mediatek,mt7622-thermal",
1147 .data = (void *)&mt7622_thermal_data,
1150 .compatible = "mediatek,mt7986-thermal",
1151 .data = (void *)&mt7986_thermal_data,
1154 .compatible = "mediatek,mt8183-thermal",
1155 .data = (void *)&mt8183_thermal_data,
1158 .compatible = "mediatek,mt8365-thermal",
1159 .data = (void *)&mt8365_thermal_data,
1163 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
1165 static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
1166 void __iomem *apmixed_base)
1170 if (!mt->conf->apmixed_buffer_ctl_reg)
1173 tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1174 tmp &= mt->conf->apmixed_buffer_ctl_mask;
1175 tmp |= mt->conf->apmixed_buffer_ctl_set;
1176 writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1180 static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1181 void __iomem *auxadc_base)
1185 writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
1186 writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1187 tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1188 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1191 static int mtk_thermal_probe(struct platform_device *pdev)
1193 int ret, i, ctrl_id;
1194 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
1195 struct mtk_thermal *mt;
1196 u64 auxadc_phys_base, apmixed_phys_base;
1197 struct thermal_zone_device *tzdev;
1198 void __iomem *apmixed_base, *auxadc_base;
1200 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1204 mt->conf = of_device_get_match_data(&pdev->dev);
1206 mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1207 if (IS_ERR(mt->thermal_base))
1208 return PTR_ERR(mt->thermal_base);
1210 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1214 mutex_init(&mt->lock);
1216 mt->dev = &pdev->dev;
1218 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1220 dev_err(&pdev->dev, "missing auxadc node\n");
1224 auxadc_base = of_iomap(auxadc, 0);
1225 auxadc_phys_base = of_get_phys_base(auxadc);
1227 of_node_put(auxadc);
1229 if (auxadc_phys_base == OF_BAD_ADDR) {
1230 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1234 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1236 dev_err(&pdev->dev, "missing apmixedsys node\n");
1240 apmixed_base = of_iomap(apmixedsys, 0);
1241 apmixed_phys_base = of_get_phys_base(apmixedsys);
1243 of_node_put(apmixedsys);
1245 if (apmixed_phys_base == OF_BAD_ADDR) {
1246 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1250 ret = device_reset_optional(&pdev->dev);
1254 mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
1255 if (IS_ERR(mt->clk_auxadc)) {
1256 ret = PTR_ERR(mt->clk_auxadc);
1257 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1261 mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
1262 if (IS_ERR(mt->clk_peri_therm)) {
1263 ret = PTR_ERR(mt->clk_peri_therm);
1264 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1268 mtk_thermal_turn_on_buffer(mt, apmixed_base);
1270 if (mt->conf->version != MTK_THERMAL_V1)
1271 mtk_thermal_release_periodic_ts(mt, auxadc_base);
1273 if (mt->conf->version == MTK_THERMAL_V1)
1274 mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1275 else if (mt->conf->version == MTK_THERMAL_V2)
1276 mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1278 mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1280 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1281 for (i = 0; i < mt->conf->num_banks; i++)
1282 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1283 auxadc_phys_base, ctrl_id);
1285 tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1288 return PTR_ERR(tzdev);
1290 ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
1292 dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1297 static struct platform_driver mtk_thermal_driver = {
1298 .probe = mtk_thermal_probe,
1300 .name = "mtk-thermal",
1301 .of_match_table = mtk_thermal_of_match,
1305 module_platform_driver(mtk_thermal_driver);
1307 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1308 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1309 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1310 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1311 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1312 MODULE_DESCRIPTION("Mediatek thermal driver");
1313 MODULE_LICENSE("GPL v2");