1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
29 - description: clock used for the controller
30 - description: clock used for the pad
38 description: device-tree node of the required ECC engine.
39 $ref: /schemas/types.yaml#/definitions/phandle
43 $ref: raw-nand-chip.yaml#
44 unevaluatedProperties: false
52 - $ref: nand-controller.yaml#
58 const: mediatek,mt2701-nfc
66 enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
67 40, 44, 48, 52, 56, 60]
73 const: mediatek,mt2712-nfc
81 enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
82 40, 44, 48, 52, 56, 60, 68, 72, 80]
88 const: mediatek,mt7622-nfc
96 enum: [4, 6, 8, 10, 12]
106 unevaluatedProperties: false
110 #include <dt-bindings/clock/mt2701-clk.h>
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 #include <dt-bindings/interrupt-controller/irq.h>
115 #address-cells = <2>;
118 nand-controller@1100d000 {
119 compatible = "mediatek,mt2701-nfc";
120 reg = <0 0x1100d000 0 0x1000>;
121 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&pericfg CLK_PERI_NFI>,
123 <&pericfg CLK_PERI_NFI_PAD>;
124 clock-names = "nfi_clk", "pad_clk";
126 #address-cells = <1>;
133 nand-ecc-mode = "hw";
134 nand-ecc-step-size = <1024>;
135 nand-ecc-strength = <24>;
138 compatible = "fixed-partitions";
139 #address-cells = <1>;
145 reg = <0x0 0x400000>;
149 reg = <0x400000 0x12c00000>;