2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 struct mdp5_cfg_handler {
19 struct mdp5_cfg config;
22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
23 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
25 const struct mdp5_cfg_hw msm8x74v1_config = {
36 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
37 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
38 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
43 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
44 .flush_hw_mask = 0x0003ffff,
48 .base = { 0x01100, 0x01500, 0x01900 },
49 .caps = MDP_PIPE_CAP_HFLIP |
57 .base = { 0x01d00, 0x02100, 0x02500 },
58 .caps = MDP_PIPE_CAP_HFLIP |
65 .base = { 0x02900, 0x02d00 },
66 .caps = MDP_PIPE_CAP_HFLIP |
72 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
74 { .id = 0, .pp = 0, .dspp = 0,
75 .caps = MDP_LM_CAP_DISPLAY, },
76 { .id = 1, .pp = 1, .dspp = 1,
77 .caps = MDP_LM_CAP_DISPLAY, },
78 { .id = 2, .pp = 2, .dspp = 2,
79 .caps = MDP_LM_CAP_DISPLAY, },
80 { .id = 3, .pp = -1, .dspp = -1,
81 .caps = MDP_LM_CAP_WB },
82 { .id = 4, .pp = -1, .dspp = -1,
83 .caps = MDP_LM_CAP_WB },
91 .base = { 0x04500, 0x04900, 0x04d00 },
95 .base = { 0x21a00, 0x21b00, 0x21c00 },
98 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
106 .max_clk = 200000000,
109 const struct mdp5_cfg_hw msm8x74v2_config = {
113 .caps = MDP_CAP_SMP |
120 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
121 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
122 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
127 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
128 .flush_hw_mask = 0x0003ffff,
132 .base = { 0x01100, 0x01500, 0x01900 },
133 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
134 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
135 MDP_PIPE_CAP_DECIMATION,
139 .base = { 0x01d00, 0x02100, 0x02500 },
140 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
141 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
145 .base = { 0x02900, 0x02d00 },
146 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
150 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
152 { .id = 0, .pp = 0, .dspp = 0,
153 .caps = MDP_LM_CAP_DISPLAY, },
154 { .id = 1, .pp = 1, .dspp = 1,
155 .caps = MDP_LM_CAP_DISPLAY, },
156 { .id = 2, .pp = 2, .dspp = 2,
157 .caps = MDP_LM_CAP_DISPLAY, },
158 { .id = 3, .pp = -1, .dspp = -1,
159 .caps = MDP_LM_CAP_WB, },
160 { .id = 4, .pp = -1, .dspp = -1,
161 .caps = MDP_LM_CAP_WB, },
165 .max_height = 0xFFFF,
169 .base = { 0x04500, 0x04900, 0x04d00 },
173 .base = { 0x13000, 0x13200 },
177 .base = { 0x12c00, 0x12d00, 0x12e00 },
180 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
188 .max_clk = 200000000,
191 const struct mdp5_cfg_hw apq8084_config = {
195 .caps = MDP_CAP_SMP |
203 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
204 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
205 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
206 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
207 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
209 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
211 /* Two SMP blocks are statically tied to RGB pipes: */
212 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
217 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
218 .flush_hw_mask = 0x003fffff,
222 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
223 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
224 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
225 MDP_PIPE_CAP_DECIMATION,
229 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
230 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
231 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
235 .base = { 0x03100, 0x03500 },
236 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
240 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
242 { .id = 0, .pp = 0, .dspp = 0,
243 .caps = MDP_LM_CAP_DISPLAY |
245 { .id = 1, .pp = 1, .dspp = 1,
246 .caps = MDP_LM_CAP_DISPLAY, },
247 { .id = 2, .pp = 2, .dspp = 2,
248 .caps = MDP_LM_CAP_DISPLAY |
250 { .id = 3, .pp = -1, .dspp = -1,
251 .caps = MDP_LM_CAP_WB, },
252 { .id = 4, .pp = -1, .dspp = -1,
253 .caps = MDP_LM_CAP_WB, },
254 { .id = 5, .pp = 3, .dspp = 3,
255 .caps = MDP_LM_CAP_DISPLAY, },
259 .max_height = 0xFFFF,
263 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
268 .base = { 0x13400, 0x13600, 0x13800 },
272 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
275 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
283 .max_clk = 320000000,
286 const struct mdp5_cfg_hw msm8x16_config = {
291 .caps = MDP_CAP_SMP |
298 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
299 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
304 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
305 .flush_hw_mask = 0x4003ffff,
310 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
311 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
312 MDP_PIPE_CAP_DECIMATION,
316 .base = { 0x14000, 0x16000 },
317 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
318 MDP_PIPE_CAP_DECIMATION,
323 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
326 .count = 2, /* LM0 and LM3 */
327 .base = { 0x44000, 0x47000 },
329 { .id = 0, .pp = 0, .dspp = 0,
330 .caps = MDP_LM_CAP_DISPLAY, },
331 { .id = 3, .pp = -1, .dspp = -1,
332 .caps = MDP_LM_CAP_WB },
336 .max_height = 0xFFFF,
344 .base = { 0x00000, 0x6a800 },
350 .max_clk = 320000000,
353 const struct mdp5_cfg_hw msm8x94_config = {
357 .caps = MDP_CAP_SMP |
365 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
366 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
367 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
368 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
369 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
371 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
373 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
374 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
379 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
380 .flush_hw_mask = 0xf0ffffff,
384 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
385 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
386 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
387 MDP_PIPE_CAP_DECIMATION,
391 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
392 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
393 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
397 .base = { 0x24000, 0x26000 },
398 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
402 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
404 { .id = 0, .pp = 0, .dspp = 0,
405 .caps = MDP_LM_CAP_DISPLAY |
407 { .id = 1, .pp = 1, .dspp = 1,
408 .caps = MDP_LM_CAP_DISPLAY, },
409 { .id = 2, .pp = 2, .dspp = 2,
410 .caps = MDP_LM_CAP_DISPLAY |
412 { .id = 3, .pp = -1, .dspp = -1,
413 .caps = MDP_LM_CAP_WB, },
414 { .id = 4, .pp = -1, .dspp = -1,
415 .caps = MDP_LM_CAP_WB, },
416 { .id = 5, .pp = 3, .dspp = 3,
417 .caps = MDP_LM_CAP_DISPLAY, },
421 .max_height = 0xFFFF,
425 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
430 .base = { 0x78000, 0x78800, 0x79000 },
434 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
437 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
445 .max_clk = 400000000,
448 const struct mdp5_cfg_hw msm8x96_config = {
452 .caps = MDP_CAP_DSC |
459 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
460 .flush_hw_mask = 0xf4ffffff,
464 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
465 .caps = MDP_PIPE_CAP_HFLIP |
469 MDP_PIPE_CAP_DECIMATION |
470 MDP_PIPE_CAP_SW_PIX_EXT |
475 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
476 .caps = MDP_PIPE_CAP_HFLIP |
479 MDP_PIPE_CAP_DECIMATION |
480 MDP_PIPE_CAP_SW_PIX_EXT |
485 .base = { 0x24000, 0x26000 },
486 .caps = MDP_PIPE_CAP_HFLIP |
488 MDP_PIPE_CAP_SW_PIX_EXT |
493 .base = { 0x34000, 0x36000 },
494 .caps = MDP_PIPE_CAP_HFLIP |
496 MDP_PIPE_CAP_SW_PIX_EXT |
497 MDP_PIPE_CAP_CURSOR |
503 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
505 { .id = 0, .pp = 0, .dspp = 0,
506 .caps = MDP_LM_CAP_DISPLAY |
508 { .id = 1, .pp = 1, .dspp = 1,
509 .caps = MDP_LM_CAP_DISPLAY, },
510 { .id = 2, .pp = 2, .dspp = -1,
511 .caps = MDP_LM_CAP_DISPLAY |
513 { .id = 3, .pp = -1, .dspp = -1,
514 .caps = MDP_LM_CAP_WB, },
515 { .id = 4, .pp = -1, .dspp = -1,
516 .caps = MDP_LM_CAP_WB, },
517 { .id = 5, .pp = 3, .dspp = -1,
518 .caps = MDP_LM_CAP_DISPLAY, },
522 .max_height = 0xFFFF,
526 .base = { 0x54000, 0x56000 },
530 .base = { 0x78000, 0x78800, 0x79000 },
534 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
542 .base = { 0x80000, 0x80400 },
545 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
553 .max_clk = 412500000,
556 static const struct mdp5_cfg_handler cfg_handlers[] = {
557 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
558 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
559 { .revision = 3, .config = { .hw = &apq8084_config } },
560 { .revision = 6, .config = { .hw = &msm8x16_config } },
561 { .revision = 9, .config = { .hw = &msm8x94_config } },
562 { .revision = 7, .config = { .hw = &msm8x96_config } },
565 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
567 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
569 return cfg_handler->config.hw;
572 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
574 return &cfg_handler->config;
577 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
579 return cfg_handler->revision;
582 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
587 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
588 uint32_t major, uint32_t minor)
590 struct drm_device *dev = mdp5_kms->dev;
591 struct platform_device *pdev = to_platform_device(dev->dev);
592 struct mdp5_cfg_handler *cfg_handler;
593 struct mdp5_cfg_platform *pconfig;
596 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
597 if (unlikely(!cfg_handler)) {
603 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
609 /* only after mdp5_cfg global pointer's init can we access the hw */
610 for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
611 if (cfg_handlers[i].revision != minor)
613 mdp5_cfg = cfg_handlers[i].config.hw;
617 if (unlikely(!mdp5_cfg)) {
618 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
624 cfg_handler->revision = minor;
625 cfg_handler->config.hw = mdp5_cfg;
627 pconfig = mdp5_get_config(pdev);
628 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
630 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
636 mdp5_cfg_destroy(cfg_handler);
641 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
643 static struct mdp5_cfg_platform config = {};
645 config.iommu = iommu_domain_alloc(&platform_bus_type);
647 config.iommu->geometry.aperture_start = 0x1000;
648 config.iommu->geometry.aperture_end = 0xffffffff;