1 // SPDX-License-Identifier: GPL-2.0+
3 * Broadcom UniMAC MDIO bus controller driver
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy.h>
17 #include <linux/platform_data/mdio-bcm-unimac.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
22 #define MDIO_START_BUSY (1 << 29)
23 #define MDIO_READ_FAIL (1 << 28)
24 #define MDIO_RD (2 << 26)
25 #define MDIO_WR (1 << 26)
26 #define MDIO_PMD_SHIFT 21
27 #define MDIO_PMD_MASK 0x1F
28 #define MDIO_REG_SHIFT 16
29 #define MDIO_REG_MASK 0x1F
32 #define MDIO_C22 (1 << 0)
34 #define MDIO_CLK_DIV_SHIFT 4
35 #define MDIO_CLK_DIV_MASK 0x3F
36 #define MDIO_SUPP_PREAMBLE (1 << 12)
38 struct unimac_mdio_priv {
39 struct mii_bus *mii_bus;
41 int (*wait_func) (void *wait_func_data);
47 static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
49 /* MIPS chips strapped for BE will automagically configure the
50 * peripheral registers for CPU-native byte order.
52 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
53 return __raw_readl(priv->base + offset);
55 return readl_relaxed(priv->base + offset);
58 static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
61 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
62 __raw_writel(val, priv->base + offset);
64 writel_relaxed(val, priv->base + offset);
67 static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
71 reg = unimac_mdio_readl(priv, MDIO_CMD);
72 reg |= MDIO_START_BUSY;
73 unimac_mdio_writel(priv, reg, MDIO_CMD);
76 static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
78 return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
81 static int unimac_mdio_poll(void *wait_func_data)
83 struct unimac_mdio_priv *priv = wait_func_data;
84 unsigned int timeout = 1000;
87 if (!unimac_mdio_busy(priv))
90 usleep_range(1000, 2000);
96 static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
98 struct unimac_mdio_priv *priv = bus->priv;
102 /* Prepare the read operation */
103 cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
104 unimac_mdio_writel(priv, cmd, MDIO_CMD);
106 /* Start MDIO transaction */
107 unimac_mdio_start(priv);
109 ret = priv->wait_func(priv->wait_func_data);
113 cmd = unimac_mdio_readl(priv, MDIO_CMD);
115 /* Some broken devices are known not to release the line during
116 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
117 * that condition here and ignore the MDIO controller read failure
120 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
126 static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
129 struct unimac_mdio_priv *priv = bus->priv;
132 /* Prepare the write operation */
133 cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
134 (reg << MDIO_REG_SHIFT) | (0xffff & val);
135 unimac_mdio_writel(priv, cmd, MDIO_CMD);
137 unimac_mdio_start(priv);
139 return priv->wait_func(priv->wait_func_data);
142 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
143 * their internal MDIO management controller making them fail to successfully
144 * be read from or written to for the first transaction. We insert a dummy
145 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
146 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
147 * PHY device for this peripheral.
149 * Once the PHY driver is registered, we can workaround subsequent reads from
150 * there (e.g: during system-wide power management).
152 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
153 * therefore the right location to stick that workaround. Since we do not want
154 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
155 * Device Tree scan to limit the search area.
157 static int unimac_mdio_reset(struct mii_bus *bus)
159 struct device_node *np = bus->dev.of_node;
160 struct device_node *child;
165 read_mask = ~bus->phy_mask;
167 for_each_available_child_of_node(np, child) {
168 addr = of_mdio_parse_addr(&bus->dev, child);
172 read_mask |= 1 << addr;
176 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
177 if (read_mask & 1 << addr) {
178 dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
179 mdiobus_read(bus, addr, MII_BMSR);
186 static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
191 /* Keep the hardware default values */
198 rate = clk_get_rate(priv->clk);
200 div = (rate / (2 * priv->clk_freq)) - 1;
201 if (div & ~MDIO_CLK_DIV_MASK) {
202 pr_warn("Incorrect MDIO clock frequency, ignoring\n");
206 /* The MDIO clock is the reference clock (typically 250Mhz) divided by
207 * 2 x (MDIO_CLK_DIV + 1)
209 reg = unimac_mdio_readl(priv, MDIO_CFG);
210 reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
211 reg |= div << MDIO_CLK_DIV_SHIFT;
212 unimac_mdio_writel(priv, reg, MDIO_CFG);
215 static int unimac_mdio_probe(struct platform_device *pdev)
217 struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
218 struct unimac_mdio_priv *priv;
219 struct device_node *np;
224 np = pdev->dev.of_node;
226 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
230 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
234 /* Just ioremap, as this MDIO block is usually integrated into an
235 * Ethernet MAC controller register range
237 priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
239 dev_err(&pdev->dev, "failed to remap register\n");
243 priv->clk = devm_clk_get_optional(&pdev->dev, NULL);
244 if (IS_ERR(priv->clk))
245 return PTR_ERR(priv->clk);
247 ret = clk_prepare_enable(priv->clk);
251 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
254 unimac_mdio_clk_set(priv);
256 priv->mii_bus = mdiobus_alloc();
257 if (!priv->mii_bus) {
259 goto out_clk_disable;
265 bus->name = pdata->bus_name;
266 priv->wait_func = pdata->wait_func;
267 priv->wait_func_data = pdata->wait_func_data;
268 bus->phy_mask = ~pdata->phy_mask;
270 bus->name = "unimac MII bus";
271 priv->wait_func_data = priv;
272 priv->wait_func = unimac_mdio_poll;
274 bus->parent = &pdev->dev;
275 bus->read = unimac_mdio_read;
276 bus->write = unimac_mdio_write;
277 bus->reset = unimac_mdio_reset;
278 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
280 ret = of_mdiobus_register(bus, np);
282 dev_err(&pdev->dev, "MDIO bus registration failed\n");
286 platform_set_drvdata(pdev, priv);
288 dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n");
295 clk_disable_unprepare(priv->clk);
299 static int unimac_mdio_remove(struct platform_device *pdev)
301 struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
303 mdiobus_unregister(priv->mii_bus);
304 mdiobus_free(priv->mii_bus);
305 clk_disable_unprepare(priv->clk);
310 static int __maybe_unused unimac_mdio_suspend(struct device *d)
312 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
314 clk_disable_unprepare(priv->clk);
319 static int __maybe_unused unimac_mdio_resume(struct device *d)
321 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
324 ret = clk_prepare_enable(priv->clk);
328 unimac_mdio_clk_set(priv);
333 static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
334 unimac_mdio_suspend, unimac_mdio_resume);
336 static const struct of_device_id unimac_mdio_ids[] = {
337 { .compatible = "brcm,genet-mdio-v5", },
338 { .compatible = "brcm,genet-mdio-v4", },
339 { .compatible = "brcm,genet-mdio-v3", },
340 { .compatible = "brcm,genet-mdio-v2", },
341 { .compatible = "brcm,genet-mdio-v1", },
342 { .compatible = "brcm,unimac-mdio", },
345 MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
347 static struct platform_driver unimac_mdio_driver = {
349 .name = UNIMAC_MDIO_DRV_NAME,
350 .of_match_table = unimac_mdio_ids,
351 .pm = &unimac_mdio_pm_ops,
353 .probe = unimac_mdio_probe,
354 .remove = unimac_mdio_remove,
356 module_platform_driver(unimac_mdio_driver);
358 MODULE_AUTHOR("Broadcom Corporation");
359 MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
360 MODULE_LICENSE("GPL");
361 MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);