2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/ras.h>
39 #include <linux/smp.h>
42 #include <linux/debugfs.h>
43 #include <linux/irq_work.h>
44 #include <linux/export.h>
45 #include <linux/jump_label.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
54 #include <asm/set_memory.h>
56 #include "mce-internal.h"
58 static DEFINE_MUTEX(mce_log_mutex);
60 /* sysfs synchronization */
61 static DEFINE_MUTEX(mce_sysfs_mutex);
63 #define CREATE_TRACE_POINTS
64 #include <trace/events/mce.h>
66 #define SPINUNIT 100 /* 100ns */
68 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 struct mce_bank *mce_banks __read_mostly;
71 struct mce_vendor_flags mce_flags __read_mostly;
73 struct mca_config mca_cfg __read_mostly = {
77 * 0: always panic on uncorrected errors, log corrected errors
78 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
79 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
80 * 3: never panic or SIGBUS, log all errors (for testing only)
86 static DEFINE_PER_CPU(struct mce, mces_seen);
87 static unsigned long mce_need_notify;
88 static int cpu_missing;
91 * MCA banks polled by the period polling timer for corrected events.
92 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
94 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
95 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
99 * MCA banks controlled through firmware first for corrected errors.
100 * This is a global list of banks for which we won't enable CMCI and we
101 * won't poll. Firmware controls these banks and is responsible for
102 * reporting corrected errors through GHES. Uncorrected/recoverable
103 * errors are still notified through a machine check.
105 mce_banks_t mce_banks_ce_disabled;
107 static struct work_struct mce_work;
108 static struct irq_work mce_irq_work;
110 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
112 #ifndef mce_unmap_kpfn
113 static void mce_unmap_kpfn(unsigned long pfn);
117 * CPU/chipset specific EDAC code can register a notifier call here to print
118 * MCE errors in a human-readable form.
120 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
122 /* Do initial initialization of a struct mce */
123 void mce_setup(struct mce *m)
125 memset(m, 0, sizeof(struct mce));
126 m->cpu = m->extcpu = smp_processor_id();
127 /* We hope get_seconds stays lockless */
128 m->time = get_seconds();
129 m->cpuvendor = boot_cpu_data.x86_vendor;
130 m->cpuid = cpuid_eax(1);
131 m->socketid = cpu_data(m->extcpu).phys_proc_id;
132 m->apicid = cpu_data(m->extcpu).initial_apicid;
133 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
135 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
136 rdmsrl(MSR_PPIN, m->ppin);
138 m->microcode = boot_cpu_data.microcode;
141 DEFINE_PER_CPU(struct mce, injectm);
142 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
144 void mce_log(struct mce *m)
146 if (!mce_gen_pool_add(m))
147 irq_work_queue(&mce_irq_work);
150 void mce_inject_log(struct mce *m)
152 mutex_lock(&mce_log_mutex);
154 mutex_unlock(&mce_log_mutex);
156 EXPORT_SYMBOL_GPL(mce_inject_log);
158 static struct notifier_block mce_srao_nb;
161 * We run the default notifier if we have only the SRAO, the first and the
162 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
163 * notifiers registered on the chain.
165 #define NUM_DEFAULT_NOTIFIERS 3
166 static atomic_t num_notifiers;
168 void mce_register_decode_chain(struct notifier_block *nb)
170 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
173 atomic_inc(&num_notifiers);
175 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
177 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
179 void mce_unregister_decode_chain(struct notifier_block *nb)
181 atomic_dec(&num_notifiers);
183 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
185 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
187 static inline u32 ctl_reg(int bank)
189 return MSR_IA32_MCx_CTL(bank);
192 static inline u32 status_reg(int bank)
194 return MSR_IA32_MCx_STATUS(bank);
197 static inline u32 addr_reg(int bank)
199 return MSR_IA32_MCx_ADDR(bank);
202 static inline u32 misc_reg(int bank)
204 return MSR_IA32_MCx_MISC(bank);
207 static inline u32 smca_ctl_reg(int bank)
209 return MSR_AMD64_SMCA_MCx_CTL(bank);
212 static inline u32 smca_status_reg(int bank)
214 return MSR_AMD64_SMCA_MCx_STATUS(bank);
217 static inline u32 smca_addr_reg(int bank)
219 return MSR_AMD64_SMCA_MCx_ADDR(bank);
222 static inline u32 smca_misc_reg(int bank)
224 return MSR_AMD64_SMCA_MCx_MISC(bank);
227 struct mca_msr_regs msr_ops = {
229 .status = status_reg,
234 static void __print_mce(struct mce *m)
236 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
238 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
239 m->mcgstatus, m->bank, m->status);
242 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
243 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
246 if (m->cs == __KERNEL_CS)
247 print_symbol("{%s}", m->ip);
251 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
253 pr_cont("ADDR %llx ", m->addr);
255 pr_cont("MISC %llx ", m->misc);
257 if (mce_flags.smca) {
259 pr_cont("SYND %llx ", m->synd);
261 pr_cont("IPID %llx ", m->ipid);
266 * Note this output is parsed by external tools and old fields
267 * should not be changed.
269 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
270 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
274 static void print_mce(struct mce *m)
277 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
280 #define PANIC_TIMEOUT 5 /* 5 seconds */
282 static atomic_t mce_panicked;
284 static int fake_panic;
285 static atomic_t mce_fake_panicked;
287 /* Panic in progress. Enable interrupts and wait for final IPI */
288 static void wait_for_panic(void)
290 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
294 while (timeout-- > 0)
296 if (panic_timeout == 0)
297 panic_timeout = mca_cfg.panic_timeout;
298 panic("Panicing machine check CPU died");
301 static void mce_panic(const char *msg, struct mce *final, char *exp)
304 struct llist_node *pending;
305 struct mce_evt_llist *l;
309 * Make sure only one CPU runs in machine check panic
311 if (atomic_inc_return(&mce_panicked) > 1)
318 /* Don't log too much for fake panic */
319 if (atomic_inc_return(&mce_fake_panicked) > 1)
322 pending = mce_gen_pool_prepare_records();
323 /* First print corrected ones that are still unlogged */
324 llist_for_each_entry(l, pending, llnode) {
325 struct mce *m = &l->mce;
326 if (!(m->status & MCI_STATUS_UC)) {
329 apei_err = apei_write_mce(m);
332 /* Now print uncorrected but with the final one last */
333 llist_for_each_entry(l, pending, llnode) {
334 struct mce *m = &l->mce;
335 if (!(m->status & MCI_STATUS_UC))
337 if (!final || mce_cmp(m, final)) {
340 apei_err = apei_write_mce(m);
346 apei_err = apei_write_mce(final);
349 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
351 pr_emerg(HW_ERR "Machine check: %s\n", exp);
353 if (panic_timeout == 0)
354 panic_timeout = mca_cfg.panic_timeout;
357 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
360 /* Support code for software error injection */
362 static int msr_to_offset(u32 msr)
364 unsigned bank = __this_cpu_read(injectm.bank);
366 if (msr == mca_cfg.rip_msr)
367 return offsetof(struct mce, ip);
368 if (msr == msr_ops.status(bank))
369 return offsetof(struct mce, status);
370 if (msr == msr_ops.addr(bank))
371 return offsetof(struct mce, addr);
372 if (msr == msr_ops.misc(bank))
373 return offsetof(struct mce, misc);
374 if (msr == MSR_IA32_MCG_STATUS)
375 return offsetof(struct mce, mcgstatus);
379 /* MSR access wrappers used for error injection */
380 static u64 mce_rdmsrl(u32 msr)
384 if (__this_cpu_read(injectm.finished)) {
385 int offset = msr_to_offset(msr);
389 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
392 if (rdmsrl_safe(msr, &v)) {
393 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
395 * Return zero in case the access faulted. This should
396 * not happen normally but can happen if the CPU does
397 * something weird, or if the code is buggy.
405 static void mce_wrmsrl(u32 msr, u64 v)
407 if (__this_cpu_read(injectm.finished)) {
408 int offset = msr_to_offset(msr);
411 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
418 * Collect all global (w.r.t. this processor) status about this machine
419 * check into our "mce" struct so that we can use it later to assess
420 * the severity of the problem as we read per-bank specific details.
422 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
426 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
429 * Get the address of the instruction at the time of
430 * the machine check error.
432 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
437 * When in VM86 mode make the cs look like ring 3
438 * always. This is a lie, but it's better than passing
439 * the additional vm86 bit around everywhere.
441 if (v8086_mode(regs))
444 /* Use accurate RIP reporting if available. */
446 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
450 int mce_available(struct cpuinfo_x86 *c)
452 if (mca_cfg.disabled)
454 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
457 static void mce_schedule_work(void)
459 if (!mce_gen_pool_empty())
460 schedule_work(&mce_work);
463 static void mce_irq_work_cb(struct irq_work *entry)
468 static void mce_report_event(struct pt_regs *regs)
470 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
473 * Triggering the work queue here is just an insurance
474 * policy in case the syscall exit notify handler
475 * doesn't run soon enough or ends up running on the
476 * wrong CPU (can happen when audit sleeps)
482 irq_work_queue(&mce_irq_work);
486 * Check if the address reported by the CPU is in a format we can parse.
487 * It would be possible to add code for most other cases, but all would
488 * be somewhat complicated (e.g. segment offset would require an instruction
489 * parser). So only support physical addresses up to page granuality for now.
491 static int mce_usable_address(struct mce *m)
493 if (!(m->status & MCI_STATUS_ADDRV))
496 /* Checks after this one are Intel-specific: */
497 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
500 if (!(m->status & MCI_STATUS_MISCV))
503 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
506 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
512 bool mce_is_memory_error(struct mce *m)
514 if (m->cpuvendor == X86_VENDOR_AMD) {
515 return amd_mce_is_memory_error(m);
517 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
519 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
521 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
522 * indicating a memory error. Bit 8 is used for indicating a
523 * cache hierarchy error. The combination of bit 2 and bit 3
524 * is used for indicating a `generic' cache hierarchy error
525 * But we can't just blindly check the above bits, because if
526 * bit 11 is set, then it is a bus/interconnect error - and
527 * either way the above bits just gives more detail on what
528 * bus/interconnect error happened. Note that bit 12 can be
529 * ignored, as it's the "filter" bit.
531 return (m->status & 0xef80) == BIT(7) ||
532 (m->status & 0xef00) == BIT(8) ||
533 (m->status & 0xeffc) == 0xc;
538 EXPORT_SYMBOL_GPL(mce_is_memory_error);
540 static bool cec_add_mce(struct mce *m)
545 /* We eat only correctable DRAM errors with usable addresses. */
546 if (mce_is_memory_error(m) &&
547 !(m->status & MCI_STATUS_UC) &&
548 mce_usable_address(m))
549 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
555 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
558 struct mce *m = (struct mce *)data;
566 /* Emit the trace record: */
569 set_bit(0, &mce_need_notify);
576 static struct notifier_block first_nb = {
577 .notifier_call = mce_first_notifier,
578 .priority = MCE_PRIO_FIRST,
581 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
584 struct mce *mce = (struct mce *)data;
590 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
591 pfn = mce->addr >> PAGE_SHIFT;
592 if (!memory_failure(pfn, MCE_VECTOR, 0))
598 static struct notifier_block mce_srao_nb = {
599 .notifier_call = srao_decode_notifier,
600 .priority = MCE_PRIO_SRAO,
603 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
606 struct mce *m = (struct mce *)data;
611 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
619 static struct notifier_block mce_default_nb = {
620 .notifier_call = mce_default_notifier,
621 /* lowest prio, we want it to run last. */
622 .priority = MCE_PRIO_LOWEST,
626 * Read ADDR and MISC registers.
628 static void mce_read_aux(struct mce *m, int i)
630 if (m->status & MCI_STATUS_MISCV)
631 m->misc = mce_rdmsrl(msr_ops.misc(i));
633 if (m->status & MCI_STATUS_ADDRV) {
634 m->addr = mce_rdmsrl(msr_ops.addr(i));
637 * Mask the reported address by the reported granularity.
639 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
640 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
646 * Extract [55:<lsb>] where lsb is the least significant
647 * *valid* bit of the address bits.
649 if (mce_flags.smca) {
650 u8 lsb = (m->addr >> 56) & 0x3f;
652 m->addr &= GENMASK_ULL(55, lsb);
656 if (mce_flags.smca) {
657 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
659 if (m->status & MCI_STATUS_SYNDV)
660 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
664 DEFINE_PER_CPU(unsigned, mce_poll_count);
667 * Poll for corrected events or events that happened before reset.
668 * Those are just logged through /dev/mcelog.
670 * This is executed in standard interrupt context.
672 * Note: spec recommends to panic for fatal unsignalled
673 * errors here. However this would be quite problematic --
674 * we would need to reimplement the Monarch handling and
675 * it would mess up the exclusion between exception handler
676 * and poll hander -- * so we skip this for now.
677 * These cases should not happen anyways, or only when the CPU
678 * is already totally * confused. In this case it's likely it will
679 * not fully execute the machine check handler either.
681 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
683 bool error_seen = false;
687 this_cpu_inc(mce_poll_count);
689 mce_gather_info(&m, NULL);
691 if (flags & MCP_TIMESTAMP)
694 for (i = 0; i < mca_cfg.banks; i++) {
695 if (!mce_banks[i].ctl || !test_bit(i, *b))
703 m.status = mce_rdmsrl(msr_ops.status(i));
705 /* If this entry is not valid, ignore it */
706 if (!(m.status & MCI_STATUS_VAL))
710 * If we are logging everything (at CPU online) or this
711 * is a corrected error, then we must log it.
713 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
717 * Newer Intel systems that support software error
718 * recovery need to make additional checks. Other
719 * CPUs should skip over uncorrected errors, but log
723 if (m.status & MCI_STATUS_UC)
728 /* Log "not enabled" (speculative) errors */
729 if (!(m.status & MCI_STATUS_EN))
733 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
734 * UC == 1 && PCC == 0 && S == 0
736 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
740 * Skip anything else. Presumption is that our read of this
741 * bank is racing with a machine check. Leave the log alone
742 * for do_machine_check() to deal with it.
751 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
754 * Don't get the IP here because it's unlikely to
755 * have anything to do with the actual error location.
757 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
759 else if (mce_usable_address(&m)) {
761 * Although we skipped logging this, we still want
762 * to take action. Add to the pool so the registered
763 * notifiers will see it.
765 if (!mce_gen_pool_add(&m))
770 * Clear state for this bank.
772 mce_wrmsrl(msr_ops.status(i), 0);
776 * Don't clear MCG_STATUS here because it's only defined for
784 EXPORT_SYMBOL_GPL(machine_check_poll);
787 * Do a quick check if any of the events requires a panic.
788 * This decides if we keep the events around or clear them.
790 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
791 struct pt_regs *regs)
796 for (i = 0; i < mca_cfg.banks; i++) {
797 m->status = mce_rdmsrl(msr_ops.status(i));
798 if (!(m->status & MCI_STATUS_VAL))
801 __set_bit(i, validp);
802 if (quirk_no_way_out)
803 quirk_no_way_out(i, m, regs);
806 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
816 * Variable to establish order between CPUs while scanning.
817 * Each CPU spins initially until executing is equal its number.
819 static atomic_t mce_executing;
822 * Defines order of CPUs on entry. First CPU becomes Monarch.
824 static atomic_t mce_callin;
827 * Check if a timeout waiting for other CPUs happened.
829 static int mce_timed_out(u64 *t, const char *msg)
832 * The others already did panic for some reason.
833 * Bail out like in a timeout.
834 * rmb() to tell the compiler that system_state
835 * might have been modified by someone else.
838 if (atomic_read(&mce_panicked))
840 if (!mca_cfg.monarch_timeout)
842 if ((s64)*t < SPINUNIT) {
843 if (mca_cfg.tolerant <= 1)
844 mce_panic(msg, NULL, NULL);
850 touch_nmi_watchdog();
855 * The Monarch's reign. The Monarch is the CPU who entered
856 * the machine check handler first. It waits for the others to
857 * raise the exception too and then grades them. When any
858 * error is fatal panic. Only then let the others continue.
860 * The other CPUs entering the MCE handler will be controlled by the
861 * Monarch. They are called Subjects.
863 * This way we prevent any potential data corruption in a unrecoverable case
864 * and also makes sure always all CPU's errors are examined.
866 * Also this detects the case of a machine check event coming from outer
867 * space (not detected by any CPUs) In this case some external agent wants
868 * us to shut down, so panic too.
870 * The other CPUs might still decide to panic if the handler happens
871 * in a unrecoverable place, but in this case the system is in a semi-stable
872 * state and won't corrupt anything by itself. It's ok to let the others
873 * continue for a bit first.
875 * All the spin loops have timeouts; when a timeout happens a CPU
876 * typically elects itself to be Monarch.
878 static void mce_reign(void)
881 struct mce *m = NULL;
882 int global_worst = 0;
887 * This CPU is the Monarch and the other CPUs have run
888 * through their handlers.
889 * Grade the severity of the errors of all the CPUs.
891 for_each_possible_cpu(cpu) {
892 int severity = mce_severity(&per_cpu(mces_seen, cpu),
895 if (severity > global_worst) {
897 global_worst = severity;
898 m = &per_cpu(mces_seen, cpu);
903 * Cannot recover? Panic here then.
904 * This dumps all the mces in the log buffer and stops the
907 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
908 mce_panic("Fatal machine check", m, msg);
911 * For UC somewhere we let the CPU who detects it handle it.
912 * Also must let continue the others, otherwise the handling
913 * CPU could deadlock on a lock.
917 * No machine check event found. Must be some external
918 * source or one CPU is hung. Panic.
920 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
921 mce_panic("Fatal machine check from unknown source", NULL, NULL);
924 * Now clear all the mces_seen so that they don't reappear on
927 for_each_possible_cpu(cpu)
928 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
931 static atomic_t global_nwo;
934 * Start of Monarch synchronization. This waits until all CPUs have
935 * entered the exception handler and then determines if any of them
936 * saw a fatal event that requires panic. Then it executes them
937 * in the entry order.
938 * TBD double check parallel CPU hotunplug
940 static int mce_start(int *no_way_out)
943 int cpus = num_online_cpus();
944 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
949 atomic_add(*no_way_out, &global_nwo);
951 * Rely on the implied barrier below, such that global_nwo
952 * is updated before mce_callin.
954 order = atomic_inc_return(&mce_callin);
959 while (atomic_read(&mce_callin) != cpus) {
960 if (mce_timed_out(&timeout,
961 "Timeout: Not all CPUs entered broadcast exception handler")) {
962 atomic_set(&global_nwo, 0);
969 * mce_callin should be read before global_nwo
975 * Monarch: Starts executing now, the others wait.
977 atomic_set(&mce_executing, 1);
980 * Subject: Now start the scanning loop one by one in
981 * the original callin order.
982 * This way when there are any shared banks it will be
983 * only seen by one CPU before cleared, avoiding duplicates.
985 while (atomic_read(&mce_executing) < order) {
986 if (mce_timed_out(&timeout,
987 "Timeout: Subject CPUs unable to finish machine check processing")) {
988 atomic_set(&global_nwo, 0);
996 * Cache the global no_way_out state.
998 *no_way_out = atomic_read(&global_nwo);
1004 * Synchronize between CPUs after main scanning loop.
1005 * This invokes the bulk of the Monarch processing.
1007 static int mce_end(int order)
1010 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1018 * Allow others to run.
1020 atomic_inc(&mce_executing);
1023 /* CHECKME: Can this race with a parallel hotplug? */
1024 int cpus = num_online_cpus();
1027 * Monarch: Wait for everyone to go through their scanning
1030 while (atomic_read(&mce_executing) <= cpus) {
1031 if (mce_timed_out(&timeout,
1032 "Timeout: Monarch CPU unable to finish machine check processing"))
1042 * Subject: Wait for Monarch to finish.
1044 while (atomic_read(&mce_executing) != 0) {
1045 if (mce_timed_out(&timeout,
1046 "Timeout: Monarch CPU did not finish machine check processing"))
1052 * Don't reset anything. That's done by the Monarch.
1058 * Reset all global state.
1061 atomic_set(&global_nwo, 0);
1062 atomic_set(&mce_callin, 0);
1066 * Let others run again.
1068 atomic_set(&mce_executing, 0);
1072 static void mce_clear_state(unsigned long *toclear)
1076 for (i = 0; i < mca_cfg.banks; i++) {
1077 if (test_bit(i, toclear))
1078 mce_wrmsrl(msr_ops.status(i), 0);
1082 static int do_memory_failure(struct mce *m)
1084 int flags = MF_ACTION_REQUIRED;
1087 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1088 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1089 flags |= MF_MUST_KILL;
1090 ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags);
1092 pr_err("Memory error not recovered");
1094 mce_unmap_kpfn(m->addr >> PAGE_SHIFT);
1098 #ifndef mce_unmap_kpfn
1099 static void mce_unmap_kpfn(unsigned long pfn)
1101 unsigned long decoy_addr;
1104 * Unmap this page from the kernel 1:1 mappings to make sure
1105 * we don't log more errors because of speculative access to
1107 * We would like to just call:
1108 * set_memory_np((unsigned long)pfn_to_kaddr(pfn), 1);
1109 * but doing that would radically increase the odds of a
1110 * speculative access to the poison page because we'd have
1111 * the virtual address of the kernel 1:1 mapping sitting
1112 * around in registers.
1113 * Instead we get tricky. We create a non-canonical address
1114 * that looks just like the one we want, but has bit 63 flipped.
1115 * This relies on set_memory_np() not checking whether we passed
1120 * Build time check to see if we have a spare virtual bit. Don't want
1121 * to leave this until run time because most developers don't have a
1122 * system that can exercise this code path. This will only become a
1123 * problem if/when we move beyond 5-level page tables.
1125 * Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD)
1127 #if PGDIR_SHIFT + 9 < 63
1128 decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
1130 #error "no unused virtual bit available"
1133 if (set_memory_np(decoy_addr, 1))
1134 pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
1139 * The actual machine check handler. This only handles real
1140 * exceptions when something got corrupted coming in through int 18.
1142 * This is executed in NMI context not subject to normal locking rules. This
1143 * implies that most kernel services cannot be safely used. Don't even
1144 * think about putting a printk in there!
1146 * On Intel systems this is entered on all CPUs in parallel through
1147 * MCE broadcast. However some CPUs might be broken beyond repair,
1148 * so be always careful when synchronizing with others.
1150 void do_machine_check(struct pt_regs *regs, long error_code)
1152 struct mca_config *cfg = &mca_cfg;
1153 struct mce m, *final;
1159 * Establish sequential order between the CPUs entering the machine
1164 * If no_way_out gets set, there is no safe way to recover from this
1165 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1169 * If kill_it gets set, there might be a way to recover from this
1173 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1174 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1175 char *msg = "Unknown";
1178 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1182 int cpu = smp_processor_id();
1185 * Cases where we avoid rendezvous handler timeout:
1186 * 1) If this CPU is offline.
1188 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1189 * skip those CPUs which remain looping in the 1st kernel - see
1190 * crash_nmi_callback().
1192 * Note: there still is a small window between kexec-ing and the new,
1193 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1194 * might not get handled properly.
1196 if (cpu_is_offline(cpu) ||
1197 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1200 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1201 if (mcgstatus & MCG_STATUS_RIPV) {
1202 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1209 this_cpu_inc(mce_exception_count);
1214 mce_gather_info(&m, regs);
1217 final = this_cpu_ptr(&mces_seen);
1220 memset(valid_banks, 0, sizeof(valid_banks));
1221 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1226 * When no restart IP might need to kill or panic.
1227 * Assume the worst for now, but if we find the
1228 * severity is MCE_AR_SEVERITY we have other options.
1230 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1234 * Check if this MCE is signaled to only this logical processor,
1237 if (m.cpuvendor == X86_VENDOR_INTEL)
1238 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1241 * Local machine check may already know that we have to panic.
1242 * Broadcast machine check begins rendezvous in mce_start()
1243 * Go through all banks in exclusion of the other CPUs. This way we
1244 * don't report duplicated events on shared banks because the first one
1245 * to see it will clear it.
1249 mce_panic("Fatal local machine check", &m, msg);
1251 order = mce_start(&no_way_out);
1254 for (i = 0; i < cfg->banks; i++) {
1255 __clear_bit(i, toclear);
1256 if (!test_bit(i, valid_banks))
1258 if (!mce_banks[i].ctl)
1265 m.status = mce_rdmsrl(msr_ops.status(i));
1266 if ((m.status & MCI_STATUS_VAL) == 0)
1270 * Non uncorrected or non signaled errors are handled by
1271 * machine_check_poll. Leave them alone, unless this panics.
1273 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1278 * Set taint even when machine check was not enabled.
1280 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1282 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1285 * When machine check was for corrected/deferred handler don't
1286 * touch, unless we're panicing.
1288 if ((severity == MCE_KEEP_SEVERITY ||
1289 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1291 __set_bit(i, toclear);
1292 if (severity == MCE_NO_SEVERITY) {
1294 * Machine check event was not enabled. Clear, but
1300 mce_read_aux(&m, i);
1302 /* assuming valid severity level != 0 */
1303 m.severity = severity;
1307 if (severity > worst) {
1313 /* mce_clear_state will clear *final, save locally for use later */
1317 mce_clear_state(toclear);
1320 * Do most of the synchronization with other CPUs.
1321 * When there's any problem use only local no_way_out state.
1324 if (mce_end(order) < 0)
1325 no_way_out = worst >= MCE_PANIC_SEVERITY;
1328 * If there was a fatal machine check we should have
1329 * already called mce_panic earlier in this function.
1330 * Since we re-read the banks, we might have found
1331 * something new. Check again to see if we found a
1332 * fatal error. We call "mce_severity()" again to
1333 * make sure we have the right "msg".
1335 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1336 mce_severity(&m, cfg->tolerant, &msg, true);
1337 mce_panic("Local fatal machine check!", &m, msg);
1342 * If tolerant is at an insane level we drop requests to kill
1343 * processes and continue even when there is no way out.
1345 if (cfg->tolerant == 3)
1347 else if (no_way_out)
1348 mce_panic("Fatal machine check on current CPU", &m, msg);
1351 mce_report_event(regs);
1352 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1356 if (worst != MCE_AR_SEVERITY && !kill_it)
1359 /* Fault was in user mode and we need to take some action */
1360 if ((m.cs & 3) == 3) {
1361 ist_begin_non_atomic(regs);
1364 if (kill_it || do_memory_failure(&m))
1365 force_sig(SIGBUS, current);
1366 local_irq_disable();
1367 ist_end_non_atomic();
1369 if (!fixup_exception(regs, X86_TRAP_MC))
1370 mce_panic("Failed kernel mode recovery", &m, NULL);
1376 EXPORT_SYMBOL_GPL(do_machine_check);
1378 #ifndef CONFIG_MEMORY_FAILURE
1379 int memory_failure(unsigned long pfn, int vector, int flags)
1381 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1382 BUG_ON(flags & MF_ACTION_REQUIRED);
1383 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1384 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1392 * Periodic polling timer for "silent" machine check errors. If the
1393 * poller finds an MCE, poll 2x faster. When the poller finds no more
1394 * errors, poll 2x slower (up to check_interval seconds).
1396 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1398 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1399 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1401 static unsigned long mce_adjust_timer_default(unsigned long interval)
1406 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1408 static void __start_timer(struct timer_list *t, unsigned long interval)
1410 unsigned long when = jiffies + interval;
1411 unsigned long flags;
1413 local_irq_save(flags);
1415 if (!timer_pending(t) || time_before(when, t->expires))
1416 mod_timer(t, round_jiffies(when));
1418 local_irq_restore(flags);
1421 static void mce_timer_fn(unsigned long data)
1423 struct timer_list *t = this_cpu_ptr(&mce_timer);
1424 int cpu = smp_processor_id();
1427 WARN_ON(cpu != data);
1429 iv = __this_cpu_read(mce_next_interval);
1431 if (mce_available(this_cpu_ptr(&cpu_info))) {
1432 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1434 if (mce_intel_cmci_poll()) {
1435 iv = mce_adjust_timer(iv);
1441 * Alert userspace if needed. If we logged an MCE, reduce the polling
1442 * interval, otherwise increase the polling interval.
1444 if (mce_notify_irq())
1445 iv = max(iv / 2, (unsigned long) HZ/100);
1447 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1450 __this_cpu_write(mce_next_interval, iv);
1451 __start_timer(t, iv);
1455 * Ensure that the timer is firing in @interval from now.
1457 void mce_timer_kick(unsigned long interval)
1459 struct timer_list *t = this_cpu_ptr(&mce_timer);
1460 unsigned long iv = __this_cpu_read(mce_next_interval);
1462 __start_timer(t, interval);
1465 __this_cpu_write(mce_next_interval, interval);
1468 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1469 static void mce_timer_delete_all(void)
1473 for_each_online_cpu(cpu)
1474 del_timer_sync(&per_cpu(mce_timer, cpu));
1478 * Notify the user(s) about new machine check events.
1479 * Can be called from interrupt context, but not from machine check/NMI
1482 int mce_notify_irq(void)
1484 /* Not more than two messages every minute */
1485 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1487 if (test_and_clear_bit(0, &mce_need_notify)) {
1490 if (__ratelimit(&ratelimit))
1491 pr_info(HW_ERR "Machine check events logged\n");
1497 EXPORT_SYMBOL_GPL(mce_notify_irq);
1499 static int __mcheck_cpu_mce_banks_init(void)
1503 mce_banks = kcalloc(MAX_NR_BANKS, sizeof(struct mce_bank), GFP_KERNEL);
1507 for (i = 0; i < MAX_NR_BANKS; i++) {
1508 struct mce_bank *b = &mce_banks[i];
1517 * Initialize Machine Checks for a CPU.
1519 static int __mcheck_cpu_cap_init(void)
1524 rdmsrl(MSR_IA32_MCG_CAP, cap);
1526 b = cap & MCG_BANKCNT_MASK;
1527 if (WARN_ON_ONCE(b > MAX_NR_BANKS))
1530 mca_cfg.banks = max(mca_cfg.banks, b);
1533 int err = __mcheck_cpu_mce_banks_init();
1538 /* Use accurate RIP reporting if available. */
1539 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1540 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1542 if (cap & MCG_SER_P)
1548 static void __mcheck_cpu_init_generic(void)
1550 enum mcp_flags m_fl = 0;
1551 mce_banks_t all_banks;
1554 if (!mca_cfg.bootlog)
1558 * Log the machine checks left over from the previous reset.
1560 bitmap_fill(all_banks, MAX_NR_BANKS);
1561 machine_check_poll(MCP_UC | m_fl, &all_banks);
1563 cr4_set_bits(X86_CR4_MCE);
1565 rdmsrl(MSR_IA32_MCG_CAP, cap);
1566 if (cap & MCG_CTL_P)
1567 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1570 static void __mcheck_cpu_init_clear_banks(void)
1574 for (i = 0; i < mca_cfg.banks; i++) {
1575 struct mce_bank *b = &mce_banks[i];
1579 wrmsrl(msr_ops.ctl(i), b->ctl);
1580 wrmsrl(msr_ops.status(i), 0);
1585 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1586 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1587 * Vol 3B Table 15-20). But this confuses both the code that determines
1588 * whether the machine check occurred in kernel or user mode, and also
1589 * the severity assessment code. Pretend that EIPV was set, and take the
1590 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1592 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1596 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1598 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1599 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1600 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1602 (MCI_STATUS_UC|MCI_STATUS_EN|
1603 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1604 MCI_STATUS_AR|MCACOD_INSTR))
1607 m->mcgstatus |= MCG_STATUS_EIPV;
1612 /* Add per CPU specific workarounds here */
1613 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1615 struct mca_config *cfg = &mca_cfg;
1617 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1618 pr_info("unknown CPU type - not enabling MCE support\n");
1622 /* This should be disabled by the BIOS, but isn't always */
1623 if (c->x86_vendor == X86_VENDOR_AMD) {
1624 if (c->x86 == 15 && cfg->banks > 4) {
1626 * disable GART TBL walk error reporting, which
1627 * trips off incorrectly with the IOMMU & 3ware
1630 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1632 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1634 * Lots of broken BIOS around that don't clear them
1635 * by default and leave crap in there. Don't log:
1640 * Various K7s with broken bank 0 around. Always disable
1643 if (c->x86 == 6 && cfg->banks > 0)
1644 mce_banks[0].ctl = 0;
1647 * overflow_recov is supported for F15h Models 00h-0fh
1648 * even though we don't have a CPUID bit for it.
1650 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1651 mce_flags.overflow_recov = 1;
1655 if (c->x86_vendor == X86_VENDOR_INTEL) {
1657 * SDM documents that on family 6 bank 0 should not be written
1658 * because it aliases to another special BIOS controlled
1660 * But it's not aliased anymore on model 0x1a+
1661 * Don't ignore bank 0 completely because there could be a
1662 * valid event later, merely don't write CTL0.
1665 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1666 mce_banks[0].init = 0;
1669 * All newer Intel systems support MCE broadcasting. Enable
1670 * synchronization with a one second timeout.
1672 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1673 cfg->monarch_timeout < 0)
1674 cfg->monarch_timeout = USEC_PER_SEC;
1677 * There are also broken BIOSes on some Pentium M and
1680 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1683 if (c->x86 == 6 && c->x86_model == 45)
1684 quirk_no_way_out = quirk_sandybridge_ifu;
1686 if (cfg->monarch_timeout < 0)
1687 cfg->monarch_timeout = 0;
1688 if (cfg->bootlog != 0)
1689 cfg->panic_timeout = 30;
1694 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1699 switch (c->x86_vendor) {
1700 case X86_VENDOR_INTEL:
1701 intel_p5_mcheck_init(c);
1704 case X86_VENDOR_CENTAUR:
1705 winchip_mcheck_init(c);
1716 * Init basic CPU features needed for early decoding of MCEs.
1718 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1720 if (c->x86_vendor == X86_VENDOR_AMD) {
1721 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1722 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1723 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1725 if (mce_flags.smca) {
1726 msr_ops.ctl = smca_ctl_reg;
1727 msr_ops.status = smca_status_reg;
1728 msr_ops.addr = smca_addr_reg;
1729 msr_ops.misc = smca_misc_reg;
1734 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1736 switch (c->x86_vendor) {
1737 case X86_VENDOR_INTEL:
1738 mce_intel_feature_init(c);
1739 mce_adjust_timer = cmci_intel_adjust_timer;
1742 case X86_VENDOR_AMD: {
1743 mce_amd_feature_init(c);
1752 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1754 switch (c->x86_vendor) {
1755 case X86_VENDOR_INTEL:
1756 mce_intel_feature_clear(c);
1763 static void mce_start_timer(struct timer_list *t)
1765 unsigned long iv = check_interval * HZ;
1767 if (mca_cfg.ignore_ce || !iv)
1770 this_cpu_write(mce_next_interval, iv);
1771 __start_timer(t, iv);
1774 static void __mcheck_cpu_setup_timer(void)
1776 struct timer_list *t = this_cpu_ptr(&mce_timer);
1777 unsigned int cpu = smp_processor_id();
1779 setup_pinned_timer(t, mce_timer_fn, cpu);
1782 static void __mcheck_cpu_init_timer(void)
1784 struct timer_list *t = this_cpu_ptr(&mce_timer);
1785 unsigned int cpu = smp_processor_id();
1787 setup_pinned_timer(t, mce_timer_fn, cpu);
1791 /* Handle unconfigured int18 (should never happen) */
1792 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1794 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1795 smp_processor_id());
1798 /* Call the installed machine check handler for this CPU setup. */
1799 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1800 unexpected_machine_check;
1802 dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1804 machine_check_vector(regs, error_code);
1808 * Called for each booted CPU to set up machine checks.
1809 * Must be called with preempt off:
1811 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1813 if (mca_cfg.disabled)
1816 if (__mcheck_cpu_ancient_init(c))
1819 if (!mce_available(c))
1822 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1823 mca_cfg.disabled = true;
1827 if (mce_gen_pool_init()) {
1828 mca_cfg.disabled = true;
1829 pr_emerg("Couldn't allocate MCE records pool!\n");
1833 machine_check_vector = do_machine_check;
1835 __mcheck_cpu_init_early(c);
1836 __mcheck_cpu_init_generic();
1837 __mcheck_cpu_init_vendor(c);
1838 __mcheck_cpu_init_clear_banks();
1839 __mcheck_cpu_setup_timer();
1843 * Called for each booted CPU to clear some machine checks opt-ins
1845 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1847 if (mca_cfg.disabled)
1850 if (!mce_available(c))
1854 * Possibly to clear general settings generic to x86
1855 * __mcheck_cpu_clear_generic(c);
1857 __mcheck_cpu_clear_vendor(c);
1861 static void __mce_disable_bank(void *arg)
1863 int bank = *((int *)arg);
1864 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1865 cmci_disable_bank(bank);
1868 void mce_disable_bank(int bank)
1870 if (bank >= mca_cfg.banks) {
1872 "Ignoring request to disable invalid MCA bank %d.\n",
1876 set_bit(bank, mce_banks_ce_disabled);
1877 on_each_cpu(__mce_disable_bank, &bank, 1);
1881 * mce=off Disables machine check
1882 * mce=no_cmci Disables CMCI
1883 * mce=no_lmce Disables LMCE
1884 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1885 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1886 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1887 * monarchtimeout is how long to wait for other CPUs on machine
1888 * check, or 0 to not wait
1889 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1891 * mce=nobootlog Don't log MCEs from before booting.
1892 * mce=bios_cmci_threshold Don't program the CMCI threshold
1893 * mce=recovery force enable memcpy_mcsafe()
1895 static int __init mcheck_enable(char *str)
1897 struct mca_config *cfg = &mca_cfg;
1905 if (!strcmp(str, "off"))
1906 cfg->disabled = true;
1907 else if (!strcmp(str, "no_cmci"))
1908 cfg->cmci_disabled = true;
1909 else if (!strcmp(str, "no_lmce"))
1910 cfg->lmce_disabled = true;
1911 else if (!strcmp(str, "dont_log_ce"))
1912 cfg->dont_log_ce = true;
1913 else if (!strcmp(str, "ignore_ce"))
1914 cfg->ignore_ce = true;
1915 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1916 cfg->bootlog = (str[0] == 'b');
1917 else if (!strcmp(str, "bios_cmci_threshold"))
1918 cfg->bios_cmci_threshold = true;
1919 else if (!strcmp(str, "recovery"))
1920 cfg->recovery = true;
1921 else if (isdigit(str[0])) {
1922 if (get_option(&str, &cfg->tolerant) == 2)
1923 get_option(&str, &(cfg->monarch_timeout));
1925 pr_info("mce argument %s ignored. Please use /sys\n", str);
1930 __setup("mce", mcheck_enable);
1932 int __init mcheck_init(void)
1934 mcheck_intel_therm_init();
1935 mce_register_decode_chain(&first_nb);
1936 mce_register_decode_chain(&mce_srao_nb);
1937 mce_register_decode_chain(&mce_default_nb);
1938 mcheck_vendor_init_severity();
1940 INIT_WORK(&mce_work, mce_gen_pool_process);
1941 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1947 * mce_syscore: PM support
1951 * Disable machine checks on suspend and shutdown. We can't really handle
1954 static void mce_disable_error_reporting(void)
1958 for (i = 0; i < mca_cfg.banks; i++) {
1959 struct mce_bank *b = &mce_banks[i];
1962 wrmsrl(msr_ops.ctl(i), 0);
1967 static void vendor_disable_error_reporting(void)
1970 * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
1971 * Disabling them for just a single offlined CPU is bad, since it will
1972 * inhibit reporting for all shared resources on the socket like the
1973 * last level cache (LLC), the integrated memory controller (iMC), etc.
1975 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1976 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1979 mce_disable_error_reporting();
1982 static int mce_syscore_suspend(void)
1984 vendor_disable_error_reporting();
1988 static void mce_syscore_shutdown(void)
1990 vendor_disable_error_reporting();
1994 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1995 * Only one CPU is active at this time, the others get re-added later using
1998 static void mce_syscore_resume(void)
2000 __mcheck_cpu_init_generic();
2001 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2002 __mcheck_cpu_init_clear_banks();
2005 static struct syscore_ops mce_syscore_ops = {
2006 .suspend = mce_syscore_suspend,
2007 .shutdown = mce_syscore_shutdown,
2008 .resume = mce_syscore_resume,
2012 * mce_device: Sysfs support
2015 static void mce_cpu_restart(void *data)
2017 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2019 __mcheck_cpu_init_generic();
2020 __mcheck_cpu_init_clear_banks();
2021 __mcheck_cpu_init_timer();
2024 /* Reinit MCEs after user configuration changes */
2025 static void mce_restart(void)
2027 mce_timer_delete_all();
2028 on_each_cpu(mce_cpu_restart, NULL, 1);
2031 /* Toggle features for corrected errors */
2032 static void mce_disable_cmci(void *data)
2034 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2039 static void mce_enable_ce(void *all)
2041 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2046 __mcheck_cpu_init_timer();
2049 static struct bus_type mce_subsys = {
2050 .name = "machinecheck",
2051 .dev_name = "machinecheck",
2054 DEFINE_PER_CPU(struct device *, mce_device);
2056 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2058 return container_of(attr, struct mce_bank, attr);
2061 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2064 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2067 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2068 const char *buf, size_t size)
2072 if (kstrtou64(buf, 0, &new) < 0)
2075 attr_to_bank(attr)->ctl = new;
2081 static ssize_t set_ignore_ce(struct device *s,
2082 struct device_attribute *attr,
2083 const char *buf, size_t size)
2087 if (kstrtou64(buf, 0, &new) < 0)
2090 mutex_lock(&mce_sysfs_mutex);
2091 if (mca_cfg.ignore_ce ^ !!new) {
2093 /* disable ce features */
2094 mce_timer_delete_all();
2095 on_each_cpu(mce_disable_cmci, NULL, 1);
2096 mca_cfg.ignore_ce = true;
2098 /* enable ce features */
2099 mca_cfg.ignore_ce = false;
2100 on_each_cpu(mce_enable_ce, (void *)1, 1);
2103 mutex_unlock(&mce_sysfs_mutex);
2108 static ssize_t set_cmci_disabled(struct device *s,
2109 struct device_attribute *attr,
2110 const char *buf, size_t size)
2114 if (kstrtou64(buf, 0, &new) < 0)
2117 mutex_lock(&mce_sysfs_mutex);
2118 if (mca_cfg.cmci_disabled ^ !!new) {
2121 on_each_cpu(mce_disable_cmci, NULL, 1);
2122 mca_cfg.cmci_disabled = true;
2125 mca_cfg.cmci_disabled = false;
2126 on_each_cpu(mce_enable_ce, NULL, 1);
2129 mutex_unlock(&mce_sysfs_mutex);
2134 static ssize_t store_int_with_restart(struct device *s,
2135 struct device_attribute *attr,
2136 const char *buf, size_t size)
2138 unsigned long old_check_interval = check_interval;
2139 ssize_t ret = device_store_ulong(s, attr, buf, size);
2141 if (check_interval == old_check_interval)
2144 mutex_lock(&mce_sysfs_mutex);
2146 mutex_unlock(&mce_sysfs_mutex);
2151 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2152 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2153 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2155 static struct dev_ext_attribute dev_attr_check_interval = {
2156 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2160 static struct dev_ext_attribute dev_attr_ignore_ce = {
2161 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2165 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2166 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2167 &mca_cfg.cmci_disabled
2170 static struct device_attribute *mce_device_attrs[] = {
2171 &dev_attr_tolerant.attr,
2172 &dev_attr_check_interval.attr,
2173 #ifdef CONFIG_X86_MCELOG_LEGACY
2176 &dev_attr_monarch_timeout.attr,
2177 &dev_attr_dont_log_ce.attr,
2178 &dev_attr_ignore_ce.attr,
2179 &dev_attr_cmci_disabled.attr,
2183 static cpumask_var_t mce_device_initialized;
2185 static void mce_device_release(struct device *dev)
2190 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2191 static int mce_device_create(unsigned int cpu)
2197 if (!mce_available(&boot_cpu_data))
2200 dev = per_cpu(mce_device, cpu);
2204 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2208 dev->bus = &mce_subsys;
2209 dev->release = &mce_device_release;
2211 err = device_register(dev);
2217 for (i = 0; mce_device_attrs[i]; i++) {
2218 err = device_create_file(dev, mce_device_attrs[i]);
2222 for (j = 0; j < mca_cfg.banks; j++) {
2223 err = device_create_file(dev, &mce_banks[j].attr);
2227 cpumask_set_cpu(cpu, mce_device_initialized);
2228 per_cpu(mce_device, cpu) = dev;
2233 device_remove_file(dev, &mce_banks[j].attr);
2236 device_remove_file(dev, mce_device_attrs[i]);
2238 device_unregister(dev);
2243 static void mce_device_remove(unsigned int cpu)
2245 struct device *dev = per_cpu(mce_device, cpu);
2248 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2251 for (i = 0; mce_device_attrs[i]; i++)
2252 device_remove_file(dev, mce_device_attrs[i]);
2254 for (i = 0; i < mca_cfg.banks; i++)
2255 device_remove_file(dev, &mce_banks[i].attr);
2257 device_unregister(dev);
2258 cpumask_clear_cpu(cpu, mce_device_initialized);
2259 per_cpu(mce_device, cpu) = NULL;
2262 /* Make sure there are no machine checks on offlined CPUs. */
2263 static void mce_disable_cpu(void)
2265 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2268 if (!cpuhp_tasks_frozen)
2271 vendor_disable_error_reporting();
2274 static void mce_reenable_cpu(void)
2278 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2281 if (!cpuhp_tasks_frozen)
2283 for (i = 0; i < mca_cfg.banks; i++) {
2284 struct mce_bank *b = &mce_banks[i];
2287 wrmsrl(msr_ops.ctl(i), b->ctl);
2291 static int mce_cpu_dead(unsigned int cpu)
2293 mce_intel_hcpu_update(cpu);
2295 /* intentionally ignoring frozen here */
2296 if (!cpuhp_tasks_frozen)
2301 static int mce_cpu_online(unsigned int cpu)
2303 struct timer_list *t = this_cpu_ptr(&mce_timer);
2306 mce_device_create(cpu);
2308 ret = mce_threshold_create_device(cpu);
2310 mce_device_remove(cpu);
2318 static int mce_cpu_pre_down(unsigned int cpu)
2320 struct timer_list *t = this_cpu_ptr(&mce_timer);
2324 mce_threshold_remove_device(cpu);
2325 mce_device_remove(cpu);
2329 static __init void mce_init_banks(void)
2333 for (i = 0; i < mca_cfg.banks; i++) {
2334 struct mce_bank *b = &mce_banks[i];
2335 struct device_attribute *a = &b->attr;
2337 sysfs_attr_init(&a->attr);
2338 a->attr.name = b->attrname;
2339 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2341 a->attr.mode = 0644;
2342 a->show = show_bank;
2343 a->store = set_bank;
2347 static __init int mcheck_init_device(void)
2351 if (!mce_available(&boot_cpu_data)) {
2356 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2363 err = subsys_system_register(&mce_subsys, NULL);
2367 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2372 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2373 mce_cpu_online, mce_cpu_pre_down);
2375 goto err_out_online;
2377 register_syscore_ops(&mce_syscore_ops);
2382 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2385 free_cpumask_var(mce_device_initialized);
2388 pr_err("Unable to init MCE device (rc: %d)\n", err);
2392 device_initcall_sync(mcheck_init_device);
2395 * Old style boot options parsing. Only for compatibility.
2397 static int __init mcheck_disable(char *str)
2399 mca_cfg.disabled = true;
2402 __setup("nomce", mcheck_disable);
2404 #ifdef CONFIG_DEBUG_FS
2405 struct dentry *mce_get_debugfs_dir(void)
2407 static struct dentry *dmce;
2410 dmce = debugfs_create_dir("mce", NULL);
2415 static void mce_reset(void)
2418 atomic_set(&mce_fake_panicked, 0);
2419 atomic_set(&mce_executing, 0);
2420 atomic_set(&mce_callin, 0);
2421 atomic_set(&global_nwo, 0);
2424 static int fake_panic_get(void *data, u64 *val)
2430 static int fake_panic_set(void *data, u64 val)
2437 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2438 fake_panic_set, "%llu\n");
2440 static int __init mcheck_debugfs_init(void)
2442 struct dentry *dmce, *ffake_panic;
2444 dmce = mce_get_debugfs_dir();
2447 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2455 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2458 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2459 EXPORT_SYMBOL_GPL(mcsafe_key);
2461 static int __init mcheck_late_init(void)
2463 pr_info("Using %d MCE banks\n", mca_cfg.banks);
2465 if (mca_cfg.recovery)
2466 static_branch_inc(&mcsafe_key);
2468 mcheck_debugfs_init();
2472 * Flush out everything that has been logged during early boot, now that
2473 * everything has been initialized (workqueues, decoders, ...).
2475 mce_schedule_work();
2479 late_initcall(mcheck_late_init);