1 #ifndef __MARVELL_CESA_H__
2 #define __MARVELL_CESA_H__
4 #include <crypto/algapi.h>
5 #include <crypto/hash.h>
6 #include <crypto/internal/hash.h>
8 #include <linux/crypto.h>
9 #include <linux/dmapool.h>
11 #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
13 #define CESA_TDMA_BYTE_CNT 0x800
14 #define CESA_TDMA_SRC_ADDR 0x810
15 #define CESA_TDMA_DST_ADDR 0x820
16 #define CESA_TDMA_NEXT_ADDR 0x830
18 #define CESA_TDMA_CONTROL 0x840
19 #define CESA_TDMA_DST_BURST GENMASK(2, 0)
20 #define CESA_TDMA_DST_BURST_32B 3
21 #define CESA_TDMA_DST_BURST_128B 4
22 #define CESA_TDMA_OUT_RD_EN BIT(4)
23 #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
24 #define CESA_TDMA_SRC_BURST_32B (3 << 6)
25 #define CESA_TDMA_SRC_BURST_128B (4 << 6)
26 #define CESA_TDMA_CHAIN BIT(9)
27 #define CESA_TDMA_BYTE_SWAP BIT(11)
28 #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
29 #define CESA_TDMA_EN BIT(12)
30 #define CESA_TDMA_FETCH_ND BIT(13)
31 #define CESA_TDMA_ACT BIT(14)
33 #define CESA_TDMA_CUR 0x870
34 #define CESA_TDMA_ERROR_CAUSE 0x8c8
35 #define CESA_TDMA_ERROR_MSK 0x8cc
37 #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
38 #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
40 #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
41 (((x) < 5) ? 0 : 0x14))
43 #define CESA_SA_CMD 0xde00
44 #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
45 #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
46 #define CESA_SA_CMD_DISABLE_SEC BIT(2)
48 #define CESA_SA_DESC_P0 0xde04
50 #define CESA_SA_DESC_P1 0xde14
52 #define CESA_SA_CFG 0xde08
53 #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
54 #define CESA_SA_CFG_DIG_ERR_CONT 0
55 #define CESA_SA_CFG_DIG_ERR_SKIP 1
56 #define CESA_SA_CFG_DIG_ERR_STOP 3
57 #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
58 #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
59 #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
60 #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
61 #define CESA_SA_CFG_MULTI_PKT BIT(11)
62 #define CESA_SA_CFG_PARA_DIS BIT(13)
64 #define CESA_SA_ACCEL_STATUS 0xde0c
65 #define CESA_SA_ST_ACT_0 BIT(0)
66 #define CESA_SA_ST_ACT_1 BIT(1)
69 * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
71 * and someone forgot to remove it while switching to the core and moving to
74 #define CESA_SA_FPGA_INT_STATUS 0xdd68
75 #define CESA_SA_INT_STATUS 0xde20
76 #define CESA_SA_INT_AUTH_DONE BIT(0)
77 #define CESA_SA_INT_DES_E_DONE BIT(1)
78 #define CESA_SA_INT_AES_E_DONE BIT(2)
79 #define CESA_SA_INT_AES_D_DONE BIT(3)
80 #define CESA_SA_INT_ENC_DONE BIT(4)
81 #define CESA_SA_INT_ACCEL0_DONE BIT(5)
82 #define CESA_SA_INT_ACCEL1_DONE BIT(6)
83 #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
84 #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
85 #define CESA_SA_INT_IDMA_DONE BIT(9)
86 #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
88 #define CESA_SA_INT_MSK 0xde24
90 #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
91 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
92 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
93 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
94 #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
95 #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
96 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
97 #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
98 #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
99 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
100 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
101 #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
102 #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
103 #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
104 #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
105 #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
106 #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
107 #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
108 #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
109 #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
110 #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
111 #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
112 #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
113 #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
114 #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
115 #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
116 #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
117 #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
118 #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
119 #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
120 #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
121 #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
125 * | ACCEL CFG | 4 * 8
127 * | CRYPT KEY | 8 * 4
130 * |-----------| 0x40 (inplace)
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
135 * | DATA OUT | 16 * x (max ->max_req_size)
136 * \-----------/ SRAM size
140 * Hashing memory map:
142 * | ACCEL CFG | 4 * 8
148 * | Output BUF| 8 * 4
150 * | DATA IN | 64 * x (max ->max_req_size)
151 * \-----------/ SRAM size
154 #define CESA_SA_CFG_SRAM_OFFSET 0x00
155 #define CESA_SA_DATA_SRAM_OFFSET 0x80
157 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
158 #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
160 #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
161 #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
162 #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
164 #define CESA_SA_DESC_CRYPT_DATA(offset) \
165 cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
166 ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
168 #define CESA_SA_DESC_CRYPT_IV(offset) \
169 cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
170 ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
172 #define CESA_SA_DESC_CRYPT_KEY(offset) \
173 cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
175 #define CESA_SA_DESC_MAC_DATA(offset) \
176 cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
177 #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
179 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
180 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
182 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
184 #define CESA_SA_DESC_MAC_DIGEST(offset) \
185 cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
186 #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
188 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
189 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
191 #define CESA_SA_DESC_MAC_IV(offset) \
192 cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
193 ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
195 #define CESA_SA_SRAM_SIZE 2048
196 #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
197 CESA_SA_DATA_SRAM_OFFSET)
199 #define CESA_SA_DEFAULT_SRAM_SIZE 2048
200 #define CESA_SA_MIN_SRAM_SIZE 1024
202 #define CESA_SA_SRAM_MSK (2048 - 1)
204 #define CESA_MAX_HASH_BLOCK_SIZE 64
205 #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
208 * struct mv_cesa_sec_accel_desc - security accelerator descriptor
209 * @config: engine config
210 * @enc_p: input and output data pointers for a cipher operation
211 * @enc_len: cipher operation length
212 * @enc_key_p: cipher key pointer
213 * @enc_iv: cipher IV pointers
214 * @mac_src_p: input pointer and total hash length
215 * @mac_digest: digest pointer and hash operation length
216 * @mac_iv: hmac IV pointers
218 * Structure passed to the CESA engine to describe the crypto operation
221 struct mv_cesa_sec_accel_desc {
233 * struct mv_cesa_blkcipher_op_ctx - cipher operation context
237 * Context associated to a cipher operation.
239 struct mv_cesa_blkcipher_op_ctx {
245 * struct mv_cesa_hash_op_ctx - hash or hmac operation context
249 * Context associated to an hash or hmac operation.
251 struct mv_cesa_hash_op_ctx {
257 * struct mv_cesa_op_ctx - crypto operation context
258 * @desc: CESA descriptor
259 * @ctx: context associated to the crypto operation
261 * Context associated to a crypto operation.
263 struct mv_cesa_op_ctx {
264 struct mv_cesa_sec_accel_desc desc;
266 struct mv_cesa_blkcipher_op_ctx blkcipher;
267 struct mv_cesa_hash_op_ctx hash;
271 /* TDMA descriptor flags */
272 #define CESA_TDMA_DST_IN_SRAM BIT(31)
273 #define CESA_TDMA_SRC_IN_SRAM BIT(30)
274 #define CESA_TDMA_END_OF_REQ BIT(29)
275 #define CESA_TDMA_BREAK_CHAIN BIT(28)
276 #define CESA_TDMA_SET_STATE BIT(27)
277 #define CESA_TDMA_TYPE_MSK GENMASK(26, 0)
278 #define CESA_TDMA_DUMMY 0
279 #define CESA_TDMA_DATA 1
280 #define CESA_TDMA_OP 2
281 #define CESA_TDMA_IV 3
284 * struct mv_cesa_tdma_desc - TDMA descriptor
285 * @byte_cnt: number of bytes to transfer
286 * @src: DMA address of the source
287 * @dst: DMA address of the destination
288 * @next_dma: DMA address of the next TDMA descriptor
289 * @cur_dma: DMA address of this TDMA descriptor
290 * @next: pointer to the next TDMA descriptor
291 * @op: CESA operation attached to this TDMA descriptor
292 * @data: raw data attached to this TDMA descriptor
293 * @flags: flags describing the TDMA transfer. See the
294 * "TDMA descriptor flags" section above
296 * TDMA descriptor used to create a transfer chain describing a crypto
299 struct mv_cesa_tdma_desc {
307 struct mv_cesa_tdma_desc *next;
309 struct mv_cesa_op_ctx *op;
316 * struct mv_cesa_sg_dma_iter - scatter-gather iterator
317 * @dir: transfer direction
319 * @offset: current position in the scatter list
320 * @op_offset: current position in the crypto operation
322 * Iterator used to iterate over a scatterlist while creating a TDMA chain for
323 * a crypto operation.
325 struct mv_cesa_sg_dma_iter {
326 enum dma_data_direction dir;
327 struct scatterlist *sg;
329 unsigned int op_offset;
333 * struct mv_cesa_dma_iter - crypto operation iterator
334 * @len: the crypto operation length
335 * @offset: current position in the crypto operation
336 * @op_len: sub-operation length (the crypto engine can only act on 2kb
339 * Iterator used to create a TDMA chain for a given crypto operation.
341 struct mv_cesa_dma_iter {
348 * struct mv_cesa_tdma_chain - TDMA chain
349 * @first: first entry in the TDMA chain
350 * @last: last entry in the TDMA chain
352 * Stores a TDMA chain for a specific crypto operation.
354 struct mv_cesa_tdma_chain {
355 struct mv_cesa_tdma_desc *first;
356 struct mv_cesa_tdma_desc *last;
359 struct mv_cesa_engine;
362 * struct mv_cesa_caps - CESA device capabilities
363 * @engines: number of engines
364 * @has_tdma: whether this device has a TDMA block
365 * @cipher_algs: supported cipher algorithms
366 * @ncipher_algs: number of supported cipher algorithms
367 * @ahash_algs: supported hash algorithms
368 * @nahash_algs: number of supported hash algorithms
370 * Structure used to describe CESA device capabilities.
372 struct mv_cesa_caps {
375 struct crypto_alg **cipher_algs;
377 struct ahash_alg **ahash_algs;
382 * struct mv_cesa_dev_dma - DMA pools
383 * @tdma_desc_pool: TDMA desc pool
384 * @op_pool: crypto operation pool
385 * @cache_pool: data cache pool (used by hash implementation when the
386 * hash request is smaller than the hash block size)
387 * @padding_pool: padding pool (used by hash implementation when hardware
388 * padding cannot be used)
390 * Structure containing the different DMA pools used by this driver.
392 struct mv_cesa_dev_dma {
393 struct dma_pool *tdma_desc_pool;
394 struct dma_pool *op_pool;
395 struct dma_pool *cache_pool;
396 struct dma_pool *padding_pool;
397 struct dma_pool *iv_pool;
401 * struct mv_cesa_dev - CESA device
402 * @caps: device capabilities
403 * @regs: device registers
404 * @sram_size: usable SRAM size
406 * @engines: array of engines
409 * Structure storing CESA device information.
412 const struct mv_cesa_caps *caps;
415 unsigned int sram_size;
417 struct mv_cesa_engine *engines;
418 struct mv_cesa_dev_dma *dma;
422 * struct mv_cesa_engine - CESA engine
424 * @regs: engine registers
425 * @sram: SRAM memory region
426 * @sram_dma: DMA address of the SRAM memory region
428 * @req: current crypto request
431 * @max_req_len: maximum chunk length (useful to create the TDMA chain)
432 * @int_mask: interrupt mask cache
433 * @pool: memory pool pointing to the memory region reserved in
435 * @queue: fifo of the pending crypto requests
436 * @load: engine load counter, useful for load balancing
437 * @chain: list of the current tdma descriptors being processed
439 * @complete_queue: fifo of the processed requests by the engine
441 * Structure storing CESA engine information.
443 struct mv_cesa_engine {
449 struct crypto_async_request *req;
454 struct gen_pool *pool;
455 struct crypto_queue queue;
457 struct mv_cesa_tdma_chain chain;
458 struct list_head complete_queue;
462 * struct mv_cesa_req_ops - CESA request operations
463 * @process: process a request chunk result (should return 0 if the
464 * operation, -EINPROGRESS if it needs more steps or an error
466 * @step: launch the crypto operation on the next chunk
467 * @cleanup: cleanup the crypto request (release associated data)
468 * @complete: complete the request, i.e copy result or context from sram when
471 struct mv_cesa_req_ops {
472 int (*process)(struct crypto_async_request *req, u32 status);
473 void (*step)(struct crypto_async_request *req);
474 void (*cleanup)(struct crypto_async_request *req);
475 void (*complete)(struct crypto_async_request *req);
479 * struct mv_cesa_ctx - CESA operation context
480 * @ops: crypto operations
482 * Base context structure inherited by operation specific ones.
485 const struct mv_cesa_req_ops *ops;
489 * struct mv_cesa_hash_ctx - CESA hash operation context
490 * @base: base context structure
492 * Hash context structure.
494 struct mv_cesa_hash_ctx {
495 struct mv_cesa_ctx base;
499 * struct mv_cesa_hash_ctx - CESA hmac operation context
500 * @base: base context structure
501 * @iv: initialization vectors
503 * HMAC context structure.
505 struct mv_cesa_hmac_ctx {
506 struct mv_cesa_ctx base;
511 * enum mv_cesa_req_type - request type definitions
512 * @CESA_STD_REQ: standard request
513 * @CESA_DMA_REQ: DMA request
515 enum mv_cesa_req_type {
521 * struct mv_cesa_req - CESA request
522 * @engine: engine associated with this request
523 * @chain: list of tdma descriptors associated with this request
526 struct mv_cesa_engine *engine;
527 struct mv_cesa_tdma_chain chain;
531 * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
533 * @iter: sg mapping iterator
534 * @offset: current offset in the SG entry mapped in memory
536 struct mv_cesa_sg_std_iter {
537 struct sg_mapping_iter iter;
542 * struct mv_cesa_ablkcipher_std_req - cipher standard request
543 * @op: operation context
544 * @offset: current operation offset
545 * @size: size of the crypto operation
547 struct mv_cesa_ablkcipher_std_req {
548 struct mv_cesa_op_ctx op;
555 * struct mv_cesa_ablkcipher_req - cipher request
556 * @req: type specific request information
557 * @src_nents: number of entries in the src sg list
558 * @dst_nents: number of entries in the dest sg list
560 struct mv_cesa_ablkcipher_req {
561 struct mv_cesa_req base;
562 struct mv_cesa_ablkcipher_std_req std;
568 * struct mv_cesa_ahash_std_req - standard hash request
569 * @offset: current operation offset
571 struct mv_cesa_ahash_std_req {
576 * struct mv_cesa_ahash_dma_req - DMA hash request
577 * @padding: padding buffer
578 * @padding_dma: DMA address of the padding buffer
579 * @cache_dma: DMA address of the cache buffer
581 struct mv_cesa_ahash_dma_req {
583 dma_addr_t padding_dma;
585 dma_addr_t cache_dma;
589 * struct mv_cesa_ahash_req - hash request
590 * @req: type specific request information
591 * @cache: cache buffer
592 * @cache_ptr: write pointer in the cache buffer
593 * @len: hash total length
594 * @src_nents: number of entries in the scatterlist
595 * @last_req: define whether the current operation is the last one
599 struct mv_cesa_ahash_req {
600 struct mv_cesa_req base;
602 struct mv_cesa_ahash_dma_req dma;
603 struct mv_cesa_ahash_std_req std;
605 struct mv_cesa_op_ctx op_tmpl;
606 u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
607 unsigned int cache_ptr;
617 extern struct mv_cesa_dev *cesa_dev;
621 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
622 struct crypto_async_request *req)
624 list_add_tail(&req->list, &engine->complete_queue);
627 static inline struct crypto_async_request *
628 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
630 struct crypto_async_request *req;
632 req = list_first_entry_or_null(&engine->complete_queue,
633 struct crypto_async_request,
636 list_del(&req->list);
642 static inline enum mv_cesa_req_type
643 mv_cesa_req_get_type(struct mv_cesa_req *req)
645 return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
648 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
651 op->desc.config &= cpu_to_le32(~mask);
652 op->desc.config |= cpu_to_le32(cfg);
655 static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
657 return le32_to_cpu(op->desc.config);
660 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
662 op->desc.config = cpu_to_le32(cfg);
665 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
666 struct mv_cesa_op_ctx *op)
668 u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
670 op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
671 op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
672 op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
673 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
674 op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
675 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
676 op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
677 op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
680 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
682 op->desc.enc_len = cpu_to_le32(len);
685 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
688 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
689 op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
692 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
695 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
696 op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
699 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
702 if (int_mask == engine->int_mask)
705 writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
706 engine->int_mask = int_mask;
709 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
711 return engine->int_mask;
714 static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
716 return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
717 CESA_SA_DESC_CFG_FIRST_FRAG;
720 int mv_cesa_queue_req(struct crypto_async_request *req,
721 struct mv_cesa_req *creq);
723 struct crypto_async_request *
724 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
725 struct crypto_async_request **backlog);
727 static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
730 u32 min_load = U32_MAX;
731 struct mv_cesa_engine *selected = NULL;
733 for (i = 0; i < cesa_dev->caps->nengines; i++) {
734 struct mv_cesa_engine *engine = cesa_dev->engines + i;
735 u32 load = atomic_read(&engine->load);
736 if (load < min_load) {
742 atomic_add(weight, &selected->load);
748 * Helper function that indicates whether a crypto request needs to be
749 * cleaned up or not after being enqueued using mv_cesa_queue_req().
751 static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
755 * The queue still had some space, the request was queued
756 * normally, so there's no need to clean it up.
758 if (ret == -EINPROGRESS)
762 * The queue had not space left, but since the request is
763 * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
764 * the backlog and will be processed later. There's no need to
767 if (ret == -EBUSY && req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
770 /* Request wasn't queued, we need to clean it up */
776 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
780 iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
784 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
785 struct scatterlist *sg,
786 enum dma_data_direction dir)
794 static inline unsigned int
795 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
796 struct mv_cesa_sg_dma_iter *sgiter)
798 return min(iter->op_len - sgiter->op_offset,
799 sg_dma_len(sgiter->sg) - sgiter->offset);
802 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
803 struct mv_cesa_sg_dma_iter *sgiter,
806 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
808 iter->offset += iter->op_len;
809 iter->op_len = min(iter->len - iter->offset,
810 CESA_SA_SRAM_PAYLOAD_SIZE);
815 void mv_cesa_dma_step(struct mv_cesa_req *dreq);
817 static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
820 if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
823 if (status & CESA_SA_INT_IDMA_OWN_ERR)
829 void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
830 struct mv_cesa_engine *engine);
831 void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
832 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
833 struct mv_cesa_req *dreq);
834 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
838 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
840 memset(chain, 0, sizeof(*chain));
843 int mv_cesa_dma_add_iv_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
844 u32 size, u32 flags, gfp_t gfp_flags);
846 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
847 const struct mv_cesa_op_ctx *op_templ,
851 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
852 dma_addr_t dst, dma_addr_t src, u32 size,
853 u32 flags, gfp_t gfp_flags);
855 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
856 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
858 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
859 struct mv_cesa_dma_iter *dma_iter,
860 struct mv_cesa_sg_dma_iter *sgiter,
863 /* Algorithm definitions */
865 extern struct ahash_alg mv_md5_alg;
866 extern struct ahash_alg mv_sha1_alg;
867 extern struct ahash_alg mv_sha256_alg;
868 extern struct ahash_alg mv_ahmac_md5_alg;
869 extern struct ahash_alg mv_ahmac_sha1_alg;
870 extern struct ahash_alg mv_ahmac_sha256_alg;
872 extern struct crypto_alg mv_cesa_ecb_des_alg;
873 extern struct crypto_alg mv_cesa_cbc_des_alg;
874 extern struct crypto_alg mv_cesa_ecb_des3_ede_alg;
875 extern struct crypto_alg mv_cesa_cbc_des3_ede_alg;
876 extern struct crypto_alg mv_cesa_ecb_aes_alg;
877 extern struct crypto_alg mv_cesa_cbc_aes_alg;
879 #endif /* __MARVELL_CESA_H__ */