2 * arch/arm/mach-orion5x/ts78xx-setup.c
4 * Maintainer: Alexander Clouter <alex@digriz.org.uk>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/sysfs.h>
16 #include <linux/platform_device.h>
17 #include <linux/mv643xx_eth.h>
18 #include <linux/ata_platform.h>
19 #include <linux/mtd/rawnand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/timeriomem-rng.h>
22 #include <asm/mach-types.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/map.h>
28 #include "ts78xx-fpga.h"
30 /*****************************************************************************
32 ****************************************************************************/
35 * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
37 #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
38 #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
39 #define TS78XX_FPGA_REGS_SIZE SZ_1M
41 static struct ts78xx_fpga_data ts78xx_fpga = {
44 /* .supports = ... - populated by ts78xx_fpga_supports() */
47 /*****************************************************************************
49 ****************************************************************************/
50 static struct map_desc ts78xx_io_desc[] __initdata = {
52 .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
53 .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
54 .length = TS78XX_FPGA_REGS_SIZE,
59 static void __init ts78xx_map_io(void)
62 iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
65 /*****************************************************************************
67 ****************************************************************************/
68 static struct mv643xx_eth_platform_data ts78xx_eth_data = {
69 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
72 /*****************************************************************************
74 ****************************************************************************/
75 static struct mv_sata_platform_data ts78xx_sata_data = {
79 /*****************************************************************************
80 * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
81 ****************************************************************************/
82 #define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
83 #define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
85 static struct resource ts78xx_ts_rtc_resources[] = {
86 DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
87 DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
90 static struct platform_device ts78xx_ts_rtc_device = {
93 .resource = ts78xx_ts_rtc_resources,
94 .num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
97 static int ts78xx_ts_rtc_load(void)
101 if (ts78xx_fpga.supports.ts_rtc.init == 0) {
102 rc = platform_device_register(&ts78xx_ts_rtc_device);
104 ts78xx_fpga.supports.ts_rtc.init = 1;
106 rc = platform_device_add(&ts78xx_ts_rtc_device);
110 pr_info("RTC could not be registered: %d\n", rc);
115 static void ts78xx_ts_rtc_unload(void)
117 platform_device_del(&ts78xx_ts_rtc_device);
120 /*****************************************************************************
122 ****************************************************************************/
123 #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
124 #define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
127 * hardware specific access to control-lines
130 * NAND_NCE: bit 0 -> bit 2
131 * NAND_CLE: bit 1 -> bit 1
132 * NAND_ALE: bit 2 -> bit 0
134 static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
137 struct nand_chip *this = mtd_to_nand(mtd);
139 if (ctrl & NAND_CTRL_CHANGE) {
142 bits = (ctrl & NAND_NCE) << 2;
143 bits |= ctrl & NAND_CLE;
144 bits |= (ctrl & NAND_ALE) >> 2;
146 writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
149 if (cmd != NAND_CMD_NONE)
150 writeb(cmd, this->IO_ADDR_W);
153 static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
155 return readb(TS_NAND_CTRL) & 0x20;
158 static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
159 const uint8_t *buf, int len)
161 struct nand_chip *chip = mtd_to_nand(mtd);
162 void __iomem *io_base = chip->IO_ADDR_W;
163 unsigned long off = ((unsigned long)buf & 3);
167 sz = min_t(int, 4 - off, len);
168 writesb(io_base, buf, sz);
175 u32 *buf32 = (u32 *)buf;
176 writesl(io_base, buf32, sz);
182 writesb(io_base, buf, len);
185 static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
186 uint8_t *buf, int len)
188 struct nand_chip *chip = mtd_to_nand(mtd);
189 void __iomem *io_base = chip->IO_ADDR_R;
190 unsigned long off = ((unsigned long)buf & 3);
194 sz = min_t(int, 4 - off, len);
195 readsb(io_base, buf, sz);
202 u32 *buf32 = (u32 *)buf;
203 readsl(io_base, buf32, sz);
209 readsb(io_base, buf, len);
212 static struct mtd_partition ts78xx_ts_nand_parts[] = {
217 .mask_flags = MTD_WRITEABLE,
220 .offset = MTDPART_OFS_APPEND,
224 .offset = MTDPART_OFS_APPEND,
228 .offset = MTDPART_OFS_APPEND,
229 .size = MTDPART_SIZ_FULL,
233 static struct platform_nand_data ts78xx_ts_nand_data = {
236 .partitions = ts78xx_ts_nand_parts,
237 .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
239 .bbt_options = NAND_BBT_USE_FLASH,
243 * The HW ECC offloading functions, used to give about a 9%
244 * performance increase for 'dd if=/dev/mtdblockX' and 5% for
245 * nanddump. This all however was changed by git commit
246 * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
247 * no performance advantage to be had so we no longer bother
249 .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
250 .dev_ready = ts78xx_ts_nand_dev_ready,
251 .write_buf = ts78xx_ts_nand_write_buf,
252 .read_buf = ts78xx_ts_nand_read_buf,
256 static struct resource ts78xx_ts_nand_resources
257 = DEFINE_RES_MEM(TS_NAND_DATA, 4);
259 static struct platform_device ts78xx_ts_nand_device = {
263 .platform_data = &ts78xx_ts_nand_data,
265 .resource = &ts78xx_ts_nand_resources,
269 static int ts78xx_ts_nand_load(void)
273 if (ts78xx_fpga.supports.ts_nand.init == 0) {
274 rc = platform_device_register(&ts78xx_ts_nand_device);
276 ts78xx_fpga.supports.ts_nand.init = 1;
278 rc = platform_device_add(&ts78xx_ts_nand_device);
281 pr_info("NAND could not be registered: %d\n", rc);
285 static void ts78xx_ts_nand_unload(void)
287 platform_device_del(&ts78xx_ts_nand_device);
290 /*****************************************************************************
292 ****************************************************************************/
293 #define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
295 static struct resource ts78xx_ts_rng_resource
296 = DEFINE_RES_MEM(TS_RNG_DATA, 4);
298 static struct timeriomem_rng_data ts78xx_ts_rng_data = {
299 .period = 1000000, /* one second */
302 static struct platform_device ts78xx_ts_rng_device = {
303 .name = "timeriomem_rng",
306 .platform_data = &ts78xx_ts_rng_data,
308 .resource = &ts78xx_ts_rng_resource,
312 static int ts78xx_ts_rng_load(void)
316 if (ts78xx_fpga.supports.ts_rng.init == 0) {
317 rc = platform_device_register(&ts78xx_ts_rng_device);
319 ts78xx_fpga.supports.ts_rng.init = 1;
321 rc = platform_device_add(&ts78xx_ts_rng_device);
324 pr_info("RNG could not be registered: %d\n", rc);
328 static void ts78xx_ts_rng_unload(void)
330 platform_device_del(&ts78xx_ts_rng_device);
333 /*****************************************************************************
334 * FPGA 'hotplug' support code
335 ****************************************************************************/
336 static void ts78xx_fpga_devices_zero_init(void)
338 ts78xx_fpga.supports.ts_rtc.init = 0;
339 ts78xx_fpga.supports.ts_nand.init = 0;
340 ts78xx_fpga.supports.ts_rng.init = 0;
343 static void ts78xx_fpga_supports(void)
345 /* TODO: put this 'table' into ts78xx-fpga.h */
346 switch (ts78xx_fpga.id) {
356 ts78xx_fpga.supports.ts_rtc.present = 1;
357 ts78xx_fpga.supports.ts_nand.present = 1;
358 ts78xx_fpga.supports.ts_rng.present = 1;
361 /* enable devices if magic matches */
362 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
363 case TS7800_FPGA_MAGIC:
364 pr_warn("unrecognised FPGA revision 0x%.2x\n",
365 ts78xx_fpga.id & 0xff);
366 ts78xx_fpga.supports.ts_rtc.present = 1;
367 ts78xx_fpga.supports.ts_nand.present = 1;
368 ts78xx_fpga.supports.ts_rng.present = 1;
371 ts78xx_fpga.supports.ts_rtc.present = 0;
372 ts78xx_fpga.supports.ts_nand.present = 0;
373 ts78xx_fpga.supports.ts_rng.present = 0;
378 static int ts78xx_fpga_load_devices(void)
382 if (ts78xx_fpga.supports.ts_rtc.present == 1) {
383 tmp = ts78xx_ts_rtc_load();
385 ts78xx_fpga.supports.ts_rtc.present = 0;
388 if (ts78xx_fpga.supports.ts_nand.present == 1) {
389 tmp = ts78xx_ts_nand_load();
391 ts78xx_fpga.supports.ts_nand.present = 0;
394 if (ts78xx_fpga.supports.ts_rng.present == 1) {
395 tmp = ts78xx_ts_rng_load();
397 ts78xx_fpga.supports.ts_rng.present = 0;
404 static int ts78xx_fpga_unload_devices(void)
408 if (ts78xx_fpga.supports.ts_rtc.present == 1)
409 ts78xx_ts_rtc_unload();
410 if (ts78xx_fpga.supports.ts_nand.present == 1)
411 ts78xx_ts_nand_unload();
412 if (ts78xx_fpga.supports.ts_rng.present == 1)
413 ts78xx_ts_rng_unload();
418 static int ts78xx_fpga_load(void)
420 ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
422 pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
423 (ts78xx_fpga.id >> 8) & 0xffffff,
424 ts78xx_fpga.id & 0xff);
426 ts78xx_fpga_supports();
428 if (ts78xx_fpga_load_devices()) {
429 ts78xx_fpga.state = -1;
436 static int ts78xx_fpga_unload(void)
438 unsigned int fpga_id;
440 fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
443 * There does not seem to be a feasible way to block access to the GPIO
444 * pins from userspace (/dev/mem). This if clause should hopefully warn
445 * those foolish enough not to follow 'policy' :)
447 * UrJTAG SVN since r1381 can be used to reprogram the FPGA
449 if (ts78xx_fpga.id != fpga_id) {
450 pr_err("FPGA magic/rev mismatch\n"
451 "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
452 (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
453 (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
454 ts78xx_fpga.state = -1;
458 if (ts78xx_fpga_unload_devices()) {
459 ts78xx_fpga.state = -1;
466 static ssize_t ts78xx_fpga_show(struct kobject *kobj,
467 struct kobj_attribute *attr, char *buf)
469 if (ts78xx_fpga.state < 0)
470 return sprintf(buf, "borked\n");
472 return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
475 static ssize_t ts78xx_fpga_store(struct kobject *kobj,
476 struct kobj_attribute *attr, const char *buf, size_t n)
480 if (ts78xx_fpga.state < 0) {
481 pr_err("FPGA borked, you must powercycle ASAP\n");
485 if (strncmp(buf, "online", sizeof("online") - 1) == 0)
487 else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
492 if (ts78xx_fpga.state == value)
495 ret = (ts78xx_fpga.state == 0)
497 : ts78xx_fpga_unload();
500 ts78xx_fpga.state = value;
505 static struct kobj_attribute ts78xx_fpga_attr =
506 __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
508 /*****************************************************************************
510 ****************************************************************************/
511 static unsigned int ts78xx_mpp_modes[] __initdata = {
513 MPP1_GPIO, /* JTAG Clock */
514 MPP2_GPIO, /* JTAG Data In */
515 MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
516 MPP4_GPIO, /* JTAG Data Out */
517 MPP5_GPIO, /* JTAG TMS */
518 MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
519 MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
533 * MPP[20] PCI Clock Out 1
534 * MPP[21] PCI Clock Out 0
543 static void __init ts78xx_init(void)
548 * Setup basic Orion functions. Need to be called early.
552 orion5x_mpp_conf(ts78xx_mpp_modes);
555 * Configure peripherals.
557 orion5x_ehci0_init();
558 orion5x_ehci1_init();
559 orion5x_eth_init(&ts78xx_eth_data);
560 orion5x_sata_init(&ts78xx_sata_data);
561 orion5x_uart0_init();
562 orion5x_uart1_init();
566 ts78xx_fpga_devices_zero_init();
567 ret = ts78xx_fpga_load();
568 ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
570 pr_err("sysfs_create_file failed: %d\n", ret);
573 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
574 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
575 .atag_offset = 0x100,
576 .nr_irqs = ORION5X_NR_IRQS,
577 .init_machine = ts78xx_init,
578 .map_io = ts78xx_map_io,
579 .init_early = orion5x_init_early,
580 .init_irq = orion5x_init_irq,
581 .init_time = orion5x_timer_init,
582 .restart = orion5x_restart,