1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2003-2008 Simtec Electronics
4 // Ben Dooks <ben@simtec.co.uk>
6 // http://www.simtec.co.uk/products/EB2410ITX/
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/list.h>
12 #include <linux/timer.h>
13 #include <linux/init.h>
14 #include <linux/gpio.h>
15 #include <linux/syscore_ops.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_s3c.h>
18 #include <linux/platform_device.h>
19 #include <linux/dm9000.h>
20 #include <linux/ata_platform.h>
21 #include <linux/i2c.h>
23 #include <linux/serial_8250.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/rawnand.h>
27 #include <linux/mtd/nand_ecc.h>
28 #include <linux/mtd/partitions.h>
30 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
31 #include <linux/platform_data/hwmon-s3c.h>
32 #include <linux/platform_data/i2c-s3c2410.h>
33 #include <linux/platform_data/mtd-nand-s3c2410.h>
35 #include <net/ax88796.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach-types.h>
44 #include <mach/hardware.h>
45 #include <mach/regs-gpio.h>
46 #include <mach/regs-lcd.h>
47 #include <mach/gpio-samsung.h>
50 #include <plat/cpu-freq.h>
51 #include <plat/devs.h>
52 #include <plat/gpio-cfg.h>
53 #include <plat/samsung-time.h>
59 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
61 /* macros for virtual address mods for the io space entries */
62 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
63 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
64 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
65 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
67 /* macros to modify the physical addresses for io space */
69 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
70 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
71 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
72 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
74 static struct map_desc bast_iodesc[] __initdata = {
77 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
78 .pfn = PA_CS2(BAST_PA_ISAIO),
82 .virtual = (u32)S3C24XX_VA_ISA_WORD,
83 .pfn = PA_CS3(BAST_PA_ISAIO),
87 /* bast CPLD control registers, and external interrupt controls */
89 .virtual = (u32)BAST_VA_CTRL1,
90 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
94 .virtual = (u32)BAST_VA_CTRL2,
95 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
99 .virtual = (u32)BAST_VA_CTRL3,
100 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
104 .virtual = (u32)BAST_VA_CTRL4,
105 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
111 .virtual = (u32)BAST_VA_PC104_IRQREQ,
112 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
116 .virtual = (u32)BAST_VA_PC104_IRQRAW,
117 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
121 .virtual = (u32)BAST_VA_PC104_IRQMASK,
122 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
127 /* peripheral space... one for each of fast/slow/byte/16bit */
128 /* note, ide is only decoded in word space, even though some registers
132 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
133 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
134 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
137 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
138 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
139 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
142 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
147 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
152 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
153 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
154 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
156 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
171 /* port 2 is not actually used */
181 /* NAND Flash on BAST board */
184 static int bast_pm_suspend(void)
186 /* ensure that an nRESET is not generated on resume. */
187 gpio_direction_output(S3C2410_GPA(21), 1);
191 static void bast_pm_resume(void)
193 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
197 #define bast_pm_suspend NULL
198 #define bast_pm_resume NULL
201 static struct syscore_ops bast_pm_syscore_ops = {
202 .suspend = bast_pm_suspend,
203 .resume = bast_pm_resume,
206 static int smartmedia_map[] = { 0 };
207 static int chip0_map[] = { 1 };
208 static int chip1_map[] = { 2 };
209 static int chip2_map[] = { 3 };
211 static struct mtd_partition __initdata bast_default_nand_part[] = {
213 .name = "Boot Agent",
219 .size = SZ_4M - SZ_16K,
225 .size = MTDPART_SIZ_FULL,
229 /* the bast has 4 selectable slots for nand-flash, the three
230 * on-board chip areas, as well as the external SmartMedia
233 * Note, there is no current hot-plug support for the SmartMedia
237 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
239 .name = "SmartMedia",
241 .nr_map = smartmedia_map,
242 .options = NAND_SCAN_SILENT_NODEV,
243 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
244 .partitions = bast_default_nand_part,
250 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
251 .partitions = bast_default_nand_part,
257 .options = NAND_SCAN_SILENT_NODEV,
258 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
259 .partitions = bast_default_nand_part,
265 .options = NAND_SCAN_SILENT_NODEV,
266 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
267 .partitions = bast_default_nand_part,
271 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
275 slot = set->nr_map[slot] & 3;
277 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
278 slot, set, set->nr_map);
280 tmp = __raw_readb(BAST_VA_CTRL2);
281 tmp &= BAST_CPLD_CTLR2_IDERST;
283 tmp |= BAST_CPLD_CTRL2_WNAND;
285 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
287 __raw_writeb(tmp, BAST_VA_CTRL2);
290 static struct s3c2410_platform_nand __initdata bast_nand_info = {
294 .nr_sets = ARRAY_SIZE(bast_nand_sets),
295 .sets = bast_nand_sets,
296 .select_chip = bast_nand_select,
297 .ecc_mode = NAND_ECC_SOFT,
302 static struct resource bast_dm9k_resource[] = {
303 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
304 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
305 [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
306 | IORESOURCE_IRQ_HIGHLEVEL),
309 /* for the moment we limit ourselves to 16bit IO until some
310 * better IO routines can be written and tested
313 static struct dm9000_plat_data bast_dm9k_platdata = {
314 .flags = DM9000_PLATF_16BITONLY,
317 static struct platform_device bast_device_dm9k = {
320 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
321 .resource = bast_dm9k_resource,
323 .platform_data = &bast_dm9k_platdata,
329 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
330 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
331 #define SERIAL_CLK (1843200)
333 static struct plat_serial8250_port bast_sio_data[] = {
335 .mapbase = SERIAL_BASE + 0x2f8,
336 .irq = BAST_IRQ_PCSERIAL1,
337 .flags = SERIAL_FLAGS,
340 .uartclk = SERIAL_CLK,
343 .mapbase = SERIAL_BASE + 0x3f8,
344 .irq = BAST_IRQ_PCSERIAL2,
345 .flags = SERIAL_FLAGS,
348 .uartclk = SERIAL_CLK,
353 static struct platform_device bast_sio = {
354 .name = "serial8250",
355 .id = PLAT8250_DEV_PLATFORM,
357 .platform_data = &bast_sio_data,
361 /* we have devices on the bus which cannot work much over the
362 * standard 100KHz i2c bus frequency
365 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
368 .frequency = 100*1000,
371 /* Asix AX88796 10/100 ethernet controller */
373 static struct ax_plat_data bast_asix_platdata = {
374 .flags = AXFLG_MAC_FROMDEV,
380 static struct resource bast_asix_resource[] = {
381 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
382 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
383 [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
386 static struct platform_device bast_device_asix = {
389 .num_resources = ARRAY_SIZE(bast_asix_resource),
390 .resource = bast_asix_resource,
392 .platform_data = &bast_asix_platdata
396 /* Asix AX88796 10/100 ethernet controller parallel port */
398 static struct resource bast_asixpp_resource[] = {
399 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
403 static struct platform_device bast_device_axpp = {
404 .name = "ax88796-pp",
406 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
407 .resource = bast_asixpp_resource,
410 /* LCD/VGA controller */
412 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
414 .type = S3C2410_LCDCON1_TFT,
429 .lcdcon5 = 0x00014b02,
432 .type = S3C2410_LCDCON1_TFT,
447 .lcdcon5 = 0x00014b02,
450 .type = S3C2410_LCDCON1_TFT,
465 .lcdcon5 = 0x00014b02,
469 /* LCD/VGA controller */
471 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
473 .displays = bast_lcd_info,
474 .num_displays = ARRAY_SIZE(bast_lcd_info),
475 .default_display = 1,
478 /* I2C devices fitted. */
480 static struct i2c_board_info bast_i2c_devs[] __initdata = {
482 I2C_BOARD_INFO("tlv320aic23", 0x1a),
484 I2C_BOARD_INFO("simtec-pmu", 0x6b),
486 I2C_BOARD_INFO("ch7013", 0x75),
490 static struct s3c_hwmon_pdata bast_hwmon_info = {
491 /* LCD contrast (0-6.6V) */
492 .in[0] = &(struct s3c_hwmon_chcfg) {
493 .name = "lcd-contrast",
497 /* LED current feedback */
498 .in[1] = &(struct s3c_hwmon_chcfg) {
499 .name = "led-feedback",
503 /* LCD feedback (0-6.6V) */
504 .in[2] = &(struct s3c_hwmon_chcfg) {
505 .name = "lcd-feedback",
509 /* Vcore (1.8-2.0V), Vref 3.3V */
510 .in[3] = &(struct s3c_hwmon_chcfg) {
517 /* Standard BAST devices */
518 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
520 static struct platform_device *bast_devices[] __initdata = {
521 &s3c2410_device_dclk,
536 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
537 .refresh = 7800, /* 7.8usec */
542 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
547 static void __init bast_map_io(void)
549 s3c_hwmon_set_platdata(&bast_hwmon_info);
551 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
552 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
553 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
556 static void __init bast_init_time(void)
558 s3c2410_init_clocks(12000000);
559 samsung_timer_init();
562 static void __init bast_init(void)
564 register_syscore_ops(&bast_pm_syscore_ops);
566 s3c_i2c0_set_platdata(&bast_i2c_info);
567 s3c_nand_set_platdata(&bast_nand_info);
568 s3c24xx_fb_set_platdata(&bast_fb_info);
569 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
571 i2c_register_board_info(0, bast_i2c_devs,
572 ARRAY_SIZE(bast_i2c_devs));
576 simtec_audio_add(NULL, true, &bast_audio);
578 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
580 s3c_cpufreq_setboard(&bast_cpufreq);
583 MACHINE_START(BAST, "Simtec-BAST")
584 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
585 .atag_offset = 0x100,
586 .map_io = bast_map_io,
587 .init_irq = s3c2410_init_irq,
588 .init_machine = bast_init,
589 .init_time = bast_init_time,