2 * arch/arm/mach-at91/pm_slow_clock.S
4 * Copyright (C) 2006 Savin Zlobec
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/linkage.h>
15 #include <linux/clk/at91_pmc.h>
17 #include "generated/at91_pm_data-offsets.h"
19 #define SRAMC_SELF_FRESH_ACTIVE 0x01
20 #define SRAMC_SELF_FRESH_EXIT 0x00
27 * Wait until master clock is ready (after switching master clock source)
30 1: ldr tmp1, [pmc, #AT91_PMC_SR]
31 tst tmp1, #AT91_PMC_MCKRDY
36 * Wait until master oscillator has stabilized.
39 1: ldr tmp1, [pmc, #AT91_PMC_SR]
40 tst tmp1, #AT91_PMC_MOSCS
45 * Wait for main oscillator selection is done
48 1: ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_MOSCSELS
54 * Wait until PLLA has locked.
57 1: ldr tmp1, [pmc, #AT91_PMC_SR]
58 tst tmp1, #AT91_PMC_LOCKA
63 * Put the processor to enter the idle state
67 #if defined(CONFIG_CPU_V7)
68 mov tmp1, #AT91_PMC_PCK
69 str tmp1, [pmc, #AT91_PMC_SCDR]
73 wfi @ Wait For Interrupt
75 mcr p15, 0, tmp1, c7, c0, 4
85 * void at91_suspend_sram_fn(struct at91_pm_data*)
87 * @r0: base address of struct at91_pm_data
89 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
91 ENTRY(at91_pm_suspend_in_sram)
92 /* Save registers on stack */
93 stmfd sp!, {r4 - r12, lr}
95 /* Drain write buffer */
97 mcr p15, 0, tmp1, c7, c10, 4
99 ldr tmp1, [r0, #PM_DATA_PMC]
101 ldr tmp1, [r0, #PM_DATA_RAMC0]
102 str tmp1, .sramc_base
103 ldr tmp1, [r0, #PM_DATA_RAMC1]
104 str tmp1, .sramc1_base
105 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
107 ldr tmp1, [r0, #PM_DATA_MODE]
109 /* Both ldrne below are here to preload their address in the TLB */
110 ldr tmp1, [r0, #PM_DATA_SHDWC]
113 ldrne tmp2, [tmp1, #0]
114 ldr tmp1, [r0, #PM_DATA_SFRBU]
117 ldrne tmp2, [tmp1, #0x10]
119 /* Active the self-refresh mode */
120 mov r0, #SRAMC_SELF_FRESH_ACTIVE
121 bl at91_sramc_self_refresh
124 cmp r0, #AT91_PM_STANDBY
126 cmp r0, #AT91_PM_BACKUP
133 /* Wait for interrupt */
143 /* Exit the self-refresh mode */
144 mov r0, #SRAMC_SELF_FRESH_EXIT
145 bl at91_sramc_self_refresh
147 /* Restore registers, and return */
148 ldmfd sp!, {r4 - r12, pc}
149 ENDPROC(at91_pm_suspend_in_sram)
151 ENTRY(at91_backup_mode)
155 str tmp1, [r0, #0x10]
159 mov tmp1, #0xA5000000
162 ENDPROC(at91_backup_mode)
164 .macro at91_pm_ulp0_mode
167 /* Turn off the crystal oscillator */
168 ldr tmp1, [pmc, #AT91_CKGR_MOR]
169 bic tmp1, tmp1, #AT91_PMC_MOSCEN
170 orr tmp1, tmp1, #AT91_PMC_KEY
171 str tmp1, [pmc, #AT91_CKGR_MOR]
173 /* Wait for interrupt */
176 /* Turn on the crystal oscillator */
177 ldr tmp1, [pmc, #AT91_CKGR_MOR]
178 orr tmp1, tmp1, #AT91_PMC_MOSCEN
179 orr tmp1, tmp1, #AT91_PMC_KEY
180 str tmp1, [pmc, #AT91_CKGR_MOR]
186 * Note: This procedure only applies on the platform which uses
187 * the external crystal oscillator as a main clock source.
189 .macro at91_pm_ulp1_mode
192 /* Switch the main clock source to 12-MHz RC oscillator */
193 ldr tmp1, [pmc, #AT91_CKGR_MOR]
194 bic tmp1, tmp1, #AT91_PMC_MOSCSEL
195 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
196 orr tmp1, tmp1, #AT91_PMC_KEY
197 str tmp1, [pmc, #AT91_CKGR_MOR]
201 /* Disable the crystal oscillator */
202 ldr tmp1, [pmc, #AT91_CKGR_MOR]
203 bic tmp1, tmp1, #AT91_PMC_MOSCEN
204 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
205 orr tmp1, tmp1, #AT91_PMC_KEY
206 str tmp1, [pmc, #AT91_CKGR_MOR]
208 /* Switch the master clock source to main clock */
209 ldr tmp1, [pmc, #AT91_PMC_MCKR]
210 bic tmp1, tmp1, #AT91_PMC_CSS
211 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
212 str tmp1, [pmc, #AT91_PMC_MCKR]
216 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
217 ldr tmp1, [pmc, #AT91_CKGR_MOR]
218 orr tmp1, tmp1, #AT91_PMC_WAITMODE
219 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
220 orr tmp1, tmp1, #AT91_PMC_KEY
221 str tmp1, [pmc, #AT91_CKGR_MOR]
223 /* Quirk for SAM9X60's PMC */
229 /* Enable the crystal oscillator */
230 ldr tmp1, [pmc, #AT91_CKGR_MOR]
231 orr tmp1, tmp1, #AT91_PMC_MOSCEN
232 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
233 orr tmp1, tmp1, #AT91_PMC_KEY
234 str tmp1, [pmc, #AT91_CKGR_MOR]
238 /* Switch the master clock source to slow clock */
239 ldr tmp1, [pmc, #AT91_PMC_MCKR]
240 bic tmp1, tmp1, #AT91_PMC_CSS
241 str tmp1, [pmc, #AT91_PMC_MCKR]
245 /* Switch main clock source to crystal oscillator */
246 ldr tmp1, [pmc, #AT91_CKGR_MOR]
247 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
248 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
249 orr tmp1, tmp1, #AT91_PMC_KEY
250 str tmp1, [pmc, #AT91_CKGR_MOR]
254 /* Switch the master clock source to main clock */
255 ldr tmp1, [pmc, #AT91_PMC_MCKR]
256 bic tmp1, tmp1, #AT91_PMC_CSS
257 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
258 str tmp1, [pmc, #AT91_PMC_MCKR]
266 /* Save Master clock setting */
267 ldr tmp1, [pmc, #AT91_PMC_MCKR]
268 str tmp1, .saved_mckr
271 * Set the Master clock source to slow clock
273 bic tmp1, tmp1, #AT91_PMC_CSS
274 str tmp1, [pmc, #AT91_PMC_MCKR]
278 /* Save PLLA setting and disable it */
279 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
280 str tmp1, .saved_pllar
282 mov tmp1, #AT91_PMC_PLLCOUNT
283 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
284 str tmp1, [pmc, #AT91_CKGR_PLLAR]
287 cmp r0, #AT91_PM_ULP1
300 /* Restore PLLA setting */
301 ldr tmp1, .saved_pllar
302 str tmp1, [pmc, #AT91_CKGR_PLLAR]
304 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
306 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
313 * Restore master clock setting
315 ldr tmp1, .saved_mckr
316 str tmp1, [pmc, #AT91_PMC_MCKR]
321 ENDPROC(at91_ulp_mode)
324 * void at91_sramc_self_refresh(unsigned int is_active)
327 * @r0: 1 - active self-refresh mode
328 * 0 - exit self-refresh mode
331 * @r2: base address of the sram controller
334 ENTRY(at91_sramc_self_refresh)
338 cmp r1, #AT91_MEMCTRL_MC
342 * at91rm9200 Memory controller
346 * For exiting the self-refresh mode, do nothing,
347 * automatically exit the self-refresh mode.
349 tst r0, #SRAMC_SELF_FRESH_ACTIVE
352 /* Active SDRAM self-refresh mode */
354 str r3, [r2, #AT91_MC_SDRAMC_SRR]
358 cmp r1, #AT91_MEMCTRL_DDRSDR
362 * DDR Memory controller
364 tst r0, #SRAMC_SELF_FRESH_ACTIVE
367 /* LPDDR1 --> force DDR2 mode during self-refresh */
368 ldr r3, [r2, #AT91_DDRSDRC_MDR]
369 str r3, .saved_sam9_mdr
370 bic r3, r3, #~AT91_DDRSDRC_MD
371 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
372 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
373 biceq r3, r3, #AT91_DDRSDRC_MD
374 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
375 streq r3, [r2, #AT91_DDRSDRC_MDR]
377 /* Active DDRC self-refresh mode */
378 ldr r3, [r2, #AT91_DDRSDRC_LPR]
379 str r3, .saved_sam9_lpr
380 bic r3, r3, #AT91_DDRSDRC_LPCB
381 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
382 str r3, [r2, #AT91_DDRSDRC_LPR]
384 /* If using the 2nd ddr controller */
389 ldr r3, [r2, #AT91_DDRSDRC_MDR]
390 str r3, .saved_sam9_mdr1
391 bic r3, r3, #~AT91_DDRSDRC_MD
392 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
393 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
394 biceq r3, r3, #AT91_DDRSDRC_MD
395 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
396 streq r3, [r2, #AT91_DDRSDRC_MDR]
398 /* Active DDRC self-refresh mode */
399 ldr r3, [r2, #AT91_DDRSDRC_LPR]
400 str r3, .saved_sam9_lpr1
401 bic r3, r3, #AT91_DDRSDRC_LPCB
402 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
403 str r3, [r2, #AT91_DDRSDRC_LPR]
409 /* Restore MDR in case of LPDDR1 */
410 ldr r3, .saved_sam9_mdr
411 str r3, [r2, #AT91_DDRSDRC_MDR]
412 /* Restore LPR on AT91 with DDRAM */
413 ldr r3, .saved_sam9_lpr
414 str r3, [r2, #AT91_DDRSDRC_LPR]
416 /* If using the 2nd ddr controller */
419 ldrne r3, .saved_sam9_mdr1
420 strne r3, [r2, #AT91_DDRSDRC_MDR]
421 ldrne r3, .saved_sam9_lpr1
422 strne r3, [r2, #AT91_DDRSDRC_LPR]
427 * SDRAMC Memory controller
430 tst r0, #SRAMC_SELF_FRESH_ACTIVE
433 /* Active SDRAMC self-refresh mode */
434 ldr r3, [r2, #AT91_SDRAMC_LPR]
435 str r3, .saved_sam9_lpr
436 bic r3, r3, #AT91_SDRAMC_LPCB
437 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
438 str r3, [r2, #AT91_SDRAMC_LPR]
441 ldr r3, .saved_sam9_lpr
442 str r3, [r2, #AT91_SDRAMC_LPR]
446 ENDPROC(at91_sramc_self_refresh)
475 ENTRY(at91_pm_suspend_in_sram_sz)
476 .word .-at91_pm_suspend_in_sram