1 From dbca73446265ce01b8e11462c3346b25953e3399 Mon Sep 17 00:00:00 2001
2 From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
3 Date: Mon, 7 Jan 2013 15:59:53 +0530
4 Subject: [PATCH] binutils: AR9271/AR7010 config
6 Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
8 bfd/xtensa-modules.c | 27121 +++++++++++++---------------------------------
9 include/xtensa-config.h | 36 +-
10 2 files changed, 7663 insertions(+), 19494 deletions(-)
12 diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-modules.c
13 index 3a79fcd..4704645 100644
14 --- a/bfd/xtensa-modules.c
15 +++ b/bfd/xtensa-modules.c
16 @@ -29,14 +29,6 @@ static xtensa_sysreg_internal sysregs[] = {
27 - { "PTEVADDR", 83, 0 },
31 @@ -47,29 +39,21 @@ static xtensa_sysreg_internal sysregs[] = {
34 { "CCOMPARE0", 240, 0 },
35 - { "CCOMPARE1", 241, 0 },
36 - { "CCOMPARE2", 242, 0 },
37 { "VECBASE", 231, 0 },
45 { "EXCSAVE1", 209, 0 },
46 { "EXCSAVE2", 210, 0 },
47 { "EXCSAVE3", 211, 0 },
48 { "EXCSAVE4", 212, 0 },
49 { "EXCSAVE5", 213, 0 },
50 - { "EXCSAVE6", 214, 0 },
51 - { "EXCSAVE7", 215, 0 },
58 { "EXCCAUSE", 232, 0 },
60 { "EXCVADDR", 238, 0 },
61 @@ -80,8 +64,6 @@ static xtensa_sysreg_internal sysregs[] = {
65 - { "MISC2", 246, 0 },
66 - { "MISC3", 247, 0 },
67 { "INTENABLE", 228, 0 },
68 { "DBREAKA0", 144, 0 },
69 { "DBREAKC0", 160, 0 },
70 @@ -92,19 +74,13 @@ static xtensa_sysreg_internal sysregs[] = {
71 { "IBREAKENABLE", 96, 0 },
72 { "ICOUNTLEVEL", 237, 0 },
73 { "DEBUGCAUSE", 233, 0 },
75 - { "ITLBCFG", 91, 0 },
76 - { "DTLBCFG", 92, 0 },
77 - { "CPENABLE", 224, 0 },
78 { "SCOMPARE1", 12, 0 },
79 - { "THREADPTR", 231, 1 },
82 + { "THREADPTR", 231, 1 }
85 -#define NUM_SYSREGS 74
86 -#define MAX_SPECIAL_REG 247
87 -#define MAX_USER_REG 233
88 +#define NUM_SYSREGS 50
89 +#define MAX_SPECIAL_REG 245
90 +#define MAX_USER_REG 231
93 /* Processor states. */
94 @@ -114,40 +90,33 @@ static xtensa_state_internal states[] = {
98 - { "INTERRUPT", 32, 0 },
99 + { "INTERRUPT", 19, 0 },
102 - { "VECBASE", 22, 0 },
103 + { "VECBASE", 21, 0 },
111 { "EXCSAVE1", 32, 0 },
112 { "EXCSAVE2", 32, 0 },
113 { "EXCSAVE3", 32, 0 },
114 { "EXCSAVE4", 32, 0 },
115 { "EXCSAVE5", 32, 0 },
116 - { "EXCSAVE6", 32, 0 },
117 - { "EXCSAVE7", 32, 0 },
128 { "EXCCAUSE", 6, 0 },
129 { "PSINTLEVEL", 4, 0 },
132 - { "PSRING", 2, 0 },
135 { "EXCVADDR", 32, 0 },
136 - { "WindowBase", 4, 0 },
137 - { "WindowStart", 16, 0 },
138 + { "WindowBase", 3, 0 },
139 + { "WindowStart", 8, 0 },
140 { "PSCALLINC", 2, 0 },
143 @@ -158,11 +127,8 @@ static xtensa_state_internal states[] = {
147 - { "MISC2", 32, 0 },
148 - { "MISC3", 32, 0 },
150 { "InOCDMode", 1, 0 },
151 - { "INTENABLE", 32, 0 },
152 + { "INTENABLE", 19, 0 },
153 { "DBREAKA0", 32, 0 },
154 { "DBREAKC0", 8, 0 },
155 { "DBREAKA1", 32, 0 },
156 @@ -174,34 +140,10 @@ static xtensa_state_internal states[] = {
157 { "DEBUGCAUSE", 6, 0 },
159 { "CCOMPARE0", 32, 0 },
160 - { "CCOMPARE1", 32, 0 },
161 - { "CCOMPARE2", 32, 0 },
165 - { "INSTPGSZID4", 2, 0 },
166 - { "DATAPGSZID4", 2, 0 },
167 - { "PTBASE", 10, 0 },
168 - { "CPENABLE", 1, 0 },
169 - { "SCOMPARE1", 32, 0 },
170 - { "RoundMode", 2, 0 },
171 - { "InvalidEnable", 1, 0 },
172 - { "DivZeroEnable", 1, 0 },
173 - { "OverflowEnable", 1, 0 },
174 - { "UnderflowEnable", 1, 0 },
175 - { "InexactEnable", 1, 0 },
176 - { "InvalidFlag", 1, 0 },
177 - { "DivZeroFlag", 1, 0 },
178 - { "OverflowFlag", 1, 0 },
179 - { "UnderflowFlag", 1, 0 },
180 - { "InexactFlag", 1, 0 },
181 - { "FPreserved20", 20, 0 },
182 - { "FPreserved20a", 20, 0 },
183 - { "FPreserved5", 5, 0 },
184 - { "FPreserved7", 7, 0 }
187 -#define NUM_STATES 89
188 + { "SCOMPARE1", 32, 0 }
191 +#define NUM_STATES 55
193 /* Macros for xtensa_state numbers (for use in iclasses because the
194 state numbers are not available when the iclass table is generated). */
195 @@ -219,82 +161,48 @@ static xtensa_state_internal states[] = {
196 #define STATE_EPC3 10
197 #define STATE_EPC4 11
198 #define STATE_EPC5 12
199 -#define STATE_EPC6 13
200 -#define STATE_EPC7 14
201 -#define STATE_EXCSAVE1 15
202 -#define STATE_EXCSAVE2 16
203 -#define STATE_EXCSAVE3 17
204 -#define STATE_EXCSAVE4 18
205 -#define STATE_EXCSAVE5 19
206 -#define STATE_EXCSAVE6 20
207 -#define STATE_EXCSAVE7 21
208 -#define STATE_EPS2 22
209 -#define STATE_EPS3 23
210 -#define STATE_EPS4 24
211 -#define STATE_EPS5 25
212 -#define STATE_EPS6 26
213 -#define STATE_EPS7 27
214 -#define STATE_EXCCAUSE 28
215 -#define STATE_PSINTLEVEL 29
216 -#define STATE_PSUM 30
217 -#define STATE_PSWOE 31
218 -#define STATE_PSRING 32
219 -#define STATE_PSEXCM 33
220 -#define STATE_DEPC 34
221 -#define STATE_EXCVADDR 35
222 -#define STATE_WindowBase 36
223 -#define STATE_WindowStart 37
224 -#define STATE_PSCALLINC 38
225 -#define STATE_PSOWB 39
226 -#define STATE_LBEG 40
227 -#define STATE_LEND 41
228 -#define STATE_SAR 42
229 -#define STATE_THREADPTR 43
230 -#define STATE_LITBADDR 44
231 -#define STATE_LITBEN 45
232 -#define STATE_MISC0 46
233 -#define STATE_MISC1 47
234 -#define STATE_MISC2 48
235 -#define STATE_MISC3 49
236 -#define STATE_ACC 50
237 -#define STATE_InOCDMode 51
238 -#define STATE_INTENABLE 52
239 -#define STATE_DBREAKA0 53
240 -#define STATE_DBREAKC0 54
241 -#define STATE_DBREAKA1 55
242 -#define STATE_DBREAKC1 56
243 -#define STATE_IBREAKA0 57
244 -#define STATE_IBREAKA1 58
245 -#define STATE_IBREAKENABLE 59
246 -#define STATE_ICOUNTLEVEL 60
247 -#define STATE_DEBUGCAUSE 61
248 -#define STATE_DBNUM 62
249 -#define STATE_CCOMPARE0 63
250 -#define STATE_CCOMPARE1 64
251 -#define STATE_CCOMPARE2 65
252 -#define STATE_ASID3 66
253 -#define STATE_ASID2 67
254 -#define STATE_ASID1 68
255 -#define STATE_INSTPGSZID4 69
256 -#define STATE_DATAPGSZID4 70
257 -#define STATE_PTBASE 71
258 -#define STATE_CPENABLE 72
259 -#define STATE_SCOMPARE1 73
260 -#define STATE_RoundMode 74
261 -#define STATE_InvalidEnable 75
262 -#define STATE_DivZeroEnable 76
263 -#define STATE_OverflowEnable 77
264 -#define STATE_UnderflowEnable 78
265 -#define STATE_InexactEnable 79
266 -#define STATE_InvalidFlag 80
267 -#define STATE_DivZeroFlag 81
268 -#define STATE_OverflowFlag 82
269 -#define STATE_UnderflowFlag 83
270 -#define STATE_InexactFlag 84
271 -#define STATE_FPreserved20 85
272 -#define STATE_FPreserved20a 86
273 -#define STATE_FPreserved5 87
274 -#define STATE_FPreserved7 88
275 +#define STATE_EXCSAVE1 13
276 +#define STATE_EXCSAVE2 14
277 +#define STATE_EXCSAVE3 15
278 +#define STATE_EXCSAVE4 16
279 +#define STATE_EXCSAVE5 17
280 +#define STATE_EPS2 18
281 +#define STATE_EPS3 19
282 +#define STATE_EPS4 20
283 +#define STATE_EPS5 21
284 +#define STATE_EXCCAUSE 22
285 +#define STATE_PSINTLEVEL 23
286 +#define STATE_PSUM 24
287 +#define STATE_PSWOE 25
288 +#define STATE_PSEXCM 26
289 +#define STATE_DEPC 27
290 +#define STATE_EXCVADDR 28
291 +#define STATE_WindowBase 29
292 +#define STATE_WindowStart 30
293 +#define STATE_PSCALLINC 31
294 +#define STATE_PSOWB 32
295 +#define STATE_LBEG 33
296 +#define STATE_LEND 34
297 +#define STATE_SAR 35
298 +#define STATE_THREADPTR 36
299 +#define STATE_LITBADDR 37
300 +#define STATE_LITBEN 38
301 +#define STATE_MISC0 39
302 +#define STATE_MISC1 40
303 +#define STATE_InOCDMode 41
304 +#define STATE_INTENABLE 42
305 +#define STATE_DBREAKA0 43
306 +#define STATE_DBREAKC0 44
307 +#define STATE_DBREAKA1 45
308 +#define STATE_DBREAKC1 46
309 +#define STATE_IBREAKA0 47
310 +#define STATE_IBREAKA1 48
311 +#define STATE_IBREAKENABLE 49
312 +#define STATE_ICOUNTLEVEL 50
313 +#define STATE_DEBUGCAUSE 51
314 +#define STATE_DBNUM 52
315 +#define STATE_CCOMPARE0 53
316 +#define STATE_SCOMPARE1 54
319 /* Field definitions. */
320 @@ -303,7 +211,7 @@ static unsigned
321 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
324 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
325 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
329 @@ -312,14 +220,14 @@ Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
332 tie_t = (val << 28) >> 28;
333 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
334 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
338 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
341 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
342 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
346 @@ -328,14 +236,14 @@ Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
349 tie_t = (val << 28) >> 28;
350 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
351 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
355 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
358 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
359 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
363 @@ -344,20491 +252,8868 @@ Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
366 tie_t = (val << 28) >> 28;
367 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
368 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
372 -Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
373 +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
376 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
377 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
382 -Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
383 +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
386 - tie_t = (val << 28) >> 28;
387 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
388 + tie_t = (val << 31) >> 31;
389 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
393 -Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
394 +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
397 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
398 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
399 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
404 -Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
405 +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
408 tie_t = (val << 28) >> 28;
409 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
410 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
411 + tie_t = (val << 27) >> 31;
412 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
416 -Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
417 +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
420 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
421 + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
426 -Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
427 +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
430 - tie_t = (val << 28) >> 28;
431 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
432 + tie_t = (val << 20) >> 20;
433 + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
437 -Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
438 +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
441 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
442 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
447 -Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
448 +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
451 - tie_t = (val << 28) >> 28;
452 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
453 + tie_t = (val << 24) >> 24;
454 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
458 -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
459 +Field_s_Slot_inst_get (const xtensa_insnbuf insn)
462 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
463 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
468 -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
469 +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
472 - tie_t = (val << 31) >> 31;
473 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
474 + tie_t = (val << 28) >> 28;
475 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
479 -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
480 +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
483 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
484 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
489 -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
490 +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
493 tie_t = (val << 28) >> 28;
494 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
495 - tie_t = (val << 27) >> 31;
496 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
500 -Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
501 +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
504 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
505 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
506 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
511 -Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
512 +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
515 tie_t = (val << 28) >> 28;
516 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
517 - tie_t = (val << 27) >> 31;
518 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
519 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
523 -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
524 +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
527 - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
528 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
529 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
534 -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
535 +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
538 - tie_t = (val << 20) >> 20;
539 - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
540 + tie_t = (val << 24) >> 24;
541 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
542 + tie_t = (val << 20) >> 28;
543 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
547 -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
548 +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
551 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
552 + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
557 -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
558 +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
561 - tie_t = (val << 24) >> 24;
562 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
563 + tie_t = (val << 16) >> 16;
564 + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
568 -Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
569 +Field_m_Slot_inst_get (const xtensa_insnbuf insn)
572 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
573 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
578 -Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
579 +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
582 - tie_t = (val << 24) >> 24;
583 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
584 + tie_t = (val << 30) >> 30;
585 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
589 -Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
590 +Field_n_Slot_inst_get (const xtensa_insnbuf insn)
593 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
594 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
595 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
600 -Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
601 +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
604 - tie_t = (val << 28) >> 28;
605 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
606 - tie_t = (val << 24) >> 28;
607 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
608 + tie_t = (val << 30) >> 30;
609 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
613 -Field_s_Slot_inst_get (const xtensa_insnbuf insn)
614 +Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
617 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
618 + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
623 -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
624 +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
627 - tie_t = (val << 28) >> 28;
628 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
629 + tie_t = (val << 14) >> 14;
630 + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
634 -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
635 +Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
638 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
639 + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
644 -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
645 +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
648 tie_t = (val << 28) >> 28;
649 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
650 + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
654 -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
655 +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
658 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
659 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
664 -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
665 +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
668 tie_t = (val << 28) >> 28;
669 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
670 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
674 -Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
675 +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
678 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
679 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
684 -Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
685 +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
688 tie_t = (val << 28) >> 28;
689 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
690 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
694 -Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
695 +Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
698 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
699 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
704 -Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
705 +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
708 tie_t = (val << 28) >> 28;
709 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
710 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
714 -Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
715 +Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
718 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
719 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
724 -Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
725 +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
728 tie_t = (val << 28) >> 28;
729 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
730 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
734 -Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
735 +Field_r_Slot_inst_get (const xtensa_insnbuf insn)
738 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
739 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
744 -Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
745 +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
748 tie_t = (val << 28) >> 28;
749 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
750 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
754 -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
755 +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
758 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
759 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
760 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
765 -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
766 +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
769 - tie_t = (val << 24) >> 24;
770 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
771 - tie_t = (val << 20) >> 28;
772 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
773 + tie_t = (val << 28) >> 28;
774 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
778 -Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
779 +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
782 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
783 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
784 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
789 -Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
790 +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
793 - tie_t = (val << 24) >> 24;
794 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
795 - tie_t = (val << 20) >> 28;
796 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
797 + tie_t = (val << 28) >> 28;
798 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
802 -Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
803 +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
806 - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
807 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
812 -Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
813 +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
816 - tie_t = (val << 20) >> 20;
817 - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
818 + tie_t = (val << 31) >> 31;
819 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
823 -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
824 +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
827 - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
828 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
833 -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
834 +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
837 - tie_t = (val << 16) >> 16;
838 - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
839 + tie_t = (val << 31) >> 31;
840 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
844 -Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
845 +Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
848 - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
849 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
850 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
855 -Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
856 +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
859 - tie_t = (val << 16) >> 16;
860 - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
861 + tie_t = (val << 28) >> 28;
862 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
863 + tie_t = (val << 27) >> 31;
864 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
868 -Field_m_Slot_inst_get (const xtensa_insnbuf insn)
869 +Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
872 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
873 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
874 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
879 -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
880 +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
883 - tie_t = (val << 30) >> 30;
884 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
885 + tie_t = (val << 28) >> 28;
886 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
887 + tie_t = (val << 27) >> 31;
888 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
892 -Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
893 +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
896 - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
897 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
898 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
903 -Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
904 +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
907 - tie_t = (val << 30) >> 30;
908 - insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
909 + tie_t = (val << 28) >> 28;
910 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
911 + tie_t = (val << 27) >> 31;
912 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
916 -Field_n_Slot_inst_get (const xtensa_insnbuf insn)
917 +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
920 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
921 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
926 -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
927 +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
930 - tie_t = (val << 30) >> 30;
931 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
932 + tie_t = (val << 31) >> 31;
933 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
937 -Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
938 +Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
941 - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
942 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
943 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
948 -Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
949 +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
952 - tie_t = (val << 30) >> 30;
953 - insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
954 + tie_t = (val << 28) >> 28;
955 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
956 + tie_t = (val << 27) >> 31;
957 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
961 -Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
962 +Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
965 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
966 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
967 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
972 -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
973 +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
976 - tie_t = (val << 14) >> 14;
977 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
978 + tie_t = (val << 28) >> 28;
979 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
980 + tie_t = (val << 24) >> 28;
981 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
985 -Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
986 +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
989 - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
990 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
991 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
996 -Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
997 +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1000 - tie_t = (val << 14) >> 14;
1001 - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
1002 + tie_t = (val << 28) >> 28;
1003 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1004 + tie_t = (val << 24) >> 28;
1005 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1009 -Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
1010 +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1013 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1014 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1019 -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1020 +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1023 tie_t = (val << 28) >> 28;
1024 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1025 + tie_t = (val << 24) >> 28;
1026 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1030 -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
1031 +Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1034 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1035 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1036 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1041 -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1042 +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1045 tie_t = (val << 28) >> 28;
1046 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1047 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1048 + tie_t = (val << 24) >> 28;
1049 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1053 -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
1054 +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1057 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1058 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1059 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1064 -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1065 +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1068 tie_t = (val << 28) >> 28;
1069 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1070 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1071 + tie_t = (val << 24) >> 28;
1072 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1076 -Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
1077 +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1080 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1081 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1082 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1087 -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1088 +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1091 tie_t = (val << 28) >> 28;
1092 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1093 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1094 + tie_t = (val << 24) >> 28;
1095 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1099 -Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1100 +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1103 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1104 + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
1109 -Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1110 +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1113 - tie_t = (val << 28) >> 28;
1114 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1115 + tie_t = (val << 29) >> 29;
1116 + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
1120 -Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
1121 +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1124 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
1125 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1130 -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1131 +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1134 tie_t = (val << 28) >> 28;
1135 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
1136 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1140 -Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1141 +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1144 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1145 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1150 -Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1151 +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1154 tie_t = (val << 28) >> 28;
1155 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1156 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1160 -Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1161 +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1164 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1165 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1170 -Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1171 +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1174 tie_t = (val << 28) >> 28;
1175 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1176 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1180 -Field_r_Slot_inst_get (const xtensa_insnbuf insn)
1181 +Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1184 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1185 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
1186 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
1191 -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1192 +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1195 - tie_t = (val << 28) >> 28;
1196 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1197 + tie_t = (val << 30) >> 30;
1198 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
1199 + tie_t = (val << 28) >> 30;
1200 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
1204 -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
1205 +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1208 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1209 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1214 -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1215 +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1218 - tie_t = (val << 28) >> 28;
1219 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1220 + tie_t = (val << 31) >> 31;
1221 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1225 -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
1226 +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1229 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1230 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1235 -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1236 +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1239 - tie_t = (val << 28) >> 28;
1240 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1241 + tie_t = (val << 31) >> 31;
1242 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1246 -Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1247 +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1250 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1251 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1256 -Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1257 +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1260 tie_t = (val << 28) >> 28;
1261 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1262 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1266 -Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1267 +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1270 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1271 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1276 -Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1277 +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1280 tie_t = (val << 28) >> 28;
1281 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1282 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1286 -Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1287 +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1290 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1291 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1296 -Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1297 +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1300 - tie_t = (val << 28) >> 28;
1301 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1302 + tie_t = (val << 30) >> 30;
1303 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1307 -Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
1308 +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1311 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1312 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1317 -Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
1318 +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1321 - tie_t = (val << 28) >> 28;
1322 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1323 + tie_t = (val << 30) >> 30;
1324 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1328 -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
1329 +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1332 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1333 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1338 -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1339 +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1342 - tie_t = (val << 31) >> 31;
1343 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1344 + tie_t = (val << 28) >> 28;
1345 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1349 -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
1350 +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1353 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1354 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1359 -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1360 +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1363 - tie_t = (val << 31) >> 31;
1364 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1365 + tie_t = (val << 28) >> 28;
1366 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1370 -Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1371 +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1374 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1375 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1380 -Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1381 +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1384 - tie_t = (val << 31) >> 31;
1385 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1386 + tie_t = (val << 29) >> 29;
1387 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1391 -Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1392 +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1395 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1396 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1397 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1402 -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1403 +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1406 - tie_t = (val << 28) >> 28;
1407 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1408 - tie_t = (val << 27) >> 31;
1409 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1410 + tie_t = (val << 29) >> 29;
1411 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1415 -Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1416 +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1419 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1420 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1421 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1426 -Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1427 +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1430 - tie_t = (val << 28) >> 28;
1431 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1432 - tie_t = (val << 27) >> 31;
1433 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1434 + tie_t = (val << 31) >> 31;
1435 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1439 -Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1440 +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1443 - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
1444 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1449 -Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1450 +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1453 - tie_t = (val << 27) >> 27;
1454 - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1455 + tie_t = (val << 31) >> 31;
1456 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1460 -Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1461 +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1464 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1465 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1466 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1467 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1472 -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1473 +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1476 tie_t = (val << 28) >> 28;
1477 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1478 - tie_t = (val << 27) >> 31;
1479 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1480 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1481 + tie_t = (val << 26) >> 30;
1482 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1486 -Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1487 +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1490 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1491 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1492 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1497 -Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1498 +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1501 tie_t = (val << 28) >> 28;
1502 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1503 - tie_t = (val << 27) >> 31;
1504 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1505 + tie_t = (val << 26) >> 30;
1506 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1510 -Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1511 +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1514 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1515 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1516 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1521 -Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1522 +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1525 tie_t = (val << 28) >> 28;
1526 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1527 - tie_t = (val << 27) >> 31;
1528 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1529 + tie_t = (val << 25) >> 29;
1530 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1534 -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1535 +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1538 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1539 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1540 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1541 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1546 -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1547 +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1550 tie_t = (val << 28) >> 28;
1551 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1552 - tie_t = (val << 27) >> 31;
1553 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1554 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1555 + tie_t = (val << 25) >> 29;
1556 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1560 -Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1561 +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1564 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1565 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1566 + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1571 -Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1572 +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1575 - tie_t = (val << 28) >> 28;
1576 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1577 - tie_t = (val << 27) >> 31;
1578 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1579 + tie_t = (val << 17) >> 17;
1580 + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1584 -Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1585 +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1588 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1589 + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1594 -Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1595 +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1598 - tie_t = (val << 27) >> 27;
1599 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1600 + tie_t = (val << 14) >> 14;
1601 + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1605 -Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1607 +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1608 + uint32 val ATTRIBUTE_UNUSED)
1610 - unsigned tie_t = 0;
1611 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1617 -Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1619 +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1622 - tie_t = (val << 27) >> 27;
1623 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1628 -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1629 +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1631 - unsigned tie_t = 0;
1632 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1638 -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1640 +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1643 - tie_t = (val << 31) >> 31;
1644 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1649 -Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1650 +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1652 - unsigned tie_t = 0;
1653 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1654 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1660 -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1662 +/* Functional units. */
1664 +static xtensa_funcUnit_internal funcUnits[] = {
1669 +/* Register files. */
1671 +static xtensa_regfile_internal regfiles[] = {
1672 + { "AR", "a", 0, 32, 32 }
1678 +static xtensa_interface_internal interfaces[] = {
1683 +/* Constant tables. */
1685 +/* constant table ai4c */
1686 +static const unsigned CONST_TBL_ai4c_0[] = {
1706 +/* constant table b4c */
1707 +static const unsigned CONST_TBL_b4c_0[] = {
1727 +/* constant table b4cu */
1728 +static const unsigned CONST_TBL_b4cu_0[] = {
1749 +/* Instruction operands. */
1752 +Operand_soffsetx4_decode (uint32 *valp)
1755 - tie_t = (val << 28) >> 28;
1756 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1757 - tie_t = (val << 27) >> 31;
1758 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1759 + unsigned soffsetx4_0, offset_0;
1760 + offset_0 = *valp & 0x3ffff;
1761 + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1762 + *valp = soffsetx4_0;
1767 -Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1769 +Operand_soffsetx4_encode (uint32 *valp)
1771 - unsigned tie_t = 0;
1772 - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1773 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1775 + unsigned offset_0, soffsetx4_0;
1776 + soffsetx4_0 = *valp;
1777 + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1783 -Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1785 +Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1788 - tie_t = (val << 28) >> 28;
1789 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1790 - tie_t = (val << 27) >> 31;
1791 - insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1792 + *valp -= (pc & ~0x3);
1797 -Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1799 +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1801 - unsigned tie_t = 0;
1802 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1803 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1805 + *valp += (pc & ~0x3);
1810 -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1812 +Operand_uimm12x8_decode (uint32 *valp)
1815 - tie_t = (val << 28) >> 28;
1816 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1817 - tie_t = (val << 24) >> 28;
1818 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1819 + unsigned uimm12x8_0, imm12_0;
1820 + imm12_0 = *valp & 0xfff;
1821 + uimm12x8_0 = imm12_0 << 3;
1822 + *valp = uimm12x8_0;
1827 -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1829 +Operand_uimm12x8_encode (uint32 *valp)
1831 - unsigned tie_t = 0;
1832 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1833 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1835 + unsigned imm12_0, uimm12x8_0;
1836 + uimm12x8_0 = *valp;
1837 + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1843 -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1845 +Operand_simm4_decode (uint32 *valp)
1848 - tie_t = (val << 28) >> 28;
1849 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1850 - tie_t = (val << 24) >> 28;
1851 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1852 + unsigned simm4_0, mn_0;
1853 + mn_0 = *valp & 0xf;
1854 + simm4_0 = ((int) mn_0 << 28) >> 28;
1860 -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1862 +Operand_simm4_encode (uint32 *valp)
1864 - unsigned tie_t = 0;
1865 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1866 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1868 + unsigned mn_0, simm4_0;
1870 + mn_0 = (simm4_0 & 0xf);
1876 -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1878 +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1881 - tie_t = (val << 28) >> 28;
1882 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1883 - tie_t = (val << 24) >> 28;
1884 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1889 -Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1891 +Operand_arr_encode (uint32 *valp)
1893 - unsigned tie_t = 0;
1894 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1895 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1898 + error = (*valp & ~0xf) != 0;
1903 -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1905 +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1908 - tie_t = (val << 28) >> 28;
1909 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1910 - tie_t = (val << 24) >> 28;
1911 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1916 -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1918 +Operand_ars_encode (uint32 *valp)
1920 - unsigned tie_t = 0;
1921 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1922 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1925 + error = (*valp & ~0xf) != 0;
1930 -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1932 +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1935 - tie_t = (val << 28) >> 28;
1936 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1937 - tie_t = (val << 24) >> 28;
1938 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1943 -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1945 +Operand_art_encode (uint32 *valp)
1947 - unsigned tie_t = 0;
1948 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1949 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1952 + error = (*valp & ~0xf) != 0;
1957 -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1960 - tie_t = (val << 28) >> 28;
1961 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1962 - tie_t = (val << 24) >> 28;
1963 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1967 -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1969 +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1971 - unsigned tie_t = 0;
1972 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1978 -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1980 +Operand_ar0_encode (uint32 *valp)
1983 - tie_t = (val << 29) >> 29;
1984 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1986 + error = (*valp & ~0x1f) != 0;
1991 -Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1993 +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1995 - unsigned tie_t = 0;
1996 - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
2002 -Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2004 +Operand_ar4_encode (uint32 *valp)
2007 - tie_t = (val << 29) >> 29;
2008 - insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
2010 + error = (*valp & ~0x1f) != 0;
2015 -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
2017 +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
2019 - unsigned tie_t = 0;
2020 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2026 -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2028 +Operand_ar8_encode (uint32 *valp)
2031 - tie_t = (val << 28) >> 28;
2032 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2034 + error = (*valp & ~0x1f) != 0;
2039 -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
2041 +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
2043 - unsigned tie_t = 0;
2044 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2050 -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2052 +Operand_ar12_encode (uint32 *valp)
2055 - tie_t = (val << 28) >> 28;
2056 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2058 + error = (*valp & ~0x1f) != 0;
2063 -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
2065 +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
2067 - unsigned tie_t = 0;
2068 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2074 -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2076 +Operand_ars_entry_encode (uint32 *valp)
2079 - tie_t = (val << 28) >> 28;
2080 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2082 + error = (*valp & ~0x1f) != 0;
2087 -Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
2089 +Operand_immrx4_decode (uint32 *valp)
2091 - unsigned tie_t = 0;
2092 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2093 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2095 + unsigned immrx4_0, r_0;
2096 + r_0 = *valp & 0xf;
2097 + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
2103 -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2105 +Operand_immrx4_encode (uint32 *valp)
2108 - tie_t = (val << 30) >> 30;
2109 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2110 - tie_t = (val << 28) >> 30;
2111 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2112 + unsigned r_0, immrx4_0;
2114 + r_0 = ((immrx4_0 >> 2) & 0xf);
2120 -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
2122 +Operand_lsi4x4_decode (uint32 *valp)
2124 - unsigned tie_t = 0;
2125 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2127 + unsigned lsi4x4_0, r_0;
2128 + r_0 = *valp & 0xf;
2129 + lsi4x4_0 = r_0 << 2;
2135 -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2137 +Operand_lsi4x4_encode (uint32 *valp)
2140 - tie_t = (val << 31) >> 31;
2141 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2142 + unsigned r_0, lsi4x4_0;
2144 + r_0 = ((lsi4x4_0 >> 2) & 0xf);
2150 -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
2152 +Operand_simm7_decode (uint32 *valp)
2154 - unsigned tie_t = 0;
2155 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2157 + unsigned simm7_0, imm7_0;
2158 + imm7_0 = *valp & 0x7f;
2159 + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
2165 -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2167 +Operand_simm7_encode (uint32 *valp)
2170 - tie_t = (val << 31) >> 31;
2171 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2172 + unsigned imm7_0, simm7_0;
2174 + imm7_0 = (simm7_0 & 0x7f);
2180 -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2182 +Operand_uimm6_decode (uint32 *valp)
2184 - unsigned tie_t = 0;
2185 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2187 + unsigned uimm6_0, imm6_0;
2188 + imm6_0 = *valp & 0x3f;
2189 + uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
2195 -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2197 +Operand_uimm6_encode (uint32 *valp)
2200 - tie_t = (val << 28) >> 28;
2201 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2202 + unsigned imm6_0, uimm6_0;
2204 + imm6_0 = (uimm6_0 - 0x4) & 0x3f;
2210 -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2212 +Operand_uimm6_ator (uint32 *valp, uint32 pc)
2214 - unsigned tie_t = 0;
2215 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2222 -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2224 +Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2227 - tie_t = (val << 28) >> 28;
2228 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2234 -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2236 +Operand_ai4const_decode (uint32 *valp)
2238 - unsigned tie_t = 0;
2239 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2241 + unsigned ai4const_0, t_0;
2242 + t_0 = *valp & 0xf;
2243 + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
2244 + *valp = ai4const_0;
2249 -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2251 +Operand_ai4const_encode (uint32 *valp)
2254 - tie_t = (val << 30) >> 30;
2255 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2256 + unsigned t_0, ai4const_0;
2257 + ai4const_0 = *valp;
2258 + switch (ai4const_0)
2260 + case 0xffffffff: t_0 = 0; break;
2261 + case 0x1: t_0 = 0x1; break;
2262 + case 0x2: t_0 = 0x2; break;
2263 + case 0x3: t_0 = 0x3; break;
2264 + case 0x4: t_0 = 0x4; break;
2265 + case 0x5: t_0 = 0x5; break;
2266 + case 0x6: t_0 = 0x6; break;
2267 + case 0x7: t_0 = 0x7; break;
2268 + case 0x8: t_0 = 0x8; break;
2269 + case 0x9: t_0 = 0x9; break;
2270 + case 0xa: t_0 = 0xa; break;
2271 + case 0xb: t_0 = 0xb; break;
2272 + case 0xc: t_0 = 0xc; break;
2273 + case 0xd: t_0 = 0xd; break;
2274 + case 0xe: t_0 = 0xe; break;
2275 + default: t_0 = 0xf; break;
2282 -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2284 +Operand_b4const_decode (uint32 *valp)
2286 - unsigned tie_t = 0;
2287 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2289 + unsigned b4const_0, r_0;
2290 + r_0 = *valp & 0xf;
2291 + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
2292 + *valp = b4const_0;
2297 -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2299 +Operand_b4const_encode (uint32 *valp)
2302 - tie_t = (val << 30) >> 30;
2303 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2305 + unsigned r_0, b4const_0;
2306 + b4const_0 = *valp;
2307 + switch (b4const_0)
2309 + case 0xffffffff: r_0 = 0; break;
2310 + case 0x1: r_0 = 0x1; break;
2311 + case 0x2: r_0 = 0x2; break;
2312 + case 0x3: r_0 = 0x3; break;
2313 + case 0x4: r_0 = 0x4; break;
2314 + case 0x5: r_0 = 0x5; break;
2315 + case 0x6: r_0 = 0x6; break;
2316 + case 0x7: r_0 = 0x7; break;
2317 + case 0x8: r_0 = 0x8; break;
2318 + case 0xa: r_0 = 0x9; break;
2319 + case 0xc: r_0 = 0xa; break;
2320 + case 0x10: r_0 = 0xb; break;
2321 + case 0x20: r_0 = 0xc; break;
2322 + case 0x40: r_0 = 0xd; break;
2323 + case 0x80: r_0 = 0xe; break;
2324 + default: r_0 = 0xf; break;
2331 -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2333 +Operand_b4constu_decode (uint32 *valp)
2335 - unsigned tie_t = 0;
2336 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2338 + unsigned b4constu_0, r_0;
2339 + r_0 = *valp & 0xf;
2340 + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2341 + *valp = b4constu_0;
2346 -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2348 +Operand_b4constu_encode (uint32 *valp)
2351 - tie_t = (val << 28) >> 28;
2352 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2353 + unsigned r_0, b4constu_0;
2354 + b4constu_0 = *valp;
2355 + switch (b4constu_0)
2357 + case 0x8000: r_0 = 0; break;
2358 + case 0x10000: r_0 = 0x1; break;
2359 + case 0x2: r_0 = 0x2; break;
2360 + case 0x3: r_0 = 0x3; break;
2361 + case 0x4: r_0 = 0x4; break;
2362 + case 0x5: r_0 = 0x5; break;
2363 + case 0x6: r_0 = 0x6; break;
2364 + case 0x7: r_0 = 0x7; break;
2365 + case 0x8: r_0 = 0x8; break;
2366 + case 0xa: r_0 = 0x9; break;
2367 + case 0xc: r_0 = 0xa; break;
2368 + case 0x10: r_0 = 0xb; break;
2369 + case 0x20: r_0 = 0xc; break;
2370 + case 0x40: r_0 = 0xd; break;
2371 + case 0x80: r_0 = 0xe; break;
2372 + default: r_0 = 0xf; break;
2379 -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2381 +Operand_uimm8_decode (uint32 *valp)
2383 - unsigned tie_t = 0;
2384 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2386 + unsigned uimm8_0, imm8_0;
2387 + imm8_0 = *valp & 0xff;
2394 -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2396 +Operand_uimm8_encode (uint32 *valp)
2399 - tie_t = (val << 28) >> 28;
2400 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2401 + unsigned imm8_0, uimm8_0;
2403 + imm8_0 = (uimm8_0 & 0xff);
2409 -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2411 +Operand_uimm8x2_decode (uint32 *valp)
2413 - unsigned tie_t = 0;
2414 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2416 + unsigned uimm8x2_0, imm8_0;
2417 + imm8_0 = *valp & 0xff;
2418 + uimm8x2_0 = imm8_0 << 1;
2419 + *valp = uimm8x2_0;
2424 -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2426 +Operand_uimm8x2_encode (uint32 *valp)
2429 - tie_t = (val << 29) >> 29;
2430 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2431 + unsigned imm8_0, uimm8x2_0;
2432 + uimm8x2_0 = *valp;
2433 + imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2439 -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2441 +Operand_uimm8x4_decode (uint32 *valp)
2443 - unsigned tie_t = 0;
2444 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2446 + unsigned uimm8x4_0, imm8_0;
2447 + imm8_0 = *valp & 0xff;
2448 + uimm8x4_0 = imm8_0 << 2;
2449 + *valp = uimm8x4_0;
2454 -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2456 +Operand_uimm8x4_encode (uint32 *valp)
2459 - tie_t = (val << 29) >> 29;
2460 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2461 + unsigned imm8_0, uimm8x4_0;
2462 + uimm8x4_0 = *valp;
2463 + imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2469 -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
2471 +Operand_uimm4x16_decode (uint32 *valp)
2473 - unsigned tie_t = 0;
2474 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2476 + unsigned uimm4x16_0, op2_0;
2477 + op2_0 = *valp & 0xf;
2478 + uimm4x16_0 = op2_0 << 4;
2479 + *valp = uimm4x16_0;
2484 -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2486 +Operand_uimm4x16_encode (uint32 *valp)
2489 - tie_t = (val << 31) >> 31;
2490 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2491 + unsigned op2_0, uimm4x16_0;
2492 + uimm4x16_0 = *valp;
2493 + op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2499 -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
2501 +Operand_simm8_decode (uint32 *valp)
2503 - unsigned tie_t = 0;
2504 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2506 + unsigned simm8_0, imm8_0;
2507 + imm8_0 = *valp & 0xff;
2508 + simm8_0 = ((int) imm8_0 << 24) >> 24;
2514 -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2516 +Operand_simm8_encode (uint32 *valp)
2519 - tie_t = (val << 31) >> 31;
2520 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2521 + unsigned imm8_0, simm8_0;
2523 + imm8_0 = (simm8_0 & 0xff);
2529 -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
2531 +Operand_simm8x256_decode (uint32 *valp)
2533 - unsigned tie_t = 0;
2534 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2535 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2537 + unsigned simm8x256_0, imm8_0;
2538 + imm8_0 = *valp & 0xff;
2539 + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2540 + *valp = simm8x256_0;
2545 -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2547 +Operand_simm8x256_encode (uint32 *valp)
2550 - tie_t = (val << 28) >> 28;
2551 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2552 - tie_t = (val << 26) >> 30;
2553 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2554 + unsigned imm8_0, simm8x256_0;
2555 + simm8x256_0 = *valp;
2556 + imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2562 -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
2564 +Operand_simm12b_decode (uint32 *valp)
2566 - unsigned tie_t = 0;
2567 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2568 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2570 + unsigned simm12b_0, imm12b_0;
2571 + imm12b_0 = *valp & 0xfff;
2572 + simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2573 + *valp = simm12b_0;
2578 -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2580 +Operand_simm12b_encode (uint32 *valp)
2583 - tie_t = (val << 28) >> 28;
2584 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2585 - tie_t = (val << 26) >> 30;
2586 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2587 + unsigned imm12b_0, simm12b_0;
2588 + simm12b_0 = *valp;
2589 + imm12b_0 = (simm12b_0 & 0xfff);
2595 -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
2597 +Operand_msalp32_decode (uint32 *valp)
2599 - unsigned tie_t = 0;
2600 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2601 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2603 + unsigned msalp32_0, sal_0;
2604 + sal_0 = *valp & 0x1f;
2605 + msalp32_0 = 0x20 - sal_0;
2606 + *valp = msalp32_0;
2611 -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2613 +Operand_msalp32_encode (uint32 *valp)
2616 - tie_t = (val << 28) >> 28;
2617 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2618 - tie_t = (val << 25) >> 29;
2619 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2620 + unsigned sal_0, msalp32_0;
2621 + msalp32_0 = *valp;
2622 + sal_0 = (0x20 - msalp32_0) & 0x1f;
2628 -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
2630 - unsigned tie_t = 0;
2631 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2632 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2635 +Operand_op2p1_decode (uint32 *valp)
2637 + unsigned op2p1_0, op2_0;
2638 + op2_0 = *valp & 0xf;
2639 + op2p1_0 = op2_0 + 0x1;
2645 -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2647 +Operand_op2p1_encode (uint32 *valp)
2650 - tie_t = (val << 28) >> 28;
2651 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2652 - tie_t = (val << 25) >> 29;
2653 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2654 + unsigned op2_0, op2p1_0;
2656 + op2_0 = (op2p1_0 - 0x1) & 0xf;
2662 -Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2664 +Operand_label8_decode (uint32 *valp)
2666 - unsigned tie_t = 0;
2667 - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2669 + unsigned label8_0, imm8_0;
2670 + imm8_0 = *valp & 0xff;
2671 + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2677 -Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2679 +Operand_label8_encode (uint32 *valp)
2682 - tie_t = (val << 25) >> 25;
2683 - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2684 + unsigned imm8_0, label8_0;
2686 + imm8_0 = (label8_0 - 0x4) & 0xff;
2692 -Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
2694 +Operand_label8_ator (uint32 *valp, uint32 pc)
2696 - unsigned tie_t = 0;
2697 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2704 -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2706 +Operand_label8_rtoa (uint32 *valp, uint32 pc)
2709 - tie_t = (val << 31) >> 31;
2710 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2716 -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
2718 +Operand_ulabel8_decode (uint32 *valp)
2720 - unsigned tie_t = 0;
2721 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2723 + unsigned ulabel8_0, imm8_0;
2724 + imm8_0 = *valp & 0xff;
2725 + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2726 + *valp = ulabel8_0;
2731 -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2733 +Operand_ulabel8_encode (uint32 *valp)
2736 - tie_t = (val << 31) >> 31;
2737 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2738 + unsigned imm8_0, ulabel8_0;
2739 + ulabel8_0 = *valp;
2740 + imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2746 -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
2748 +Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2750 - unsigned tie_t = 0;
2751 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2758 -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2760 +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2763 - tie_t = (val << 30) >> 30;
2764 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2770 -Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
2772 +Operand_label12_decode (uint32 *valp)
2774 - unsigned tie_t = 0;
2775 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2777 + unsigned label12_0, imm12_0;
2778 + imm12_0 = *valp & 0xfff;
2779 + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2780 + *valp = label12_0;
2785 -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2787 +Operand_label12_encode (uint32 *valp)
2790 - tie_t = (val << 31) >> 31;
2791 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2792 + unsigned imm12_0, label12_0;
2793 + label12_0 = *valp;
2794 + imm12_0 = (label12_0 - 0x4) & 0xfff;
2800 -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
2802 +Operand_label12_ator (uint32 *valp, uint32 pc)
2804 - unsigned tie_t = 0;
2805 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2812 -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2814 +Operand_label12_rtoa (uint32 *valp, uint32 pc)
2817 - tie_t = (val << 31) >> 31;
2818 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2824 -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
2826 +Operand_soffset_decode (uint32 *valp)
2828 - unsigned tie_t = 0;
2829 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2831 + unsigned soffset_0, offset_0;
2832 + offset_0 = *valp & 0x3ffff;
2833 + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2834 + *valp = soffset_0;
2839 -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2841 +Operand_soffset_encode (uint32 *valp)
2844 - tie_t = (val << 30) >> 30;
2845 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2846 + unsigned offset_0, soffset_0;
2847 + soffset_0 = *valp;
2848 + offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2854 -Field_w_Slot_inst_get (const xtensa_insnbuf insn)
2856 +Operand_soffset_ator (uint32 *valp, uint32 pc)
2858 - unsigned tie_t = 0;
2859 - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
2866 -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2868 +Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2871 - tie_t = (val << 30) >> 30;
2872 - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
2878 -Field_y_Slot_inst_get (const xtensa_insnbuf insn)
2880 +Operand_uimm16x4_decode (uint32 *valp)
2882 - unsigned tie_t = 0;
2883 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2885 + unsigned uimm16x4_0, imm16_0;
2886 + imm16_0 = *valp & 0xffff;
2887 + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2888 + *valp = uimm16x4_0;
2893 -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2895 +Operand_uimm16x4_encode (uint32 *valp)
2898 - tie_t = (val << 31) >> 31;
2899 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2900 + unsigned imm16_0, uimm16x4_0;
2901 + uimm16x4_0 = *valp;
2902 + imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2908 -Field_x_Slot_inst_get (const xtensa_insnbuf insn)
2910 +Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2912 - unsigned tie_t = 0;
2913 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2915 + *valp -= ((pc + 3) & ~0x3);
2920 -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2922 +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2925 - tie_t = (val << 31) >> 31;
2926 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2927 + *valp += ((pc + 3) & ~0x3);
2932 -Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
2934 +Operand_immt_decode (uint32 *valp)
2936 - unsigned tie_t = 0;
2937 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2939 + unsigned immt_0, t_0;
2940 + t_0 = *valp & 0xf;
2947 -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2949 +Operand_immt_encode (uint32 *valp)
2952 - tie_t = (val << 29) >> 29;
2953 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2954 + unsigned t_0, immt_0;
2956 + t_0 = immt_0 & 0xf;
2962 -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
2964 +Operand_imms_decode (uint32 *valp)
2966 - unsigned tie_t = 0;
2967 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2969 + unsigned imms_0, s_0;
2970 + s_0 = *valp & 0xf;
2977 -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2979 +Operand_imms_encode (uint32 *valp)
2982 - tie_t = (val << 29) >> 29;
2983 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2984 + unsigned s_0, imms_0;
2986 + s_0 = imms_0 & 0xf;
2992 -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
2994 +Operand_tp7_decode (uint32 *valp)
2996 - unsigned tie_t = 0;
2997 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2999 + unsigned tp7_0, t_0;
3000 + t_0 = *valp & 0xf;
3001 + tp7_0 = t_0 + 0x7;
3007 -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3009 +Operand_tp7_encode (uint32 *valp)
3012 - tie_t = (val << 29) >> 29;
3013 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
3014 + unsigned t_0, tp7_0;
3016 + t_0 = (tp7_0 - 0x7) & 0xf;
3022 -Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
3024 +Operand_xt_wbr15_label_decode (uint32 *valp)
3026 - unsigned tie_t = 0;
3027 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3029 + unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
3030 + xt_wbr15_imm_0 = *valp & 0x7fff;
3031 + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
3032 + *valp = xt_wbr15_label_0;
3037 -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3039 +Operand_xt_wbr15_label_encode (uint32 *valp)
3042 - tie_t = (val << 29) >> 29;
3043 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3044 + unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
3045 + xt_wbr15_label_0 = *valp;
3046 + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
3047 + *valp = xt_wbr15_imm_0;
3052 -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
3054 +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
3056 - unsigned tie_t = 0;
3057 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3064 -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3066 +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
3069 - tie_t = (val << 29) >> 29;
3070 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3076 -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
3078 +Operand_xt_wbr18_label_decode (uint32 *valp)
3080 - unsigned tie_t = 0;
3081 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3083 + unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
3084 + xt_wbr18_imm_0 = *valp & 0x3ffff;
3085 + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
3086 + *valp = xt_wbr18_label_0;
3091 -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3093 +Operand_xt_wbr18_label_encode (uint32 *valp)
3096 - tie_t = (val << 29) >> 29;
3097 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3098 + unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
3099 + xt_wbr18_label_0 = *valp;
3100 + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
3101 + *valp = xt_wbr18_imm_0;
3106 -Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
3108 +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
3110 - unsigned tie_t = 0;
3111 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3118 -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3120 +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
3123 - tie_t = (val << 29) >> 29;
3124 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3130 -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
3132 - unsigned tie_t = 0;
3133 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3136 +static xtensa_operand_internal operands[] = {
3137 + { "soffsetx4", 10, -1, 0,
3138 + XTENSA_OPERAND_IS_PCRELATIVE,
3139 + Operand_soffsetx4_encode, Operand_soffsetx4_decode,
3140 + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
3141 + { "uimm12x8", 3, -1, 0,
3143 + Operand_uimm12x8_encode, Operand_uimm12x8_decode,
3145 + { "simm4", 26, -1, 0,
3147 + Operand_simm4_encode, Operand_simm4_decode,
3149 + { "arr", 14, 0, 1,
3150 + XTENSA_OPERAND_IS_REGISTER,
3151 + Operand_arr_encode, Operand_arr_decode,
3154 + XTENSA_OPERAND_IS_REGISTER,
3155 + Operand_ars_encode, Operand_ars_decode,
3157 + { "*ars_invisible", 5, 0, 1,
3158 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3159 + Operand_ars_encode, Operand_ars_decode,
3162 + XTENSA_OPERAND_IS_REGISTER,
3163 + Operand_art_encode, Operand_art_decode,
3165 + { "ar0", 37, 0, 1,
3166 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3167 + Operand_ar0_encode, Operand_ar0_decode,
3169 + { "ar4", 38, 0, 1,
3170 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3171 + Operand_ar4_encode, Operand_ar4_decode,
3173 + { "ar8", 39, 0, 1,
3174 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3175 + Operand_ar8_encode, Operand_ar8_decode,
3177 + { "ar12", 40, 0, 1,
3178 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3179 + Operand_ar12_encode, Operand_ar12_decode,
3181 + { "ars_entry", 5, 0, 1,
3182 + XTENSA_OPERAND_IS_REGISTER,
3183 + Operand_ars_entry_encode, Operand_ars_entry_decode,
3185 + { "immrx4", 14, -1, 0,
3187 + Operand_immrx4_encode, Operand_immrx4_decode,
3189 + { "lsi4x4", 14, -1, 0,
3191 + Operand_lsi4x4_encode, Operand_lsi4x4_decode,
3193 + { "simm7", 34, -1, 0,
3195 + Operand_simm7_encode, Operand_simm7_decode,
3197 + { "uimm6", 33, -1, 0,
3198 + XTENSA_OPERAND_IS_PCRELATIVE,
3199 + Operand_uimm6_encode, Operand_uimm6_decode,
3200 + Operand_uimm6_ator, Operand_uimm6_rtoa },
3201 + { "ai4const", 0, -1, 0,
3203 + Operand_ai4const_encode, Operand_ai4const_decode,
3205 + { "b4const", 14, -1, 0,
3207 + Operand_b4const_encode, Operand_b4const_decode,
3209 + { "b4constu", 14, -1, 0,
3211 + Operand_b4constu_encode, Operand_b4constu_decode,
3213 + { "uimm8", 4, -1, 0,
3215 + Operand_uimm8_encode, Operand_uimm8_decode,
3217 + { "uimm8x2", 4, -1, 0,
3219 + Operand_uimm8x2_encode, Operand_uimm8x2_decode,
3221 + { "uimm8x4", 4, -1, 0,
3223 + Operand_uimm8x4_encode, Operand_uimm8x4_decode,
3225 + { "uimm4x16", 13, -1, 0,
3227 + Operand_uimm4x16_encode, Operand_uimm4x16_decode,
3229 + { "simm8", 4, -1, 0,
3231 + Operand_simm8_encode, Operand_simm8_decode,
3233 + { "simm8x256", 4, -1, 0,
3235 + Operand_simm8x256_encode, Operand_simm8x256_decode,
3237 + { "simm12b", 6, -1, 0,
3239 + Operand_simm12b_encode, Operand_simm12b_decode,
3241 + { "msalp32", 18, -1, 0,
3243 + Operand_msalp32_encode, Operand_msalp32_decode,
3245 + { "op2p1", 13, -1, 0,
3247 + Operand_op2p1_encode, Operand_op2p1_decode,
3249 + { "label8", 4, -1, 0,
3250 + XTENSA_OPERAND_IS_PCRELATIVE,
3251 + Operand_label8_encode, Operand_label8_decode,
3252 + Operand_label8_ator, Operand_label8_rtoa },
3253 + { "ulabel8", 4, -1, 0,
3254 + XTENSA_OPERAND_IS_PCRELATIVE,
3255 + Operand_ulabel8_encode, Operand_ulabel8_decode,
3256 + Operand_ulabel8_ator, Operand_ulabel8_rtoa },
3257 + { "label12", 3, -1, 0,
3258 + XTENSA_OPERAND_IS_PCRELATIVE,
3259 + Operand_label12_encode, Operand_label12_decode,
3260 + Operand_label12_ator, Operand_label12_rtoa },
3261 + { "soffset", 10, -1, 0,
3262 + XTENSA_OPERAND_IS_PCRELATIVE,
3263 + Operand_soffset_encode, Operand_soffset_decode,
3264 + Operand_soffset_ator, Operand_soffset_rtoa },
3265 + { "uimm16x4", 7, -1, 0,
3266 + XTENSA_OPERAND_IS_PCRELATIVE,
3267 + Operand_uimm16x4_encode, Operand_uimm16x4_decode,
3268 + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
3269 + { "immt", 0, -1, 0,
3271 + Operand_immt_encode, Operand_immt_decode,
3273 + { "imms", 5, -1, 0,
3275 + Operand_imms_encode, Operand_imms_decode,
3277 + { "tp7", 0, -1, 0,
3279 + Operand_tp7_encode, Operand_tp7_decode,
3281 + { "xt_wbr15_label", 35, -1, 0,
3282 + XTENSA_OPERAND_IS_PCRELATIVE,
3283 + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
3284 + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
3285 + { "xt_wbr18_label", 36, -1, 0,
3286 + XTENSA_OPERAND_IS_PCRELATIVE,
3287 + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
3288 + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
3289 + { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
3290 + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
3291 + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
3292 + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
3293 + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
3294 + { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
3295 + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
3296 + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
3297 + { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
3298 + { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
3299 + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
3300 + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
3301 + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
3302 + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
3303 + { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
3304 + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
3305 + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
3306 + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
3307 + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
3308 + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
3309 + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
3310 + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
3311 + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
3312 + { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
3313 + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
3314 + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
3315 + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
3316 + { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
3317 + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
3318 + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
3319 + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
3320 + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
3321 + { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
3322 + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
3323 + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
3324 + { "xt_wbr15_imm", 35, -1, 0, 0, 0, 0, 0, 0 },
3325 + { "xt_wbr18_imm", 36, -1, 0, 0, 0, 0, 0, 0 }
3329 -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3332 - tie_t = (val << 29) >> 29;
3333 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3336 +/* Iclass table. */
3339 -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
3341 - unsigned tie_t = 0;
3342 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3345 +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3346 + { { STATE_PSEXCM }, 'o' },
3347 + { { STATE_EPC1 }, 'i' }
3351 -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3354 - tie_t = (val << 29) >> 29;
3355 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3357 +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3358 + { { STATE_DEPC }, 'i' }
3362 -Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
3364 - unsigned tie_t = 0;
3365 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3368 +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3369 + { { 0 /* soffsetx4 */ }, 'i' },
3370 + { { 10 /* ar12 */ }, 'o' }
3374 -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3377 - tie_t = (val << 30) >> 30;
3378 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3380 +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3381 + { { STATE_PSCALLINC }, 'o' }
3385 -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
3387 - unsigned tie_t = 0;
3388 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3391 +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3392 + { { 0 /* soffsetx4 */ }, 'i' },
3393 + { { 9 /* ar8 */ }, 'o' }
3397 -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3400 - tie_t = (val << 30) >> 30;
3401 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3403 +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3404 + { { STATE_PSCALLINC }, 'o' }
3408 -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
3410 - unsigned tie_t = 0;
3411 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3414 +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3415 + { { 0 /* soffsetx4 */ }, 'i' },
3416 + { { 8 /* ar4 */ }, 'o' }
3420 -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3423 - tie_t = (val << 30) >> 30;
3424 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3426 +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3427 + { { STATE_PSCALLINC }, 'o' }
3431 -Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
3433 - unsigned tie_t = 0;
3434 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3437 +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3438 + { { 4 /* ars */ }, 'i' },
3439 + { { 10 /* ar12 */ }, 'o' }
3443 -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3446 - tie_t = (val << 30) >> 30;
3447 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3449 +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3450 + { { STATE_PSCALLINC }, 'o' }
3454 -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
3456 - unsigned tie_t = 0;
3457 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3460 +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3461 + { { 4 /* ars */ }, 'i' },
3462 + { { 9 /* ar8 */ }, 'o' }
3466 -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3469 - tie_t = (val << 30) >> 30;
3470 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3472 +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3473 + { { STATE_PSCALLINC }, 'o' }
3477 -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
3479 - unsigned tie_t = 0;
3480 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3483 +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3484 + { { 4 /* ars */ }, 'i' },
3485 + { { 8 /* ar4 */ }, 'o' }
3489 -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3492 - tie_t = (val << 30) >> 30;
3493 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3495 +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3496 + { { STATE_PSCALLINC }, 'o' }
3500 -Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
3502 - unsigned tie_t = 0;
3503 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3506 +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3507 + { { 11 /* ars_entry */ }, 's' },
3508 + { { 4 /* ars */ }, 'i' },
3509 + { { 1 /* uimm12x8 */ }, 'i' }
3513 -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3516 - tie_t = (val << 30) >> 30;
3517 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3519 +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3520 + { { STATE_PSCALLINC }, 'i' },
3521 + { { STATE_PSEXCM }, 'i' },
3522 + { { STATE_PSWOE }, 'i' },
3523 + { { STATE_WindowBase }, 'm' },
3524 + { { STATE_WindowStart }, 'm' }
3528 -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
3530 - unsigned tie_t = 0;
3531 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3534 +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3535 + { { 6 /* art */ }, 'o' },
3536 + { { 4 /* ars */ }, 'i' }
3540 -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3543 - tie_t = (val << 30) >> 30;
3544 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3546 +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3547 + { { STATE_WindowBase }, 'i' },
3548 + { { STATE_WindowStart }, 'i' }
3552 -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
3554 - unsigned tie_t = 0;
3555 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3558 +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3559 + { { 2 /* simm4 */ }, 'i' }
3563 -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3566 - tie_t = (val << 30) >> 30;
3567 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3569 +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3570 + { { STATE_WindowBase }, 'm' }
3574 -Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
3576 - unsigned tie_t = 0;
3577 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3580 +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3581 + { { 5 /* *ars_invisible */ }, 'i' }
3585 -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3588 - tie_t = (val << 31) >> 31;
3589 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3591 +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3592 + { { STATE_WindowBase }, 'm' },
3593 + { { STATE_WindowStart }, 'm' },
3594 + { { STATE_PSEXCM }, 'i' },
3595 + { { STATE_PSWOE }, 'i' }
3599 -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
3601 - unsigned tie_t = 0;
3602 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3605 +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3606 + { { STATE_EPC1 }, 'i' },
3607 + { { STATE_PSEXCM }, 'o' },
3608 + { { STATE_WindowBase }, 'm' },
3609 + { { STATE_WindowStart }, 'm' },
3610 + { { STATE_PSOWB }, 'i' }
3614 -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3617 - tie_t = (val << 31) >> 31;
3618 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3620 +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3621 + { { 6 /* art */ }, 'o' },
3622 + { { 4 /* ars */ }, 'i' },
3623 + { { 12 /* immrx4 */ }, 'i' }
3627 -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
3629 - unsigned tie_t = 0;
3630 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3633 +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3634 + { { 6 /* art */ }, 'i' },
3635 + { { 4 /* ars */ }, 'i' },
3636 + { { 12 /* immrx4 */ }, 'i' }
3640 -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3643 - tie_t = (val << 31) >> 31;
3644 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3646 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3647 + { { 6 /* art */ }, 'o' }
3651 -Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
3653 - unsigned tie_t = 0;
3654 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3657 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3658 + { { STATE_WindowBase }, 'i' }
3662 -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3665 - tie_t = (val << 31) >> 31;
3666 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3668 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3669 + { { 6 /* art */ }, 'i' }
3673 -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
3675 - unsigned tie_t = 0;
3676 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3681 -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3684 - tie_t = (val << 31) >> 31;
3685 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3687 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3688 + { { STATE_WindowBase }, 'o' }
3692 -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
3694 - unsigned tie_t = 0;
3695 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3698 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3699 + { { 6 /* art */ }, 'm' }
3703 -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3706 - tie_t = (val << 31) >> 31;
3707 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3709 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3710 + { { STATE_WindowBase }, 'm' }
3714 -Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
3716 - unsigned tie_t = 0;
3717 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3720 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3721 + { { 6 /* art */ }, 'o' }
3725 -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3728 - tie_t = (val << 31) >> 31;
3729 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3731 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3732 + { { STATE_WindowStart }, 'i' }
3736 -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
3738 - unsigned tie_t = 0;
3739 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3742 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3743 + { { 6 /* art */ }, 'i' }
3747 -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3750 - tie_t = (val << 31) >> 31;
3751 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3753 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3754 + { { STATE_WindowStart }, 'o' }
3758 -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
3760 - unsigned tie_t = 0;
3761 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3764 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3765 + { { 6 /* art */ }, 'm' }
3769 -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3772 - tie_t = (val << 31) >> 31;
3773 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3775 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3776 + { { STATE_WindowStart }, 'm' }
3780 -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
3782 - unsigned tie_t = 0;
3783 - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
3786 +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3787 + { { 3 /* arr */ }, 'o' },
3788 + { { 4 /* ars */ }, 'i' },
3789 + { { 6 /* art */ }, 'i' }
3793 -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3796 - tie_t = (val << 17) >> 17;
3797 - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
3799 +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3800 + { { 3 /* arr */ }, 'o' },
3801 + { { 4 /* ars */ }, 'i' },
3802 + { { 16 /* ai4const */ }, 'i' }
3806 -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
3808 - unsigned tie_t = 0;
3809 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
3812 +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3813 + { { 4 /* ars */ }, 'i' },
3814 + { { 15 /* uimm6 */ }, 'i' }
3818 -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3821 - tie_t = (val << 14) >> 14;
3822 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
3824 +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3825 + { { 6 /* art */ }, 'o' },
3826 + { { 4 /* ars */ }, 'i' },
3827 + { { 13 /* lsi4x4 */ }, 'i' }
3831 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3833 - unsigned tie_t = 0;
3834 - tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
3837 +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3838 + { { 6 /* art */ }, 'o' },
3839 + { { 4 /* ars */ }, 'i' }
3843 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3846 - tie_t = (val << 14) >> 14;
3847 - insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
3849 +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3850 + { { 4 /* ars */ }, 'o' },
3851 + { { 14 /* simm7 */ }, 'i' }
3855 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3857 - unsigned tie_t = 0;
3858 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3861 +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3862 + { { 5 /* *ars_invisible */ }, 'i' }
3866 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3869 - tie_t = (val << 28) >> 28;
3870 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3872 +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3873 + { { 6 /* art */ }, 'i' },
3874 + { { 4 /* ars */ }, 'i' },
3875 + { { 13 /* lsi4x4 */ }, 'i' }
3879 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3881 - unsigned tie_t = 0;
3882 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3885 +static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3886 + { { 3 /* arr */ }, 'o' }
3890 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3893 - tie_t = (val << 29) >> 29;
3894 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3896 +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3897 + { { STATE_THREADPTR }, 'i' }
3901 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3903 - unsigned tie_t = 0;
3904 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3907 +static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3908 + { { 6 /* art */ }, 'i' }
3912 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3915 - tie_t = (val << 29) >> 29;
3916 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3918 +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3919 + { { STATE_THREADPTR }, 'o' }
3923 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3925 - unsigned tie_t = 0;
3926 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3929 +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3930 + { { 6 /* art */ }, 'o' },
3931 + { { 4 /* ars */ }, 'i' },
3932 + { { 23 /* simm8 */ }, 'i' }
3936 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3939 - tie_t = (val << 29) >> 29;
3940 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3942 +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3943 + { { 6 /* art */ }, 'o' },
3944 + { { 4 /* ars */ }, 'i' },
3945 + { { 24 /* simm8x256 */ }, 'i' }
3949 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3951 - unsigned tie_t = 0;
3952 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3955 +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3956 + { { 3 /* arr */ }, 'o' },
3957 + { { 4 /* ars */ }, 'i' },
3958 + { { 6 /* art */ }, 'i' }
3962 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3965 - tie_t = (val << 29) >> 29;
3966 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3968 +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3969 + { { 3 /* arr */ }, 'o' },
3970 + { { 4 /* ars */ }, 'i' },
3971 + { { 6 /* art */ }, 'i' }
3975 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3977 - unsigned tie_t = 0;
3978 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
3979 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3982 +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3983 + { { 4 /* ars */ }, 'i' },
3984 + { { 17 /* b4const */ }, 'i' },
3985 + { { 28 /* label8 */ }, 'i' }
3989 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3992 - tie_t = (val << 28) >> 28;
3993 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
3994 - tie_t = (val << 24) >> 28;
3995 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
3997 +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3998 + { { 4 /* ars */ }, 'i' },
3999 + { { 40 /* bbi */ }, 'i' },
4000 + { { 28 /* label8 */ }, 'i' }
4004 -Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4006 - unsigned tie_t = 0;
4007 - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
4010 +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
4011 + { { 4 /* ars */ }, 'i' },
4012 + { { 18 /* b4constu */ }, 'i' },
4013 + { { 28 /* label8 */ }, 'i' }
4017 -Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4020 - tie_t = (val << 30) >> 30;
4021 - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
4023 +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
4024 + { { 4 /* ars */ }, 'i' },
4025 + { { 6 /* art */ }, 'i' },
4026 + { { 28 /* label8 */ }, 'i' }
4030 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4032 - unsigned tie_t = 0;
4033 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
4036 +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
4037 + { { 4 /* ars */ }, 'i' },
4038 + { { 30 /* label12 */ }, 'i' }
4042 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4045 - tie_t = (val << 28) >> 28;
4046 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
4048 +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
4049 + { { 0 /* soffsetx4 */ }, 'i' },
4050 + { { 7 /* ar0 */ }, 'o' }
4054 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4056 - unsigned tie_t = 0;
4057 - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
4060 +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
4061 + { { 4 /* ars */ }, 'i' },
4062 + { { 7 /* ar0 */ }, 'o' }
4066 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4069 - tie_t = (val << 31) >> 31;
4070 - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
4072 +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
4073 + { { 3 /* arr */ }, 'o' },
4074 + { { 6 /* art */ }, 'i' },
4075 + { { 55 /* sae */ }, 'i' },
4076 + { { 27 /* op2p1 */ }, 'i' }
4080 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4082 - unsigned tie_t = 0;
4083 - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
4086 +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
4087 + { { 31 /* soffset */ }, 'i' }
4091 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4094 - tie_t = (val << 30) >> 30;
4095 - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
4097 +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
4098 + { { 4 /* ars */ }, 'i' }
4102 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4104 - unsigned tie_t = 0;
4105 - tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
4108 +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
4109 + { { 6 /* art */ }, 'o' },
4110 + { { 4 /* ars */ }, 'i' },
4111 + { { 20 /* uimm8x2 */ }, 'i' }
4115 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4118 - tie_t = (val << 27) >> 27;
4119 - insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
4121 +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
4122 + { { 6 /* art */ }, 'o' },
4123 + { { 4 /* ars */ }, 'i' },
4124 + { { 20 /* uimm8x2 */ }, 'i' }
4128 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4130 - unsigned tie_t = 0;
4131 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4134 +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
4135 + { { 6 /* art */ }, 'o' },
4136 + { { 4 /* ars */ }, 'i' },
4137 + { { 21 /* uimm8x4 */ }, 'i' }
4141 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4144 - tie_t = (val << 26) >> 26;
4145 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4147 +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
4148 + { { 6 /* art */ }, 'o' },
4149 + { { 32 /* uimm16x4 */ }, 'i' }
4153 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4155 - unsigned tie_t = 0;
4156 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4157 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4160 +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
4161 + { { STATE_LITBADDR }, 'i' },
4162 + { { STATE_LITBEN }, 'i' }
4166 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4169 - tie_t = (val << 29) >> 29;
4170 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4171 - tie_t = (val << 23) >> 26;
4172 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4174 +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
4175 + { { 6 /* art */ }, 'o' },
4176 + { { 4 /* ars */ }, 'i' },
4177 + { { 19 /* uimm8 */ }, 'i' }
4181 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4183 - unsigned tie_t = 0;
4184 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4185 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4188 +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
4189 + { { 4 /* ars */ }, 'i' },
4190 + { { 29 /* ulabel8 */ }, 'i' }
4194 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4197 - tie_t = (val << 29) >> 29;
4198 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4199 - tie_t = (val << 23) >> 26;
4200 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4202 +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
4203 + { { STATE_LBEG }, 'o' },
4204 + { { STATE_LEND }, 'o' },
4205 + { { STATE_LCOUNT }, 'o' }
4209 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4211 - unsigned tie_t = 0;
4212 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4213 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4216 +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
4217 + { { 4 /* ars */ }, 'i' },
4218 + { { 29 /* ulabel8 */ }, 'i' }
4222 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4225 - tie_t = (val << 30) >> 30;
4226 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4227 - tie_t = (val << 24) >> 26;
4228 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4230 +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
4231 + { { STATE_LBEG }, 'o' },
4232 + { { STATE_LEND }, 'o' },
4233 + { { STATE_LCOUNT }, 'o' }
4237 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4239 - unsigned tie_t = 0;
4240 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4241 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
4244 +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
4245 + { { 6 /* art */ }, 'o' },
4246 + { { 25 /* simm12b */ }, 'i' }
4250 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4253 - tie_t = (val << 31) >> 31;
4254 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
4255 - tie_t = (val << 25) >> 26;
4256 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4258 +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
4259 + { { 3 /* arr */ }, 'm' },
4260 + { { 4 /* ars */ }, 'i' },
4261 + { { 6 /* art */ }, 'i' }
4265 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4267 - unsigned tie_t = 0;
4268 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4269 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4272 +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
4273 + { { 3 /* arr */ }, 'o' },
4274 + { { 6 /* art */ }, 'i' }
4278 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4281 - tie_t = (val << 30) >> 30;
4282 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4283 - tie_t = (val << 24) >> 26;
4284 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4286 +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
4287 + { { 5 /* *ars_invisible */ }, 'i' }
4291 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4293 - unsigned tie_t = 0;
4294 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4295 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4298 +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
4299 + { { 6 /* art */ }, 'i' },
4300 + { { 4 /* ars */ }, 'i' },
4301 + { { 20 /* uimm8x2 */ }, 'i' }
4305 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4308 - tie_t = (val << 30) >> 30;
4309 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4310 - tie_t = (val << 24) >> 26;
4311 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4313 +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
4314 + { { 6 /* art */ }, 'i' },
4315 + { { 4 /* ars */ }, 'i' },
4316 + { { 21 /* uimm8x4 */ }, 'i' }
4320 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4322 - unsigned tie_t = 0;
4323 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4324 - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
4327 +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
4328 + { { 6 /* art */ }, 'i' },
4329 + { { 4 /* ars */ }, 'i' },
4330 + { { 19 /* uimm8 */ }, 'i' }
4334 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4337 - tie_t = (val << 31) >> 31;
4338 - insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
4339 - tie_t = (val << 25) >> 26;
4340 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4342 +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
4343 + { { 4 /* ars */ }, 'i' }
4347 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4349 - unsigned tie_t = 0;
4350 - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
4353 +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
4354 + { { STATE_SAR }, 'o' }
4358 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4361 - tie_t = (val << 29) >> 29;
4362 - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
4364 +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
4365 + { { 59 /* sas */ }, 'i' }
4369 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4371 - unsigned tie_t = 0;
4372 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4375 +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
4376 + { { STATE_SAR }, 'o' }
4380 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4383 - tie_t = (val << 31) >> 31;
4384 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4386 +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
4387 + { { 3 /* arr */ }, 'o' },
4388 + { { 4 /* ars */ }, 'i' }
4392 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4394 - unsigned tie_t = 0;
4395 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4396 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4399 +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
4400 + { { STATE_SAR }, 'i' }
4404 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4407 - tie_t = (val << 28) >> 28;
4408 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4409 - tie_t = (val << 27) >> 31;
4410 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4412 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
4413 + { { 3 /* arr */ }, 'o' },
4414 + { { 4 /* ars */ }, 'i' },
4415 + { { 6 /* art */ }, 'i' }
4419 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4421 - unsigned tie_t = 0;
4422 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4425 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
4426 + { { STATE_SAR }, 'i' }
4430 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4433 - tie_t = (val << 30) >> 30;
4434 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4436 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
4437 + { { 3 /* arr */ }, 'o' },
4438 + { { 6 /* art */ }, 'i' }
4442 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4444 - unsigned tie_t = 0;
4445 - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
4446 - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
4449 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
4450 + { { STATE_SAR }, 'i' }
4454 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4457 - tie_t = (val << 26) >> 26;
4458 - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
4459 - tie_t = (val << 21) >> 27;
4460 - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
4462 +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
4463 + { { 3 /* arr */ }, 'o' },
4464 + { { 4 /* ars */ }, 'i' },
4465 + { { 26 /* msalp32 */ }, 'i' }
4469 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4471 - unsigned tie_t = 0;
4472 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4473 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4476 +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
4477 + { { 3 /* arr */ }, 'o' },
4478 + { { 6 /* art */ }, 'i' },
4479 + { { 57 /* sargt */ }, 'i' }
4483 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4486 - tie_t = (val << 28) >> 28;
4487 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4488 - tie_t = (val << 27) >> 31;
4489 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4491 +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
4492 + { { 3 /* arr */ }, 'o' },
4493 + { { 6 /* art */ }, 'i' },
4494 + { { 43 /* s */ }, 'i' }
4498 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4500 - unsigned tie_t = 0;
4501 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4502 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4505 +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
4506 + { { STATE_XTSYNC }, 'i' }
4510 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4513 - tie_t = (val << 31) >> 31;
4514 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4515 - tie_t = (val << 29) >> 30;
4516 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4518 +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
4519 + { { 6 /* art */ }, 'o' },
4520 + { { 43 /* s */ }, 'i' }
4524 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4526 - unsigned tie_t = 0;
4527 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4528 - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
4531 +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
4532 + { { STATE_PSWOE }, 'i' },
4533 + { { STATE_PSCALLINC }, 'i' },
4534 + { { STATE_PSOWB }, 'i' },
4535 + { { STATE_PSUM }, 'i' },
4536 + { { STATE_PSEXCM }, 'i' },
4537 + { { STATE_PSINTLEVEL }, 'm' }
4541 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4544 - tie_t = (val << 27) >> 27;
4545 - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
4546 - tie_t = (val << 26) >> 31;
4547 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4549 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
4550 + { { 6 /* art */ }, 'o' }
4554 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4556 - unsigned tie_t = 0;
4557 - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
4560 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
4561 + { { STATE_LEND }, 'i' }
4565 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4568 - tie_t = (val << 29) >> 29;
4569 - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
4571 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
4572 + { { 6 /* art */ }, 'i' }
4576 -Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4578 - unsigned tie_t = 0;
4579 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
4582 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
4583 + { { STATE_LEND }, 'o' }
4587 -Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4590 - tie_t = (val << 29) >> 29;
4591 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
4593 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
4594 + { { 6 /* art */ }, 'm' }
4598 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4600 - unsigned tie_t = 0;
4601 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4604 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
4605 + { { STATE_LEND }, 'm' }
4609 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4612 - tie_t = (val << 31) >> 31;
4613 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4615 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
4616 + { { 6 /* art */ }, 'o' }
4620 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4622 - unsigned tie_t = 0;
4623 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4624 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4627 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
4628 + { { STATE_LCOUNT }, 'i' }
4632 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4635 - tie_t = (val << 31) >> 31;
4636 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4637 - tie_t = (val << 30) >> 31;
4638 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4640 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
4641 + { { 6 /* art */ }, 'i' }
4645 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4647 - unsigned tie_t = 0;
4648 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4649 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4650 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4653 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
4654 + { { STATE_XTSYNC }, 'o' },
4655 + { { STATE_LCOUNT }, 'o' }
4659 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4662 - tie_t = (val << 31) >> 31;
4663 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4664 - tie_t = (val << 30) >> 31;
4665 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4666 - tie_t = (val << 29) >> 31;
4667 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4669 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
4670 + { { 6 /* art */ }, 'm' }
4674 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4676 - unsigned tie_t = 0;
4677 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4678 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4679 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4682 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
4683 + { { STATE_XTSYNC }, 'o' },
4684 + { { STATE_LCOUNT }, 'm' }
4688 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4691 - tie_t = (val << 31) >> 31;
4692 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4693 - tie_t = (val << 30) >> 31;
4694 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4695 - tie_t = (val << 29) >> 31;
4696 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4698 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
4699 + { { 6 /* art */ }, 'o' }
4703 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4705 - unsigned tie_t = 0;
4706 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4707 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4710 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
4711 + { { STATE_LBEG }, 'i' }
4715 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4718 - tie_t = (val << 29) >> 29;
4719 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4720 - tie_t = (val << 28) >> 31;
4721 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4723 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
4724 + { { 6 /* art */ }, 'i' }
4728 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4730 - unsigned tie_t = 0;
4731 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4732 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4735 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
4736 + { { STATE_LBEG }, 'o' }
4740 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4743 - tie_t = (val << 29) >> 29;
4744 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4745 - tie_t = (val << 28) >> 31;
4746 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4748 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
4749 + { { 6 /* art */ }, 'm' }
4753 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4755 - unsigned tie_t = 0;
4756 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4757 - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
4760 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
4761 + { { STATE_LBEG }, 'm' }
4765 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4768 - tie_t = (val << 30) >> 30;
4769 - insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
4770 - tie_t = (val << 29) >> 31;
4771 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4773 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
4774 + { { 6 /* art */ }, 'o' }
4778 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4780 - unsigned tie_t = 0;
4781 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4782 - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
4785 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
4786 + { { STATE_SAR }, 'i' }
4790 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4793 - tie_t = (val << 31) >> 31;
4794 - insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
4795 - tie_t = (val << 30) >> 31;
4796 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4798 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
4799 + { { 6 /* art */ }, 'i' }
4803 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4805 - unsigned tie_t = 0;
4806 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4809 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
4810 + { { STATE_SAR }, 'o' },
4811 + { { STATE_XTSYNC }, 'o' }
4815 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4818 - tie_t = (val << 30) >> 30;
4819 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4821 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
4822 + { { 6 /* art */ }, 'm' }
4826 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4828 - unsigned tie_t = 0;
4829 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4832 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
4833 + { { STATE_SAR }, 'm' }
4837 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4840 - tie_t = (val << 31) >> 31;
4841 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4843 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
4844 + { { 6 /* art */ }, 'o' }
4848 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4850 - unsigned tie_t = 0;
4851 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
4852 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4853 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4856 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
4857 + { { STATE_LITBADDR }, 'i' },
4858 + { { STATE_LITBEN }, 'i' }
4862 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4865 - tie_t = (val << 28) >> 28;
4866 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4867 - tie_t = (val << 26) >> 30;
4868 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4869 - tie_t = (val << 22) >> 28;
4870 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4872 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
4873 + { { 6 /* art */ }, 'i' }
4877 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4879 - unsigned tie_t = 0;
4880 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4881 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4884 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
4885 + { { STATE_LITBADDR }, 'o' },
4886 + { { STATE_LITBEN }, 'o' }
4890 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4893 - tie_t = (val << 31) >> 31;
4894 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4895 - tie_t = (val << 30) >> 31;
4896 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4898 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
4899 + { { 6 /* art */ }, 'm' }
4903 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4905 - unsigned tie_t = 0;
4906 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4907 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4910 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
4911 + { { STATE_LITBADDR }, 'm' },
4912 + { { STATE_LITBEN }, 'm' }
4916 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4919 - tie_t = (val << 30) >> 30;
4920 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4921 - tie_t = (val << 29) >> 31;
4922 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4924 +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
4925 + { { 6 /* art */ }, 'o' }
4929 -Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4931 - unsigned tie_t = 0;
4932 - tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
4935 +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
4936 + { { 6 /* art */ }, 'o' }
4940 -Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4943 - tie_t = (val << 27) >> 27;
4944 - insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
4946 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
4947 + { { 6 /* art */ }, 'o' }
4951 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4953 - unsigned tie_t = 0;
4954 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
4955 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
4956 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4959 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
4960 + { { STATE_PSWOE }, 'i' },
4961 + { { STATE_PSCALLINC }, 'i' },
4962 + { { STATE_PSOWB }, 'i' },
4963 + { { STATE_PSUM }, 'i' },
4964 + { { STATE_PSEXCM }, 'i' },
4965 + { { STATE_PSINTLEVEL }, 'i' }
4969 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4972 - tie_t = (val << 28) >> 28;
4973 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4974 - tie_t = (val << 27) >> 31;
4975 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
4976 - tie_t = (val << 24) >> 29;
4977 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
4979 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
4980 + { { 6 /* art */ }, 'i' }
4984 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4986 - unsigned tie_t = 0;
4987 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
4990 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
4991 + { { STATE_PSWOE }, 'o' },
4992 + { { STATE_PSCALLINC }, 'o' },
4993 + { { STATE_PSOWB }, 'o' },
4994 + { { STATE_PSUM }, 'o' },
4995 + { { STATE_PSEXCM }, 'o' },
4996 + { { STATE_PSINTLEVEL }, 'o' }
5000 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5003 - tie_t = (val << 29) >> 29;
5004 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5006 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
5007 + { { 6 /* art */ }, 'm' }
5011 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5013 - unsigned tie_t = 0;
5014 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5015 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5016 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5019 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
5020 + { { STATE_PSWOE }, 'm' },
5021 + { { STATE_PSCALLINC }, 'm' },
5022 + { { STATE_PSOWB }, 'm' },
5023 + { { STATE_PSUM }, 'm' },
5024 + { { STATE_PSEXCM }, 'm' },
5025 + { { STATE_PSINTLEVEL }, 'm' }
5029 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5032 - tie_t = (val << 28) >> 28;
5033 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5034 - tie_t = (val << 27) >> 31;
5035 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5036 - tie_t = (val << 24) >> 29;
5037 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5039 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
5040 + { { 6 /* art */ }, 'o' }
5044 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5046 - unsigned tie_t = 0;
5047 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5048 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5049 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5054 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5057 - tie_t = (val << 28) >> 28;
5058 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5059 - tie_t = (val << 27) >> 31;
5060 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5061 - tie_t = (val << 24) >> 29;
5062 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5064 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
5065 + { { STATE_EPC1 }, 'i' }
5069 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5071 - unsigned tie_t = 0;
5072 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5073 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5074 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5077 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
5078 + { { 6 /* art */ }, 'i' }
5082 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5085 - tie_t = (val << 28) >> 28;
5086 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5087 - tie_t = (val << 27) >> 31;
5088 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5089 - tie_t = (val << 24) >> 29;
5090 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5092 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
5093 + { { STATE_EPC1 }, 'o' }
5097 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5099 - unsigned tie_t = 0;
5100 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5101 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5104 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
5105 + { { 6 /* art */ }, 'm' }
5109 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5112 - tie_t = (val << 31) >> 31;
5113 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5114 - tie_t = (val << 28) >> 29;
5115 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5117 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
5118 + { { STATE_EPC1 }, 'm' }
5122 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5124 - unsigned tie_t = 0;
5125 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5126 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5129 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
5130 + { { 6 /* art */ }, 'o' }
5134 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5137 - tie_t = (val << 31) >> 31;
5138 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5139 - tie_t = (val << 28) >> 29;
5140 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5142 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
5143 + { { STATE_EXCSAVE1 }, 'i' }
5147 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5149 - unsigned tie_t = 0;
5150 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5151 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5154 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
5155 + { { 6 /* art */ }, 'i' }
5159 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5162 - tie_t = (val << 31) >> 31;
5163 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5164 - tie_t = (val << 28) >> 29;
5165 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5167 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
5168 + { { STATE_EXCSAVE1 }, 'o' }
5172 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5174 - unsigned tie_t = 0;
5175 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5176 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5179 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
5180 + { { 6 /* art */ }, 'm' }
5184 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5187 - tie_t = (val << 31) >> 31;
5188 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5189 - tie_t = (val << 28) >> 29;
5190 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5192 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
5193 + { { STATE_EXCSAVE1 }, 'm' }
5197 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5199 - unsigned tie_t = 0;
5200 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5201 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5204 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
5205 + { { 6 /* art */ }, 'o' }
5209 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5212 - tie_t = (val << 31) >> 31;
5213 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5214 - tie_t = (val << 28) >> 29;
5215 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5217 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
5218 + { { STATE_EPC2 }, 'i' }
5222 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5224 - unsigned tie_t = 0;
5225 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5226 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5229 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
5230 + { { 6 /* art */ }, 'i' }
5234 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5237 - tie_t = (val << 31) >> 31;
5238 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5239 - tie_t = (val << 28) >> 29;
5240 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5242 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
5243 + { { STATE_EPC2 }, 'o' }
5247 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5249 - unsigned tie_t = 0;
5250 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5251 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5254 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
5255 + { { 6 /* art */ }, 'm' }
5259 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5262 - tie_t = (val << 31) >> 31;
5263 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5264 - tie_t = (val << 28) >> 29;
5265 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5267 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
5268 + { { STATE_EPC2 }, 'm' }
5272 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5274 - unsigned tie_t = 0;
5275 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5276 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5279 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
5280 + { { 6 /* art */ }, 'o' }
5284 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5287 - tie_t = (val << 31) >> 31;
5288 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5289 - tie_t = (val << 28) >> 29;
5290 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5292 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
5293 + { { STATE_EXCSAVE2 }, 'i' }
5297 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5299 - unsigned tie_t = 0;
5300 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5301 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5304 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
5305 + { { 6 /* art */ }, 'i' }
5309 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5312 - tie_t = (val << 31) >> 31;
5313 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5314 - tie_t = (val << 28) >> 29;
5315 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5317 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
5318 + { { STATE_EXCSAVE2 }, 'o' }
5322 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5324 - unsigned tie_t = 0;
5325 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5326 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5329 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
5330 + { { 6 /* art */ }, 'm' }
5334 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5337 - tie_t = (val << 31) >> 31;
5338 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5339 - tie_t = (val << 28) >> 29;
5340 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5342 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
5343 + { { STATE_EXCSAVE2 }, 'm' }
5347 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5349 - unsigned tie_t = 0;
5350 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5351 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5354 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
5355 + { { 6 /* art */ }, 'o' }
5359 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5362 - tie_t = (val << 31) >> 31;
5363 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5364 - tie_t = (val << 28) >> 29;
5365 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5367 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
5368 + { { STATE_EPC3 }, 'i' }
5372 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5374 - unsigned tie_t = 0;
5375 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5376 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5379 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
5380 + { { 6 /* art */ }, 'i' }
5384 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5387 - tie_t = (val << 31) >> 31;
5388 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5389 - tie_t = (val << 28) >> 29;
5390 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5392 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
5393 + { { STATE_EPC3 }, 'o' }
5397 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5399 - unsigned tie_t = 0;
5400 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5401 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5404 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
5405 + { { 6 /* art */ }, 'm' }
5409 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5412 - tie_t = (val << 31) >> 31;
5413 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5414 - tie_t = (val << 28) >> 29;
5415 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5417 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
5418 + { { STATE_EPC3 }, 'm' }
5422 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5424 - unsigned tie_t = 0;
5425 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5426 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5429 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
5430 + { { 6 /* art */ }, 'o' }
5434 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5437 - tie_t = (val << 31) >> 31;
5438 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5439 - tie_t = (val << 28) >> 29;
5440 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5442 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
5443 + { { STATE_EXCSAVE3 }, 'i' }
5447 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5449 - unsigned tie_t = 0;
5450 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5451 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5454 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
5455 + { { 6 /* art */ }, 'i' }
5459 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5462 - tie_t = (val << 31) >> 31;
5463 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5464 - tie_t = (val << 28) >> 29;
5465 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5467 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
5468 + { { STATE_EXCSAVE3 }, 'o' }
5472 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5474 - unsigned tie_t = 0;
5475 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5476 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5479 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
5480 + { { 6 /* art */ }, 'm' }
5484 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5487 - tie_t = (val << 31) >> 31;
5488 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5489 - tie_t = (val << 28) >> 29;
5490 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5492 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
5493 + { { STATE_EXCSAVE3 }, 'm' }
5497 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5499 - unsigned tie_t = 0;
5500 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5501 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5504 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
5505 + { { 6 /* art */ }, 'o' }
5509 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5512 - tie_t = (val << 31) >> 31;
5513 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5514 - tie_t = (val << 28) >> 29;
5515 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5517 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
5518 + { { STATE_EPC4 }, 'i' }
5522 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5524 - unsigned tie_t = 0;
5525 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5526 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5529 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
5530 + { { 6 /* art */ }, 'i' }
5534 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5537 - tie_t = (val << 31) >> 31;
5538 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5539 - tie_t = (val << 28) >> 29;
5540 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5542 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
5543 + { { STATE_EPC4 }, 'o' }
5547 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5549 - unsigned tie_t = 0;
5550 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5551 - tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
5554 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
5555 + { { 6 /* art */ }, 'm' }
5559 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5562 - tie_t = (val << 5) >> 5;
5563 - insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
5564 - tie_t = (val << 2) >> 29;
5565 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5567 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
5568 + { { STATE_EPC4 }, 'm' }
5572 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
5574 - unsigned tie_t = 0;
5575 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
5578 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
5579 + { { 6 /* art */ }, 'o' }
5583 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
5586 - tie_t = (val << 28) >> 28;
5587 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
5589 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
5590 + { { STATE_EXCSAVE4 }, 'i' }
5594 -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
5595 - uint32 val ATTRIBUTE_UNUSED)
5599 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
5600 + { { 6 /* art */ }, 'i' }
5604 -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5608 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
5609 + { { STATE_EXCSAVE4 }, 'o' }
5613 -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5617 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
5618 + { { 6 /* art */ }, 'm' }
5622 -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5626 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
5627 + { { STATE_EXCSAVE4 }, 'm' }
5631 -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5635 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
5636 + { { 6 /* art */ }, 'o' }
5640 -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5644 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
5645 + { { STATE_EPC5 }, 'i' }
5649 -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5653 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
5654 + { { 6 /* art */ }, 'i' }
5658 -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5662 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
5663 + { { STATE_EPC5 }, 'o' }
5667 -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5671 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
5672 + { { 6 /* art */ }, 'm' }
5676 -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5680 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
5681 + { { STATE_EPC5 }, 'm' }
5685 -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5689 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
5690 + { { 6 /* art */ }, 'o' }
5694 -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5698 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
5699 + { { STATE_EXCSAVE5 }, 'i' }
5703 -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5707 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
5708 + { { 6 /* art */ }, 'i' }
5712 -/* Functional units. */
5713 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
5714 + { { STATE_EXCSAVE5 }, 'o' }
5717 -static xtensa_funcUnit_internal funcUnits[] = {
5718 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
5719 + { { 6 /* art */ }, 'm' }
5722 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
5723 + { { STATE_EXCSAVE5 }, 'm' }
5727 -/* Register files. */
5728 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
5729 + { { 6 /* art */ }, 'o' }
5732 -static xtensa_regfile_internal regfiles[] = {
5733 - { "AR", "a", 0, 32, 64 },
5734 - { "MR", "m", 1, 32, 4 },
5735 - { "BR", "b", 2, 1, 16 },
5736 - { "FR", "f", 3, 32, 16 },
5737 - { "BR2", "b", 2, 2, 8 },
5738 - { "BR4", "b", 2, 4, 4 },
5739 - { "BR8", "b", 2, 8, 2 },
5740 - { "BR16", "b", 2, 16, 1 }
5741 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
5742 + { { STATE_EPS2 }, 'i' }
5747 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
5748 + { { 6 /* art */ }, 'i' }
5751 -static xtensa_interface_internal interfaces[] = {
5752 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
5753 + { { STATE_EPS2 }, 'o' }
5756 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
5757 + { { 6 /* art */ }, 'm' }
5761 -/* Constant tables. */
5762 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
5763 + { { STATE_EPS2 }, 'm' }
5766 -/* constant table ai4c */
5767 -static const unsigned CONST_TBL_ai4c_0[] = {
5785 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
5786 + { { 6 /* art */ }, 'o' }
5789 -/* constant table b4c */
5790 -static const unsigned CONST_TBL_b4c_0[] = {
5808 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
5809 + { { STATE_EPS3 }, 'i' }
5812 -/* constant table b4cu */
5813 -static const unsigned CONST_TBL_b4cu_0[] = {
5831 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
5832 + { { 6 /* art */ }, 'i' }
5836 -/* Instruction operands. */
5839 -Operand_soffsetx4_decode (uint32 *valp)
5841 - unsigned soffsetx4_0, offset_0;
5842 - offset_0 = *valp & 0x3ffff;
5843 - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
5844 - *valp = soffsetx4_0;
5847 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
5848 + { { STATE_EPS3 }, 'o' }
5852 -Operand_soffsetx4_encode (uint32 *valp)
5854 - unsigned offset_0, soffsetx4_0;
5855 - soffsetx4_0 = *valp;
5856 - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
5860 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
5861 + { { 6 /* art */ }, 'm' }
5865 -Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
5867 - *valp -= (pc & ~0x3);
5870 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
5871 + { { STATE_EPS3 }, 'm' }
5875 -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
5877 - *valp += (pc & ~0x3);
5880 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
5881 + { { 6 /* art */ }, 'o' }
5885 -Operand_uimm12x8_decode (uint32 *valp)
5887 - unsigned uimm12x8_0, imm12_0;
5888 - imm12_0 = *valp & 0xfff;
5889 - uimm12x8_0 = imm12_0 << 3;
5890 - *valp = uimm12x8_0;
5893 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
5894 + { { STATE_EPS4 }, 'i' }
5898 -Operand_uimm12x8_encode (uint32 *valp)
5900 - unsigned imm12_0, uimm12x8_0;
5901 - uimm12x8_0 = *valp;
5902 - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
5906 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
5907 + { { 6 /* art */ }, 'i' }
5911 -Operand_simm4_decode (uint32 *valp)
5913 - unsigned simm4_0, mn_0;
5914 - mn_0 = *valp & 0xf;
5915 - simm4_0 = ((int) mn_0 << 28) >> 28;
5919 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
5920 + { { STATE_EPS4 }, 'o' }
5924 -Operand_simm4_encode (uint32 *valp)
5926 - unsigned mn_0, simm4_0;
5928 - mn_0 = (simm4_0 & 0xf);
5932 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
5933 + { { 6 /* art */ }, 'm' }
5937 -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5941 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
5942 + { { STATE_EPS4 }, 'm' }
5946 -Operand_arr_encode (uint32 *valp)
5949 - error = (*valp & ~0xf) != 0;
5952 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
5953 + { { 6 /* art */ }, 'o' }
5957 -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
5961 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
5962 + { { STATE_EPS5 }, 'i' }
5966 -Operand_ars_encode (uint32 *valp)
5969 - error = (*valp & ~0xf) != 0;
5972 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
5973 + { { 6 /* art */ }, 'i' }
5977 -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
5981 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
5982 + { { STATE_EPS5 }, 'o' }
5986 -Operand_art_encode (uint32 *valp)
5989 - error = (*valp & ~0xf) != 0;
5992 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
5993 + { { 6 /* art */ }, 'm' }
5997 -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6001 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6002 + { { STATE_EPS5 }, 'm' }
6006 -Operand_ar0_encode (uint32 *valp)
6009 - error = (*valp & ~0x3f) != 0;
6012 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6013 + { { 6 /* art */ }, 'o' }
6017 -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
6021 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6022 + { { STATE_EXCVADDR }, 'i' }
6026 -Operand_ar4_encode (uint32 *valp)
6029 - error = (*valp & ~0x3f) != 0;
6032 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6033 + { { 6 /* art */ }, 'i' }
6037 -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
6041 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6042 + { { STATE_EXCVADDR }, 'o' }
6046 -Operand_ar8_encode (uint32 *valp)
6049 - error = (*valp & ~0x3f) != 0;
6052 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6053 + { { 6 /* art */ }, 'm' }
6057 -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
6061 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6062 + { { STATE_EXCVADDR }, 'm' }
6066 -Operand_ar12_encode (uint32 *valp)
6069 - error = (*valp & ~0x3f) != 0;
6072 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6073 + { { 6 /* art */ }, 'o' }
6077 -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
6081 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6082 + { { STATE_DEPC }, 'i' }
6086 -Operand_ars_entry_encode (uint32 *valp)
6089 - error = (*valp & ~0x3f) != 0;
6092 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6093 + { { 6 /* art */ }, 'i' }
6097 -Operand_immrx4_decode (uint32 *valp)
6099 - unsigned immrx4_0, r_0;
6100 - r_0 = *valp & 0xf;
6101 - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
6105 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6106 + { { STATE_DEPC }, 'o' }
6110 -Operand_immrx4_encode (uint32 *valp)
6112 - unsigned r_0, immrx4_0;
6114 - r_0 = ((immrx4_0 >> 2) & 0xf);
6118 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6119 + { { 6 /* art */ }, 'm' }
6123 -Operand_lsi4x4_decode (uint32 *valp)
6125 - unsigned lsi4x4_0, r_0;
6126 - r_0 = *valp & 0xf;
6127 - lsi4x4_0 = r_0 << 2;
6131 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6132 + { { STATE_DEPC }, 'm' }
6136 -Operand_lsi4x4_encode (uint32 *valp)
6138 - unsigned r_0, lsi4x4_0;
6140 - r_0 = ((lsi4x4_0 >> 2) & 0xf);
6144 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6145 + { { 6 /* art */ }, 'o' }
6149 -Operand_simm7_decode (uint32 *valp)
6151 - unsigned simm7_0, imm7_0;
6152 - imm7_0 = *valp & 0x7f;
6153 - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
6157 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6158 + { { STATE_EXCCAUSE }, 'i' },
6159 + { { STATE_XTSYNC }, 'i' }
6163 -Operand_simm7_encode (uint32 *valp)
6165 - unsigned imm7_0, simm7_0;
6167 - imm7_0 = (simm7_0 & 0x7f);
6171 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6172 + { { 6 /* art */ }, 'i' }
6176 -Operand_uimm6_decode (uint32 *valp)
6178 - unsigned uimm6_0, imm6_0;
6179 - imm6_0 = *valp & 0x3f;
6180 - uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
6184 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6185 + { { STATE_EXCCAUSE }, 'o' }
6189 -Operand_uimm6_encode (uint32 *valp)
6191 - unsigned imm6_0, uimm6_0;
6193 - imm6_0 = (uimm6_0 - 0x4) & 0x3f;
6197 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6198 + { { 6 /* art */ }, 'm' }
6202 -Operand_uimm6_ator (uint32 *valp, uint32 pc)
6207 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6208 + { { STATE_EXCCAUSE }, 'm' }
6212 -Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
6217 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6218 + { { 6 /* art */ }, 'o' }
6222 -Operand_ai4const_decode (uint32 *valp)
6224 - unsigned ai4const_0, t_0;
6225 - t_0 = *valp & 0xf;
6226 - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
6227 - *valp = ai4const_0;
6230 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6231 + { { STATE_MISC0 }, 'i' }
6235 -Operand_ai4const_encode (uint32 *valp)
6237 - unsigned t_0, ai4const_0;
6238 - ai4const_0 = *valp;
6239 - switch (ai4const_0)
6241 - case 0xffffffff: t_0 = 0; break;
6242 - case 0x1: t_0 = 0x1; break;
6243 - case 0x2: t_0 = 0x2; break;
6244 - case 0x3: t_0 = 0x3; break;
6245 - case 0x4: t_0 = 0x4; break;
6246 - case 0x5: t_0 = 0x5; break;
6247 - case 0x6: t_0 = 0x6; break;
6248 - case 0x7: t_0 = 0x7; break;
6249 - case 0x8: t_0 = 0x8; break;
6250 - case 0x9: t_0 = 0x9; break;
6251 - case 0xa: t_0 = 0xa; break;
6252 - case 0xb: t_0 = 0xb; break;
6253 - case 0xc: t_0 = 0xc; break;
6254 - case 0xd: t_0 = 0xd; break;
6255 - case 0xe: t_0 = 0xe; break;
6256 - default: t_0 = 0xf; break;
6261 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6262 + { { 6 /* art */ }, 'i' }
6266 -Operand_b4const_decode (uint32 *valp)
6268 - unsigned b4const_0, r_0;
6269 - r_0 = *valp & 0xf;
6270 - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
6271 - *valp = b4const_0;
6274 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6275 + { { STATE_MISC0 }, 'o' }
6279 -Operand_b4const_encode (uint32 *valp)
6281 - unsigned r_0, b4const_0;
6282 - b4const_0 = *valp;
6283 - switch (b4const_0)
6285 - case 0xffffffff: r_0 = 0; break;
6286 - case 0x1: r_0 = 0x1; break;
6287 - case 0x2: r_0 = 0x2; break;
6288 - case 0x3: r_0 = 0x3; break;
6289 - case 0x4: r_0 = 0x4; break;
6290 - case 0x5: r_0 = 0x5; break;
6291 - case 0x6: r_0 = 0x6; break;
6292 - case 0x7: r_0 = 0x7; break;
6293 - case 0x8: r_0 = 0x8; break;
6294 - case 0xa: r_0 = 0x9; break;
6295 - case 0xc: r_0 = 0xa; break;
6296 - case 0x10: r_0 = 0xb; break;
6297 - case 0x20: r_0 = 0xc; break;
6298 - case 0x40: r_0 = 0xd; break;
6299 - case 0x80: r_0 = 0xe; break;
6300 - default: r_0 = 0xf; break;
6305 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6306 + { { 6 /* art */ }, 'm' }
6310 -Operand_b4constu_decode (uint32 *valp)
6312 - unsigned b4constu_0, r_0;
6313 - r_0 = *valp & 0xf;
6314 - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
6315 - *valp = b4constu_0;
6318 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6319 + { { STATE_MISC0 }, 'm' }
6323 -Operand_b4constu_encode (uint32 *valp)
6325 - unsigned r_0, b4constu_0;
6326 - b4constu_0 = *valp;
6327 - switch (b4constu_0)
6329 - case 0x8000: r_0 = 0; break;
6330 - case 0x10000: r_0 = 0x1; break;
6331 - case 0x2: r_0 = 0x2; break;
6332 - case 0x3: r_0 = 0x3; break;
6333 - case 0x4: r_0 = 0x4; break;
6334 - case 0x5: r_0 = 0x5; break;
6335 - case 0x6: r_0 = 0x6; break;
6336 - case 0x7: r_0 = 0x7; break;
6337 - case 0x8: r_0 = 0x8; break;
6338 - case 0xa: r_0 = 0x9; break;
6339 - case 0xc: r_0 = 0xa; break;
6340 - case 0x10: r_0 = 0xb; break;
6341 - case 0x20: r_0 = 0xc; break;
6342 - case 0x40: r_0 = 0xd; break;
6343 - case 0x80: r_0 = 0xe; break;
6344 - default: r_0 = 0xf; break;
6349 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6350 + { { 6 /* art */ }, 'o' }
6354 -Operand_uimm8_decode (uint32 *valp)
6356 - unsigned uimm8_0, imm8_0;
6357 - imm8_0 = *valp & 0xff;
6362 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6363 + { { STATE_MISC1 }, 'i' }
6367 -Operand_uimm8_encode (uint32 *valp)
6369 - unsigned imm8_0, uimm8_0;
6371 - imm8_0 = (uimm8_0 & 0xff);
6375 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
6376 + { { 6 /* art */ }, 'i' }
6380 -Operand_uimm8x2_decode (uint32 *valp)
6382 - unsigned uimm8x2_0, imm8_0;
6383 - imm8_0 = *valp & 0xff;
6384 - uimm8x2_0 = imm8_0 << 1;
6385 - *valp = uimm8x2_0;
6388 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
6389 + { { STATE_MISC1 }, 'o' }
6393 -Operand_uimm8x2_encode (uint32 *valp)
6395 - unsigned imm8_0, uimm8x2_0;
6396 - uimm8x2_0 = *valp;
6397 - imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
6401 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
6402 + { { 6 /* art */ }, 'm' }
6406 -Operand_uimm8x4_decode (uint32 *valp)
6408 - unsigned uimm8x4_0, imm8_0;
6409 - imm8_0 = *valp & 0xff;
6410 - uimm8x4_0 = imm8_0 << 2;
6411 - *valp = uimm8x4_0;
6414 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
6415 + { { STATE_MISC1 }, 'm' }
6419 -Operand_uimm8x4_encode (uint32 *valp)
6421 - unsigned imm8_0, uimm8x4_0;
6422 - uimm8x4_0 = *valp;
6423 - imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
6427 +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
6428 + { { 6 /* art */ }, 'o' }
6432 -Operand_uimm4x16_decode (uint32 *valp)
6434 - unsigned uimm4x16_0, op2_0;
6435 - op2_0 = *valp & 0xf;
6436 - uimm4x16_0 = op2_0 << 4;
6437 - *valp = uimm4x16_0;
6440 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
6441 + { { 6 /* art */ }, 'o' }
6445 -Operand_uimm4x16_encode (uint32 *valp)
6447 - unsigned op2_0, uimm4x16_0;
6448 - uimm4x16_0 = *valp;
6449 - op2_0 = ((uimm4x16_0 >> 4) & 0xf);
6453 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
6454 + { { STATE_VECBASE }, 'i' }
6458 -Operand_simm8_decode (uint32 *valp)
6460 - unsigned simm8_0, imm8_0;
6461 - imm8_0 = *valp & 0xff;
6462 - simm8_0 = ((int) imm8_0 << 24) >> 24;
6466 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
6467 + { { 6 /* art */ }, 'i' }
6471 -Operand_simm8_encode (uint32 *valp)
6473 - unsigned imm8_0, simm8_0;
6475 - imm8_0 = (simm8_0 & 0xff);
6479 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
6480 + { { STATE_VECBASE }, 'o' }
6484 -Operand_simm8x256_decode (uint32 *valp)
6486 - unsigned simm8x256_0, imm8_0;
6487 - imm8_0 = *valp & 0xff;
6488 - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
6489 - *valp = simm8x256_0;
6492 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
6493 + { { 6 /* art */ }, 'm' }
6497 -Operand_simm8x256_encode (uint32 *valp)
6499 - unsigned imm8_0, simm8x256_0;
6500 - simm8x256_0 = *valp;
6501 - imm8_0 = ((simm8x256_0 >> 8) & 0xff);
6505 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
6506 + { { STATE_VECBASE }, 'm' }
6510 -Operand_simm12b_decode (uint32 *valp)
6512 - unsigned simm12b_0, imm12b_0;
6513 - imm12b_0 = *valp & 0xfff;
6514 - simm12b_0 = ((int) imm12b_0 << 20) >> 20;
6515 - *valp = simm12b_0;
6518 +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
6519 + { { 43 /* s */ }, 'i' }
6523 -Operand_simm12b_encode (uint32 *valp)
6525 - unsigned imm12b_0, simm12b_0;
6526 - simm12b_0 = *valp;
6527 - imm12b_0 = (simm12b_0 & 0xfff);
6531 +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
6532 + { { STATE_PSWOE }, 'o' },
6533 + { { STATE_PSCALLINC }, 'o' },
6534 + { { STATE_PSOWB }, 'o' },
6535 + { { STATE_PSUM }, 'o' },
6536 + { { STATE_PSEXCM }, 'o' },
6537 + { { STATE_PSINTLEVEL }, 'o' },
6538 + { { STATE_EPC1 }, 'i' },
6539 + { { STATE_EPC2 }, 'i' },
6540 + { { STATE_EPC3 }, 'i' },
6541 + { { STATE_EPC4 }, 'i' },
6542 + { { STATE_EPC5 }, 'i' },
6543 + { { STATE_EPS2 }, 'i' },
6544 + { { STATE_EPS3 }, 'i' },
6545 + { { STATE_EPS4 }, 'i' },
6546 + { { STATE_EPS5 }, 'i' },
6547 + { { STATE_InOCDMode }, 'm' }
6551 -Operand_msalp32_decode (uint32 *valp)
6553 - unsigned msalp32_0, sal_0;
6554 - sal_0 = *valp & 0x1f;
6555 - msalp32_0 = 0x20 - sal_0;
6556 - *valp = msalp32_0;
6559 +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
6560 + { { 43 /* s */ }, 'i' }
6564 -Operand_msalp32_encode (uint32 *valp)
6566 - unsigned sal_0, msalp32_0;
6567 - msalp32_0 = *valp;
6568 - sal_0 = (0x20 - msalp32_0) & 0x1f;
6572 +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
6573 + { { STATE_PSINTLEVEL }, 'o' }
6577 -Operand_op2p1_decode (uint32 *valp)
6579 - unsigned op2p1_0, op2_0;
6580 - op2_0 = *valp & 0xf;
6581 - op2p1_0 = op2_0 + 0x1;
6585 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
6586 + { { 6 /* art */ }, 'o' }
6590 -Operand_op2p1_encode (uint32 *valp)
6592 - unsigned op2_0, op2p1_0;
6594 - op2_0 = (op2p1_0 - 0x1) & 0xf;
6598 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
6599 + { { STATE_INTERRUPT }, 'i' }
6603 -Operand_label8_decode (uint32 *valp)
6605 - unsigned label8_0, imm8_0;
6606 - imm8_0 = *valp & 0xff;
6607 - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
6611 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
6612 + { { 6 /* art */ }, 'i' }
6616 -Operand_label8_encode (uint32 *valp)
6618 - unsigned imm8_0, label8_0;
6620 - imm8_0 = (label8_0 - 0x4) & 0xff;
6624 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
6625 + { { STATE_XTSYNC }, 'o' },
6626 + { { STATE_INTERRUPT }, 'm' }
6630 -Operand_label8_ator (uint32 *valp, uint32 pc)
6635 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
6636 + { { 6 /* art */ }, 'i' }
6640 -Operand_label8_rtoa (uint32 *valp, uint32 pc)
6647 -Operand_ulabel8_decode (uint32 *valp)
6649 - unsigned ulabel8_0, imm8_0;
6650 - imm8_0 = *valp & 0xff;
6651 - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
6652 - *valp = ulabel8_0;
6655 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
6656 + { { STATE_XTSYNC }, 'o' },
6657 + { { STATE_INTERRUPT }, 'm' }
6661 -Operand_ulabel8_encode (uint32 *valp)
6663 - unsigned imm8_0, ulabel8_0;
6664 - ulabel8_0 = *valp;
6665 - imm8_0 = (ulabel8_0 - 0x4) & 0xff;
6669 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
6670 + { { 6 /* art */ }, 'o' }
6674 -Operand_ulabel8_ator (uint32 *valp, uint32 pc)
6679 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
6680 + { { STATE_INTENABLE }, 'i' }
6684 -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
6689 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
6690 + { { 6 /* art */ }, 'i' }
6694 -Operand_label12_decode (uint32 *valp)
6696 - unsigned label12_0, imm12_0;
6697 - imm12_0 = *valp & 0xfff;
6698 - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
6699 - *valp = label12_0;
6702 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
6703 + { { STATE_INTENABLE }, 'o' }
6707 -Operand_label12_encode (uint32 *valp)
6709 - unsigned imm12_0, label12_0;
6710 - label12_0 = *valp;
6711 - imm12_0 = (label12_0 - 0x4) & 0xfff;
6715 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
6716 + { { 6 /* art */ }, 'm' }
6720 -Operand_label12_ator (uint32 *valp, uint32 pc)
6725 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
6726 + { { STATE_INTENABLE }, 'm' }
6730 -Operand_label12_rtoa (uint32 *valp, uint32 pc)
6735 +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
6736 + { { 34 /* imms */ }, 'i' },
6737 + { { 33 /* immt */ }, 'i' }
6741 -Operand_soffset_decode (uint32 *valp)
6743 - unsigned soffset_0, offset_0;
6744 - offset_0 = *valp & 0x3ffff;
6745 - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
6746 - *valp = soffset_0;
6749 +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
6750 + { { STATE_PSEXCM }, 'i' },
6751 + { { STATE_PSINTLEVEL }, 'i' }
6755 -Operand_soffset_encode (uint32 *valp)
6757 - unsigned offset_0, soffset_0;
6758 - soffset_0 = *valp;
6759 - offset_0 = (soffset_0 - 0x4) & 0x3ffff;
6763 +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
6764 + { { 34 /* imms */ }, 'i' }
6768 -Operand_soffset_ator (uint32 *valp, uint32 pc)
6773 +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
6774 + { { STATE_PSEXCM }, 'i' },
6775 + { { STATE_PSINTLEVEL }, 'i' }
6779 -Operand_soffset_rtoa (uint32 *valp, uint32 pc)
6784 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
6785 + { { 6 /* art */ }, 'o' }
6789 -Operand_uimm16x4_decode (uint32 *valp)
6791 - unsigned uimm16x4_0, imm16_0;
6792 - imm16_0 = *valp & 0xffff;
6793 - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
6794 - *valp = uimm16x4_0;
6797 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
6798 + { { STATE_DBREAKA0 }, 'i' }
6802 -Operand_uimm16x4_encode (uint32 *valp)
6804 - unsigned imm16_0, uimm16x4_0;
6805 - uimm16x4_0 = *valp;
6806 - imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
6810 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
6811 + { { 6 /* art */ }, 'i' }
6815 -Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
6817 - *valp -= ((pc + 3) & ~0x3);
6820 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
6821 + { { STATE_DBREAKA0 }, 'o' },
6822 + { { STATE_XTSYNC }, 'o' }
6826 -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
6828 - *valp += ((pc + 3) & ~0x3);
6831 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
6832 + { { 6 /* art */ }, 'm' }
6836 -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
6840 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
6841 + { { STATE_DBREAKA0 }, 'm' },
6842 + { { STATE_XTSYNC }, 'o' }
6846 -Operand_mx_encode (uint32 *valp)
6849 - error = (*valp & ~0x3) != 0;
6852 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
6853 + { { 6 /* art */ }, 'o' }
6857 -Operand_my_decode (uint32 *valp)
6862 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
6863 + { { STATE_DBREAKC0 }, 'i' }
6867 -Operand_my_encode (uint32 *valp)
6870 - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
6871 - *valp = *valp & 1;
6874 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
6875 + { { 6 /* art */ }, 'i' }
6879 -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
6883 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
6884 + { { STATE_DBREAKC0 }, 'o' },
6885 + { { STATE_XTSYNC }, 'o' }
6889 -Operand_mw_encode (uint32 *valp)
6892 - error = (*valp & ~0x3) != 0;
6895 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
6896 + { { 6 /* art */ }, 'm' }
6900 -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6904 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
6905 + { { STATE_DBREAKC0 }, 'm' },
6906 + { { STATE_XTSYNC }, 'o' }
6910 -Operand_mr0_encode (uint32 *valp)
6913 - error = (*valp & ~0x3) != 0;
6916 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
6917 + { { 6 /* art */ }, 'o' }
6921 -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
6925 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
6926 + { { STATE_DBREAKA1 }, 'i' }
6930 -Operand_mr1_encode (uint32 *valp)
6933 - error = (*valp & ~0x3) != 0;
6936 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
6937 + { { 6 /* art */ }, 'i' }
6941 -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
6947 -Operand_mr2_encode (uint32 *valp)
6950 - error = (*valp & ~0x3) != 0;
6953 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
6954 + { { STATE_DBREAKA1 }, 'o' },
6955 + { { STATE_XTSYNC }, 'o' }
6959 -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
6963 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
6964 + { { 6 /* art */ }, 'm' }
6968 -Operand_mr3_encode (uint32 *valp)
6971 - error = (*valp & ~0x3) != 0;
6974 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
6975 + { { STATE_DBREAKA1 }, 'm' },
6976 + { { STATE_XTSYNC }, 'o' }
6980 -Operand_immt_decode (uint32 *valp)
6982 - unsigned immt_0, t_0;
6983 - t_0 = *valp & 0xf;
6988 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
6989 + { { 6 /* art */ }, 'o' }
6993 -Operand_immt_encode (uint32 *valp)
6995 - unsigned t_0, immt_0;
6997 - t_0 = immt_0 & 0xf;
7001 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7002 + { { STATE_DBREAKC1 }, 'i' }
7006 -Operand_imms_decode (uint32 *valp)
7008 - unsigned imms_0, s_0;
7009 - s_0 = *valp & 0xf;
7014 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7015 + { { 6 /* art */ }, 'i' }
7019 -Operand_imms_encode (uint32 *valp)
7021 - unsigned s_0, imms_0;
7023 - s_0 = imms_0 & 0xf;
7027 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7028 + { { STATE_DBREAKC1 }, 'o' },
7029 + { { STATE_XTSYNC }, 'o' }
7033 -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7037 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7038 + { { 6 /* art */ }, 'm' }
7042 -Operand_bt_encode (uint32 *valp)
7045 - error = (*valp & ~0xf) != 0;
7048 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7049 + { { STATE_DBREAKC1 }, 'm' },
7050 + { { STATE_XTSYNC }, 'o' }
7054 -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7058 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7059 + { { 6 /* art */ }, 'o' }
7063 -Operand_bs_encode (uint32 *valp)
7066 - error = (*valp & ~0xf) != 0;
7069 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7070 + { { STATE_IBREAKA0 }, 'i' }
7074 -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
7078 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7079 + { { 6 /* art */ }, 'i' }
7083 -Operand_br_encode (uint32 *valp)
7086 - error = (*valp & ~0xf) != 0;
7089 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7090 + { { STATE_IBREAKA0 }, 'o' }
7094 -Operand_bt2_decode (uint32 *valp)
7096 - *valp = *valp << 1;
7099 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7100 + { { 6 /* art */ }, 'm' }
7104 -Operand_bt2_encode (uint32 *valp)
7107 - error = (*valp & ~(0x7 << 1)) != 0;
7108 - *valp = *valp >> 1;
7111 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7112 + { { STATE_IBREAKA0 }, 'm' }
7116 -Operand_bs2_decode (uint32 *valp)
7118 - *valp = *valp << 1;
7121 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7122 + { { 6 /* art */ }, 'o' }
7126 -Operand_bs2_encode (uint32 *valp)
7129 - error = (*valp & ~(0x7 << 1)) != 0;
7130 - *valp = *valp >> 1;
7133 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7134 + { { STATE_IBREAKA1 }, 'i' }
7138 -Operand_br2_decode (uint32 *valp)
7140 - *valp = *valp << 1;
7143 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7144 + { { 6 /* art */ }, 'i' }
7148 -Operand_br2_encode (uint32 *valp)
7151 - error = (*valp & ~(0x7 << 1)) != 0;
7152 - *valp = *valp >> 1;
7155 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7156 + { { STATE_IBREAKA1 }, 'o' }
7160 -Operand_bt4_decode (uint32 *valp)
7162 - *valp = *valp << 2;
7165 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7166 + { { 6 /* art */ }, 'm' }
7170 -Operand_bt4_encode (uint32 *valp)
7173 - error = (*valp & ~(0x3 << 2)) != 0;
7174 - *valp = *valp >> 2;
7177 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7178 + { { STATE_IBREAKA1 }, 'm' }
7182 -Operand_bs4_decode (uint32 *valp)
7184 - *valp = *valp << 2;
7187 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7188 + { { 6 /* art */ }, 'o' }
7192 -Operand_bs4_encode (uint32 *valp)
7195 - error = (*valp & ~(0x3 << 2)) != 0;
7196 - *valp = *valp >> 2;
7199 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7200 + { { STATE_IBREAKENABLE }, 'i' }
7204 -Operand_br4_decode (uint32 *valp)
7206 - *valp = *valp << 2;
7209 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7210 + { { 6 /* art */ }, 'i' }
7214 -Operand_br4_encode (uint32 *valp)
7217 - error = (*valp & ~(0x3 << 2)) != 0;
7218 - *valp = *valp >> 2;
7221 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7222 + { { STATE_IBREAKENABLE }, 'o' }
7226 -Operand_bt8_decode (uint32 *valp)
7228 - *valp = *valp << 3;
7231 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7232 + { { 6 /* art */ }, 'm' }
7236 -Operand_bt8_encode (uint32 *valp)
7239 - error = (*valp & ~(0x1 << 3)) != 0;
7240 - *valp = *valp >> 3;
7243 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7244 + { { STATE_IBREAKENABLE }, 'm' }
7248 -Operand_bs8_decode (uint32 *valp)
7250 - *valp = *valp << 3;
7253 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7254 + { { 6 /* art */ }, 'o' }
7258 -Operand_bs8_encode (uint32 *valp)
7261 - error = (*valp & ~(0x1 << 3)) != 0;
7262 - *valp = *valp >> 3;
7265 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7266 + { { STATE_DEBUGCAUSE }, 'i' },
7267 + { { STATE_DBNUM }, 'i' }
7271 -Operand_br8_decode (uint32 *valp)
7273 - *valp = *valp << 3;
7276 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7277 + { { 6 /* art */ }, 'i' }
7281 -Operand_br8_encode (uint32 *valp)
7284 - error = (*valp & ~(0x1 << 3)) != 0;
7285 - *valp = *valp >> 3;
7288 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7289 + { { STATE_DEBUGCAUSE }, 'o' },
7290 + { { STATE_DBNUM }, 'o' }
7294 -Operand_bt16_decode (uint32 *valp)
7296 - *valp = *valp << 4;
7299 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7300 + { { 6 /* art */ }, 'm' }
7304 -Operand_bt16_encode (uint32 *valp)
7307 - error = (*valp & ~(0 << 4)) != 0;
7308 - *valp = *valp >> 4;
7311 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7312 + { { STATE_DEBUGCAUSE }, 'm' },
7313 + { { STATE_DBNUM }, 'm' }
7317 -Operand_bs16_decode (uint32 *valp)
7319 - *valp = *valp << 4;
7322 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7323 + { { 6 /* art */ }, 'o' }
7327 -Operand_bs16_encode (uint32 *valp)
7330 - error = (*valp & ~(0 << 4)) != 0;
7331 - *valp = *valp >> 4;
7334 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7335 + { { STATE_ICOUNT }, 'i' }
7339 -Operand_br16_decode (uint32 *valp)
7341 - *valp = *valp << 4;
7344 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7345 + { { 6 /* art */ }, 'i' }
7349 -Operand_br16_encode (uint32 *valp)
7352 - error = (*valp & ~(0 << 4)) != 0;
7353 - *valp = *valp >> 4;
7356 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7357 + { { STATE_XTSYNC }, 'o' },
7358 + { { STATE_ICOUNT }, 'o' }
7362 -Operand_brall_decode (uint32 *valp)
7364 - *valp = *valp << 4;
7367 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7368 + { { 6 /* art */ }, 'm' }
7372 -Operand_brall_encode (uint32 *valp)
7375 - error = (*valp & ~(0 << 4)) != 0;
7376 - *valp = *valp >> 4;
7379 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7380 + { { STATE_XTSYNC }, 'o' },
7381 + { { STATE_ICOUNT }, 'm' }
7385 -Operand_tp7_decode (uint32 *valp)
7387 - unsigned tp7_0, t_0;
7388 - t_0 = *valp & 0xf;
7389 - tp7_0 = t_0 + 0x7;
7393 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7394 + { { 6 /* art */ }, 'o' }
7398 -Operand_tp7_encode (uint32 *valp)
7400 - unsigned t_0, tp7_0;
7402 - t_0 = (tp7_0 - 0x7) & 0xf;
7406 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7407 + { { STATE_ICOUNTLEVEL }, 'i' }
7411 -Operand_xt_wbr15_label_decode (uint32 *valp)
7413 - unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
7414 - xt_wbr15_imm_0 = *valp & 0x7fff;
7415 - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
7416 - *valp = xt_wbr15_label_0;
7419 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7420 + { { 6 /* art */ }, 'i' }
7424 -Operand_xt_wbr15_label_encode (uint32 *valp)
7426 - unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
7427 - xt_wbr15_label_0 = *valp;
7428 - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
7429 - *valp = xt_wbr15_imm_0;
7432 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7433 + { { STATE_ICOUNTLEVEL }, 'o' }
7437 -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
7442 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7443 + { { 6 /* art */ }, 'm' }
7447 -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
7452 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7453 + { { STATE_ICOUNTLEVEL }, 'm' }
7457 -Operand_xt_wbr18_label_decode (uint32 *valp)
7459 - unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
7460 - xt_wbr18_imm_0 = *valp & 0x3ffff;
7461 - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
7462 - *valp = xt_wbr18_label_0;
7465 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7466 + { { 6 /* art */ }, 'o' }
7470 -Operand_xt_wbr18_label_encode (uint32 *valp)
7472 - unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
7473 - xt_wbr18_label_0 = *valp;
7474 - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
7475 - *valp = xt_wbr18_imm_0;
7478 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7479 + { { STATE_DDR }, 'i' }
7483 -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
7488 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7489 + { { 6 /* art */ }, 'i' }
7493 -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
7498 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7499 + { { STATE_XTSYNC }, 'o' },
7500 + { { STATE_DDR }, 'o' }
7504 -Operand_cimm8x4_decode (uint32 *valp)
7506 - unsigned cimm8x4_0, imm8_0;
7507 - imm8_0 = *valp & 0xff;
7508 - cimm8x4_0 = (imm8_0 << 2) | 0;
7509 - *valp = cimm8x4_0;
7512 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7513 + { { 6 /* art */ }, 'm' }
7517 -Operand_cimm8x4_encode (uint32 *valp)
7519 - unsigned imm8_0, cimm8x4_0;
7520 - cimm8x4_0 = *valp;
7521 - imm8_0 = (cimm8x4_0 >> 2) & 0xff;
7525 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7526 + { { STATE_XTSYNC }, 'o' },
7527 + { { STATE_DDR }, 'm' }
7531 -Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
7535 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7536 + { { 34 /* imms */ }, 'i' }
7540 -Operand_frr_encode (uint32 *valp)
7543 - error = (*valp & ~0xf) != 0;
7546 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7547 + { { STATE_InOCDMode }, 'm' },
7548 + { { STATE_EPC4 }, 'i' },
7549 + { { STATE_PSWOE }, 'o' },
7550 + { { STATE_PSCALLINC }, 'o' },
7551 + { { STATE_PSOWB }, 'o' },
7552 + { { STATE_PSUM }, 'o' },
7553 + { { STATE_PSEXCM }, 'o' },
7554 + { { STATE_PSINTLEVEL }, 'o' },
7555 + { { STATE_EPS4 }, 'i' }
7559 -Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7563 +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7564 + { { STATE_InOCDMode }, 'm' }
7568 -Operand_frs_encode (uint32 *valp)
7571 - error = (*valp & ~0xf) != 0;
7574 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7575 + { { 6 /* art */ }, 'i' }
7579 -Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7583 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7584 + { { STATE_XTSYNC }, 'o' }
7588 -Operand_frt_encode (uint32 *valp)
7591 - error = (*valp & ~0xf) != 0;
7594 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7595 + { { 6 /* art */ }, 'o' }
7598 -static xtensa_operand_internal operands[] = {
7599 - { "soffsetx4", 10, -1, 0,
7600 - XTENSA_OPERAND_IS_PCRELATIVE,
7601 - Operand_soffsetx4_encode, Operand_soffsetx4_decode,
7602 - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
7603 - { "uimm12x8", 3, -1, 0,
7605 - Operand_uimm12x8_encode, Operand_uimm12x8_decode,
7607 - { "simm4", 26, -1, 0,
7609 - Operand_simm4_encode, Operand_simm4_decode,
7611 - { "arr", 14, 0, 1,
7612 - XTENSA_OPERAND_IS_REGISTER,
7613 - Operand_arr_encode, Operand_arr_decode,
7616 - XTENSA_OPERAND_IS_REGISTER,
7617 - Operand_ars_encode, Operand_ars_decode,
7619 - { "*ars_invisible", 5, 0, 1,
7620 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7621 - Operand_ars_encode, Operand_ars_decode,
7624 - XTENSA_OPERAND_IS_REGISTER,
7625 - Operand_art_encode, Operand_art_decode,
7627 - { "ar0", 123, 0, 1,
7628 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7629 - Operand_ar0_encode, Operand_ar0_decode,
7631 - { "ar4", 124, 0, 1,
7632 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7633 - Operand_ar4_encode, Operand_ar4_decode,
7635 - { "ar8", 125, 0, 1,
7636 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7637 - Operand_ar8_encode, Operand_ar8_decode,
7639 - { "ar12", 126, 0, 1,
7640 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7641 - Operand_ar12_encode, Operand_ar12_decode,
7643 - { "ars_entry", 5, 0, 1,
7644 - XTENSA_OPERAND_IS_REGISTER,
7645 - Operand_ars_entry_encode, Operand_ars_entry_decode,
7647 - { "immrx4", 14, -1, 0,
7649 - Operand_immrx4_encode, Operand_immrx4_decode,
7651 - { "lsi4x4", 14, -1, 0,
7653 - Operand_lsi4x4_encode, Operand_lsi4x4_decode,
7655 - { "simm7", 34, -1, 0,
7657 - Operand_simm7_encode, Operand_simm7_decode,
7659 - { "uimm6", 33, -1, 0,
7660 - XTENSA_OPERAND_IS_PCRELATIVE,
7661 - Operand_uimm6_encode, Operand_uimm6_decode,
7662 - Operand_uimm6_ator, Operand_uimm6_rtoa },
7663 - { "ai4const", 0, -1, 0,
7665 - Operand_ai4const_encode, Operand_ai4const_decode,
7667 - { "b4const", 14, -1, 0,
7669 - Operand_b4const_encode, Operand_b4const_decode,
7671 - { "b4constu", 14, -1, 0,
7673 - Operand_b4constu_encode, Operand_b4constu_decode,
7675 - { "uimm8", 4, -1, 0,
7677 - Operand_uimm8_encode, Operand_uimm8_decode,
7679 - { "uimm8x2", 4, -1, 0,
7681 - Operand_uimm8x2_encode, Operand_uimm8x2_decode,
7683 - { "uimm8x4", 4, -1, 0,
7685 - Operand_uimm8x4_encode, Operand_uimm8x4_decode,
7687 - { "uimm4x16", 13, -1, 0,
7689 - Operand_uimm4x16_encode, Operand_uimm4x16_decode,
7691 - { "simm8", 4, -1, 0,
7693 - Operand_simm8_encode, Operand_simm8_decode,
7695 - { "simm8x256", 4, -1, 0,
7697 - Operand_simm8x256_encode, Operand_simm8x256_decode,
7699 - { "simm12b", 6, -1, 0,
7701 - Operand_simm12b_encode, Operand_simm12b_decode,
7703 - { "msalp32", 18, -1, 0,
7705 - Operand_msalp32_encode, Operand_msalp32_decode,
7707 - { "op2p1", 13, -1, 0,
7709 - Operand_op2p1_encode, Operand_op2p1_decode,
7711 - { "label8", 4, -1, 0,
7712 - XTENSA_OPERAND_IS_PCRELATIVE,
7713 - Operand_label8_encode, Operand_label8_decode,
7714 - Operand_label8_ator, Operand_label8_rtoa },
7715 - { "ulabel8", 4, -1, 0,
7716 - XTENSA_OPERAND_IS_PCRELATIVE,
7717 - Operand_ulabel8_encode, Operand_ulabel8_decode,
7718 - Operand_ulabel8_ator, Operand_ulabel8_rtoa },
7719 - { "label12", 3, -1, 0,
7720 - XTENSA_OPERAND_IS_PCRELATIVE,
7721 - Operand_label12_encode, Operand_label12_decode,
7722 - Operand_label12_ator, Operand_label12_rtoa },
7723 - { "soffset", 10, -1, 0,
7724 - XTENSA_OPERAND_IS_PCRELATIVE,
7725 - Operand_soffset_encode, Operand_soffset_decode,
7726 - Operand_soffset_ator, Operand_soffset_rtoa },
7727 - { "uimm16x4", 7, -1, 0,
7728 - XTENSA_OPERAND_IS_PCRELATIVE,
7729 - Operand_uimm16x4_encode, Operand_uimm16x4_decode,
7730 - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
7732 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7733 - Operand_mx_encode, Operand_mx_decode,
7736 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7737 - Operand_my_encode, Operand_my_decode,
7740 - XTENSA_OPERAND_IS_REGISTER,
7741 - Operand_mw_encode, Operand_mw_decode,
7743 - { "mr0", 127, 1, 1,
7744 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7745 - Operand_mr0_encode, Operand_mr0_decode,
7747 - { "mr1", 128, 1, 1,
7748 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7749 - Operand_mr1_encode, Operand_mr1_decode,
7751 - { "mr2", 129, 1, 1,
7752 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7753 - Operand_mr2_encode, Operand_mr2_decode,
7755 - { "mr3", 130, 1, 1,
7756 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7757 - Operand_mr3_encode, Operand_mr3_decode,
7759 - { "immt", 0, -1, 0,
7761 - Operand_immt_encode, Operand_immt_decode,
7763 - { "imms", 5, -1, 0,
7765 - Operand_imms_encode, Operand_imms_decode,
7768 - XTENSA_OPERAND_IS_REGISTER,
7769 - Operand_bt_encode, Operand_bt_decode,
7772 - XTENSA_OPERAND_IS_REGISTER,
7773 - Operand_bs_encode, Operand_bs_decode,
7776 - XTENSA_OPERAND_IS_REGISTER,
7777 - Operand_br_encode, Operand_br_decode,
7779 - { "bt2", 44, 2, 2,
7780 - XTENSA_OPERAND_IS_REGISTER,
7781 - Operand_bt2_encode, Operand_bt2_decode,
7783 - { "bs2", 45, 2, 2,
7784 - XTENSA_OPERAND_IS_REGISTER,
7785 - Operand_bs2_encode, Operand_bs2_decode,
7787 - { "br2", 46, 2, 2,
7788 - XTENSA_OPERAND_IS_REGISTER,
7789 - Operand_br2_encode, Operand_br2_decode,
7791 - { "bt4", 47, 2, 4,
7792 - XTENSA_OPERAND_IS_REGISTER,
7793 - Operand_bt4_encode, Operand_bt4_decode,
7795 - { "bs4", 48, 2, 4,
7796 - XTENSA_OPERAND_IS_REGISTER,
7797 - Operand_bs4_encode, Operand_bs4_decode,
7799 - { "br4", 49, 2, 4,
7800 - XTENSA_OPERAND_IS_REGISTER,
7801 - Operand_br4_encode, Operand_br4_decode,
7803 - { "bt8", 50, 2, 8,
7804 - XTENSA_OPERAND_IS_REGISTER,
7805 - Operand_bt8_encode, Operand_bt8_decode,
7807 - { "bs8", 51, 2, 8,
7808 - XTENSA_OPERAND_IS_REGISTER,
7809 - Operand_bs8_encode, Operand_bs8_decode,
7811 - { "br8", 52, 2, 8,
7812 - XTENSA_OPERAND_IS_REGISTER,
7813 - Operand_br8_encode, Operand_br8_decode,
7815 - { "bt16", 131, 2, 16,
7816 - XTENSA_OPERAND_IS_REGISTER,
7817 - Operand_bt16_encode, Operand_bt16_decode,
7819 - { "bs16", 132, 2, 16,
7820 - XTENSA_OPERAND_IS_REGISTER,
7821 - Operand_bs16_encode, Operand_bs16_decode,
7823 - { "br16", 133, 2, 16,
7824 - XTENSA_OPERAND_IS_REGISTER,
7825 - Operand_br16_encode, Operand_br16_decode,
7827 - { "brall", 134, 2, 16,
7828 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7829 - Operand_brall_encode, Operand_brall_decode,
7831 - { "tp7", 0, -1, 0,
7833 - Operand_tp7_encode, Operand_tp7_decode,
7835 - { "xt_wbr15_label", 53, -1, 0,
7836 - XTENSA_OPERAND_IS_PCRELATIVE,
7837 - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
7838 - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
7839 - { "xt_wbr18_label", 54, -1, 0,
7840 - XTENSA_OPERAND_IS_PCRELATIVE,
7841 - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
7842 - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
7843 - { "cimm8x4", 4, -1, 0,
7845 - Operand_cimm8x4_encode, Operand_cimm8x4_decode,
7847 - { "frr", 14, 3, 1,
7848 - XTENSA_OPERAND_IS_REGISTER,
7849 - Operand_frr_encode, Operand_frr_decode,
7852 - XTENSA_OPERAND_IS_REGISTER,
7853 - Operand_frs_encode, Operand_frs_decode,
7856 - XTENSA_OPERAND_IS_REGISTER,
7857 - Operand_frt_encode, Operand_frt_decode,
7859 - { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
7860 - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
7861 - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
7862 - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
7863 - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
7864 - { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
7865 - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
7866 - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
7867 - { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
7868 - { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
7869 - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
7870 - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
7871 - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
7872 - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
7873 - { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
7874 - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
7875 - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
7876 - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
7877 - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
7878 - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
7879 - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
7880 - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
7881 - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
7882 - { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
7883 - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
7884 - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
7885 - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
7886 - { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
7887 - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
7888 - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
7889 - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
7890 - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
7891 - { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
7892 - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
7893 - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
7894 - { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
7895 - { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
7896 - { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
7897 - { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
7898 - { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
7899 - { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
7900 - { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
7901 - { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
7902 - { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
7903 - { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
7904 - { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
7905 - { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
7906 - { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
7907 - { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
7908 - { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
7909 - { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
7910 - { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
7911 - { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
7912 - { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
7913 - { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
7914 - { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
7915 - { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
7916 - { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
7917 - { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
7918 - { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
7919 - { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
7920 - { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
7921 - { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
7922 - { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
7923 - { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
7924 - { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
7925 - { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
7926 - { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
7927 - { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
7928 - { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
7929 - { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
7930 - { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
7931 - { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
7932 - { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
7933 - { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
7934 - { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
7935 - { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
7936 - { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
7937 - { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
7938 - { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
7939 - { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
7940 - { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
7941 - { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
7942 - { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
7943 - { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
7944 - { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
7945 - { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
7946 - { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
7947 - { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
7948 - { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
7949 - { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
7950 - { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
7951 - { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
7952 - { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
7953 - { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
7954 - { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
7955 - { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
7956 - { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
7957 - { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
7958 - { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
7959 - { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
7960 - { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
7961 - { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
7962 - { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
7963 - { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
7964 - { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
7965 - { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
7966 - { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
7967 - { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
7968 - { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
7969 - { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
7970 - { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
7971 - { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
7972 - { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
7973 - { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
7974 - { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
7975 - { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
7976 - { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
7977 - { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
7978 - { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
7979 - { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
7980 - { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
7981 - { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
7982 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7983 + { { STATE_CCOUNT }, 'i' }
7987 -/* Iclass table. */
7989 -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
7990 - { { STATE_PSRING }, 'i' },
7991 - { { STATE_PSEXCM }, 'm' },
7992 - { { STATE_EPC1 }, 'i' }
7993 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7994 + { { 6 /* art */ }, 'i' }
7997 -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
7998 - { { STATE_PSEXCM }, 'i' },
7999 - { { STATE_PSRING }, 'i' },
8000 - { { STATE_DEPC }, 'i' }
8001 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
8002 + { { STATE_XTSYNC }, 'o' },
8003 + { { STATE_CCOUNT }, 'o' }
8006 -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
8007 - { { 0 /* soffsetx4 */ }, 'i' },
8008 - { { 10 /* ar12 */ }, 'o' }
8009 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
8010 + { { 6 /* art */ }, 'm' }
8013 -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
8014 - { { STATE_PSCALLINC }, 'o' }
8015 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
8016 + { { STATE_XTSYNC }, 'o' },
8017 + { { STATE_CCOUNT }, 'm' }
8020 -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
8021 - { { 0 /* soffsetx4 */ }, 'i' },
8022 - { { 9 /* ar8 */ }, 'o' }
8025 -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
8026 - { { STATE_PSCALLINC }, 'o' }
8029 -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
8030 - { { 0 /* soffsetx4 */ }, 'i' },
8031 - { { 8 /* ar4 */ }, 'o' }
8034 -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
8035 - { { STATE_PSCALLINC }, 'o' }
8038 -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
8039 - { { 4 /* ars */ }, 'i' },
8040 - { { 10 /* ar12 */ }, 'o' }
8041 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
8042 + { { 6 /* art */ }, 'o' }
8045 -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
8046 - { { STATE_PSCALLINC }, 'o' }
8047 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
8048 + { { STATE_CCOMPARE0 }, 'i' }
8051 -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
8052 - { { 4 /* ars */ }, 'i' },
8053 - { { 9 /* ar8 */ }, 'o' }
8054 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
8055 + { { 6 /* art */ }, 'i' }
8058 -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
8059 - { { STATE_PSCALLINC }, 'o' }
8060 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
8061 + { { STATE_CCOMPARE0 }, 'o' },
8062 + { { STATE_INTERRUPT }, 'm' }
8065 -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
8066 - { { 4 /* ars */ }, 'i' },
8067 - { { 8 /* ar4 */ }, 'o' }
8068 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
8069 + { { 6 /* art */ }, 'm' }
8072 -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
8073 - { { STATE_PSCALLINC }, 'o' }
8074 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
8075 + { { STATE_CCOMPARE0 }, 'm' },
8076 + { { STATE_INTERRUPT }, 'm' }
8079 -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
8080 - { { 11 /* ars_entry */ }, 's' },
8081 - { { 4 /* ars */ }, 'i' },
8082 - { { 1 /* uimm12x8 */ }, 'i' }
8083 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8084 + { { 4 /* ars */ }, 'i' }
8087 -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
8088 - { { STATE_PSCALLINC }, 'i' },
8089 - { { STATE_PSEXCM }, 'i' },
8090 - { { STATE_PSWOE }, 'i' },
8091 - { { STATE_WindowBase }, 'm' },
8092 - { { STATE_WindowStart }, 'm' }
8093 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8094 + { { STATE_XTSYNC }, 'o' }
8097 -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
8098 +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8099 { { 6 /* art */ }, 'o' },
8100 { { 4 /* ars */ }, 'i' }
8103 -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
8104 - { { STATE_WindowBase }, 'i' },
8105 - { { STATE_WindowStart }, 'i' }
8108 -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
8109 - { { 2 /* simm4 */ }, 'i' }
8112 -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
8113 - { { STATE_PSEXCM }, 'i' },
8114 - { { STATE_PSRING }, 'i' },
8115 - { { STATE_WindowBase }, 'm' }
8118 -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
8119 - { { 5 /* *ars_invisible */ }, 'i' }
8120 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8121 + { { 6 /* art */ }, 'i' },
8122 + { { 4 /* ars */ }, 'i' }
8125 -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
8126 - { { STATE_WindowBase }, 'm' },
8127 - { { STATE_WindowStart }, 'm' },
8128 - { { STATE_PSEXCM }, 'i' },
8129 - { { STATE_PSWOE }, 'i' }
8130 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8131 + { { STATE_XTSYNC }, 'o' }
8134 -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
8135 - { { STATE_EPC1 }, 'i' },
8136 - { { STATE_PSEXCM }, 'm' },
8137 - { { STATE_PSRING }, 'i' },
8138 - { { STATE_WindowBase }, 'm' },
8139 - { { STATE_WindowStart }, 'm' },
8140 - { { STATE_PSOWB }, 'i' }
8141 +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8142 + { { 4 /* ars */ }, 'i' }
8145 -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
8146 +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8147 { { 6 /* art */ }, 'o' },
8148 - { { 4 /* ars */ }, 'i' },
8149 - { { 12 /* immrx4 */ }, 'i' }
8152 -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
8153 - { { STATE_PSEXCM }, 'i' },
8154 - { { STATE_PSRING }, 'i' }
8155 + { { 4 /* ars */ }, 'i' }
8158 -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
8159 +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8160 { { 6 /* art */ }, 'i' },
8161 - { { 4 /* ars */ }, 'i' },
8162 - { { 12 /* immrx4 */ }, 'i' }
8165 -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
8166 - { { STATE_PSEXCM }, 'i' },
8167 - { { STATE_PSRING }, 'i' }
8170 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
8171 - { { 6 /* art */ }, 'o' }
8174 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
8175 - { { STATE_PSEXCM }, 'i' },
8176 - { { STATE_PSRING }, 'i' },
8177 - { { STATE_WindowBase }, 'i' }
8180 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
8181 - { { 6 /* art */ }, 'i' }
8184 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
8185 - { { STATE_PSEXCM }, 'i' },
8186 - { { STATE_PSRING }, 'i' },
8187 - { { STATE_WindowBase }, 'o' }
8190 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
8191 - { { 6 /* art */ }, 'm' }
8194 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
8195 - { { STATE_PSEXCM }, 'i' },
8196 - { { STATE_PSRING }, 'i' },
8197 - { { STATE_WindowBase }, 'm' }
8200 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
8201 - { { 6 /* art */ }, 'o' }
8204 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
8205 - { { STATE_PSEXCM }, 'i' },
8206 - { { STATE_PSRING }, 'i' },
8207 - { { STATE_WindowStart }, 'i' }
8210 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
8211 - { { 6 /* art */ }, 'i' }
8214 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
8215 - { { STATE_PSEXCM }, 'i' },
8216 - { { STATE_PSRING }, 'i' },
8217 - { { STATE_WindowStart }, 'o' }
8220 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
8221 - { { 6 /* art */ }, 'm' }
8224 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
8225 - { { STATE_PSEXCM }, 'i' },
8226 - { { STATE_PSRING }, 'i' },
8227 - { { STATE_WindowStart }, 'm' }
8228 + { { 4 /* ars */ }, 'i' }
8231 -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
8232 +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8233 { { 3 /* arr */ }, 'o' },
8234 { { 4 /* ars */ }, 'i' },
8235 { { 6 /* art */ }, 'i' }
8238 -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
8239 - { { 3 /* arr */ }, 'o' },
8240 - { { 4 /* ars */ }, 'i' },
8241 - { { 16 /* ai4const */ }, 'i' }
8242 +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8243 + { { 6 /* art */ }, 'o' },
8244 + { { 4 /* ars */ }, 'i' }
8247 -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
8248 +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8249 + { { 3 /* arr */ }, 'o' },
8250 { { 4 /* ars */ }, 'i' },
8251 - { { 15 /* uimm6 */ }, 'i' }
8252 + { { 35 /* tp7 */ }, 'i' }
8255 -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
8256 +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8257 { { 6 /* art */ }, 'o' },
8258 { { 4 /* ars */ }, 'i' },
8259 - { { 13 /* lsi4x4 */ }, 'i' }
8262 -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
8263 - { { 6 /* art */ }, 'o' },
8264 - { { 4 /* ars */ }, 'i' }
8267 -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
8268 - { { 4 /* ars */ }, 'o' },
8269 - { { 14 /* simm7 */ }, 'i' }
8270 + { { 21 /* uimm8x4 */ }, 'i' }
8273 -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
8274 - { { 5 /* *ars_invisible */ }, 'i' }
8275 +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8276 + { { 6 /* art */ }, 'i' },
8277 + { { 4 /* ars */ }, 'i' },
8278 + { { 21 /* uimm8x4 */ }, 'i' }
8281 -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
8282 - { { 6 /* art */ }, 'i' },
8283 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8284 + { { 6 /* art */ }, 'm' },
8285 { { 4 /* ars */ }, 'i' },
8286 - { { 13 /* lsi4x4 */ }, 'i' }
8287 + { { 21 /* uimm8x4 */ }, 'i' }
8290 -static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
8291 - { { 3 /* arr */ }, 'o' }
8292 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8293 + { { STATE_SCOMPARE1 }, 'i' },
8294 + { { STATE_SCOMPARE1 }, 'i' }
8297 -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
8298 - { { STATE_THREADPTR }, 'i' }
8299 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8300 + { { 6 /* art */ }, 'o' }
8303 -static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
8304 - { { 6 /* art */ }, 'i' }
8305 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8306 + { { STATE_SCOMPARE1 }, 'i' }
8309 -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
8310 - { { STATE_THREADPTR }, 'o' }
8311 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8312 + { { 6 /* art */ }, 'i' }
8315 -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
8316 - { { 6 /* art */ }, 'o' },
8317 - { { 4 /* ars */ }, 'i' },
8318 - { { 23 /* simm8 */ }, 'i' }
8319 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8320 + { { STATE_SCOMPARE1 }, 'o' }
8323 -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
8324 - { { 6 /* art */ }, 'o' },
8325 - { { 4 /* ars */ }, 'i' },
8326 - { { 24 /* simm8x256 */ }, 'i' }
8327 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8328 + { { 6 /* art */ }, 'm' }
8331 -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
8332 - { { 3 /* arr */ }, 'o' },
8333 - { { 4 /* ars */ }, 'i' },
8334 - { { 6 /* art */ }, 'i' }
8335 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8336 + { { STATE_SCOMPARE1 }, 'm' }
8339 -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
8340 +static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8341 { { 3 /* arr */ }, 'o' },
8342 { { 4 /* ars */ }, 'i' },
8343 { { 6 /* art */ }, 'i' }
8346 -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
8347 - { { 4 /* ars */ }, 'i' },
8348 - { { 17 /* b4const */ }, 'i' },
8349 - { { 28 /* label8 */ }, 'i' }
8352 -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
8353 - { { 4 /* ars */ }, 'i' },
8354 - { { 67 /* bbi */ }, 'i' },
8355 - { { 28 /* label8 */ }, 'i' }
8358 -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
8359 - { { 4 /* ars */ }, 'i' },
8360 - { { 18 /* b4constu */ }, 'i' },
8361 - { { 28 /* label8 */ }, 'i' }
8364 -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
8365 - { { 4 /* ars */ }, 'i' },
8366 - { { 6 /* art */ }, 'i' },
8367 - { { 28 /* label8 */ }, 'i' }
8370 -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
8371 - { { 4 /* ars */ }, 'i' },
8372 - { { 30 /* label12 */ }, 'i' }
8375 -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
8376 - { { 0 /* soffsetx4 */ }, 'i' },
8377 - { { 7 /* ar0 */ }, 'o' }
8380 -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
8381 - { { 4 /* ars */ }, 'i' },
8382 - { { 7 /* ar0 */ }, 'o' }
8385 -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
8386 - { { 3 /* arr */ }, 'o' },
8387 - { { 6 /* art */ }, 'i' },
8388 - { { 82 /* sae */ }, 'i' },
8389 - { { 27 /* op2p1 */ }, 'i' }
8392 -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
8393 - { { 31 /* soffset */ }, 'i' }
8396 -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
8397 - { { 4 /* ars */ }, 'i' }
8400 -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
8401 - { { 6 /* art */ }, 'o' },
8402 - { { 4 /* ars */ }, 'i' },
8403 - { { 20 /* uimm8x2 */ }, 'i' }
8406 -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
8407 - { { 6 /* art */ }, 'o' },
8408 - { { 4 /* ars */ }, 'i' },
8409 - { { 20 /* uimm8x2 */ }, 'i' }
8412 -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
8413 - { { 6 /* art */ }, 'o' },
8414 - { { 4 /* ars */ }, 'i' },
8415 - { { 21 /* uimm8x4 */ }, 'i' }
8418 -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
8419 - { { 6 /* art */ }, 'o' },
8420 - { { 32 /* uimm16x4 */ }, 'i' }
8423 -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
8424 - { { STATE_LITBADDR }, 'i' },
8425 - { { STATE_LITBEN }, 'i' }
8428 -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
8429 - { { 6 /* art */ }, 'o' },
8430 - { { 4 /* ars */ }, 'i' },
8431 - { { 19 /* uimm8 */ }, 'i' }
8434 -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
8435 - { { 4 /* ars */ }, 'i' },
8436 - { { 29 /* ulabel8 */ }, 'i' }
8439 -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
8440 - { { STATE_LBEG }, 'o' },
8441 - { { STATE_LEND }, 'o' },
8442 - { { STATE_LCOUNT }, 'o' }
8445 -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
8446 - { { 4 /* ars */ }, 'i' },
8447 - { { 29 /* ulabel8 */ }, 'i' }
8450 -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
8451 - { { STATE_LBEG }, 'o' },
8452 - { { STATE_LEND }, 'o' },
8453 - { { STATE_LCOUNT }, 'o' }
8456 -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
8457 - { { 6 /* art */ }, 'o' },
8458 - { { 25 /* simm12b */ }, 'i' }
8461 -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
8462 - { { 3 /* arr */ }, 'm' },
8463 - { { 4 /* ars */ }, 'i' },
8464 - { { 6 /* art */ }, 'i' }
8467 -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
8468 - { { 3 /* arr */ }, 'o' },
8469 - { { 6 /* art */ }, 'i' }
8472 -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
8473 - { { 5 /* *ars_invisible */ }, 'i' }
8476 -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
8477 - { { 6 /* art */ }, 'i' },
8478 - { { 4 /* ars */ }, 'i' },
8479 - { { 20 /* uimm8x2 */ }, 'i' }
8482 -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
8483 - { { 6 /* art */ }, 'i' },
8484 - { { 4 /* ars */ }, 'i' },
8485 - { { 21 /* uimm8x4 */ }, 'i' }
8488 -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
8489 - { { 6 /* art */ }, 'i' },
8490 - { { 4 /* ars */ }, 'i' },
8491 - { { 19 /* uimm8 */ }, 'i' }
8494 -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
8495 - { { 4 /* ars */ }, 'i' }
8498 -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
8499 - { { STATE_SAR }, 'o' }
8502 -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
8503 - { { 86 /* sas */ }, 'i' }
8506 -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
8507 - { { STATE_SAR }, 'o' }
8510 -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
8511 - { { 3 /* arr */ }, 'o' },
8512 - { { 4 /* ars */ }, 'i' }
8515 -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
8516 - { { STATE_SAR }, 'i' }
8519 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
8520 - { { 3 /* arr */ }, 'o' },
8521 - { { 4 /* ars */ }, 'i' },
8522 - { { 6 /* art */ }, 'i' }
8525 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
8526 - { { STATE_SAR }, 'i' }
8529 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
8530 - { { 3 /* arr */ }, 'o' },
8531 - { { 6 /* art */ }, 'i' }
8534 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
8535 - { { STATE_SAR }, 'i' }
8538 -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
8539 - { { 3 /* arr */ }, 'o' },
8540 - { { 4 /* ars */ }, 'i' },
8541 - { { 26 /* msalp32 */ }, 'i' }
8544 -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
8545 - { { 3 /* arr */ }, 'o' },
8546 - { { 6 /* art */ }, 'i' },
8547 - { { 84 /* sargt */ }, 'i' }
8550 -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
8551 - { { 3 /* arr */ }, 'o' },
8552 - { { 6 /* art */ }, 'i' },
8553 - { { 70 /* s */ }, 'i' }
8556 -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
8557 - { { STATE_XTSYNC }, 'i' }
8560 -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
8561 - { { 6 /* art */ }, 'o' },
8562 - { { 70 /* s */ }, 'i' }
8565 -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
8566 - { { STATE_PSWOE }, 'i' },
8567 - { { STATE_PSCALLINC }, 'i' },
8568 - { { STATE_PSOWB }, 'i' },
8569 - { { STATE_PSRING }, 'i' },
8570 - { { STATE_PSUM }, 'i' },
8571 - { { STATE_PSEXCM }, 'i' },
8572 - { { STATE_PSINTLEVEL }, 'm' }
8575 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
8576 - { { 6 /* art */ }, 'o' }
8579 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
8580 - { { STATE_LEND }, 'i' }
8583 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
8584 - { { 6 /* art */ }, 'i' }
8587 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
8588 - { { STATE_LEND }, 'o' }
8591 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
8592 - { { 6 /* art */ }, 'm' }
8595 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
8596 - { { STATE_LEND }, 'm' }
8599 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
8600 - { { 6 /* art */ }, 'o' }
8603 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
8604 - { { STATE_LCOUNT }, 'i' }
8607 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
8608 - { { 6 /* art */ }, 'i' }
8611 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
8612 - { { STATE_XTSYNC }, 'o' },
8613 - { { STATE_LCOUNT }, 'o' }
8616 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
8617 - { { 6 /* art */ }, 'm' }
8620 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
8621 - { { STATE_XTSYNC }, 'o' },
8622 - { { STATE_LCOUNT }, 'm' }
8625 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
8626 - { { 6 /* art */ }, 'o' }
8629 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
8630 - { { STATE_LBEG }, 'i' }
8633 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
8634 - { { 6 /* art */ }, 'i' }
8637 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
8638 - { { STATE_LBEG }, 'o' }
8641 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
8642 - { { 6 /* art */ }, 'm' }
8645 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
8646 - { { STATE_LBEG }, 'm' }
8649 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
8650 - { { 6 /* art */ }, 'o' }
8653 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
8654 - { { STATE_SAR }, 'i' }
8657 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
8658 - { { 6 /* art */ }, 'i' }
8661 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
8662 - { { STATE_SAR }, 'o' },
8663 - { { STATE_XTSYNC }, 'o' }
8666 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
8667 - { { 6 /* art */ }, 'm' }
8670 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
8671 - { { STATE_SAR }, 'm' }
8674 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
8675 - { { 6 /* art */ }, 'o' }
8678 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
8679 - { { STATE_LITBADDR }, 'i' },
8680 - { { STATE_LITBEN }, 'i' }
8683 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
8684 - { { 6 /* art */ }, 'i' }
8687 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
8688 - { { STATE_LITBADDR }, 'o' },
8689 - { { STATE_LITBEN }, 'o' }
8692 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
8693 - { { 6 /* art */ }, 'm' }
8696 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
8697 - { { STATE_LITBADDR }, 'm' },
8698 - { { STATE_LITBEN }, 'm' }
8701 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
8702 - { { 6 /* art */ }, 'o' }
8705 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
8706 - { { STATE_PSEXCM }, 'i' },
8707 - { { STATE_PSRING }, 'i' }
8710 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
8711 - { { 6 /* art */ }, 'o' }
8714 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
8715 - { { STATE_PSEXCM }, 'i' },
8716 - { { STATE_PSRING }, 'i' }
8719 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
8720 - { { 6 /* art */ }, 'o' }
8723 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
8724 - { { STATE_PSWOE }, 'i' },
8725 - { { STATE_PSCALLINC }, 'i' },
8726 - { { STATE_PSOWB }, 'i' },
8727 - { { STATE_PSRING }, 'i' },
8728 - { { STATE_PSUM }, 'i' },
8729 - { { STATE_PSEXCM }, 'i' },
8730 - { { STATE_PSINTLEVEL }, 'i' }
8733 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
8734 - { { 6 /* art */ }, 'i' }
8737 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
8738 - { { STATE_PSWOE }, 'o' },
8739 - { { STATE_PSCALLINC }, 'o' },
8740 - { { STATE_PSOWB }, 'o' },
8741 - { { STATE_PSRING }, 'm' },
8742 - { { STATE_PSUM }, 'o' },
8743 - { { STATE_PSEXCM }, 'm' },
8744 - { { STATE_PSINTLEVEL }, 'o' }
8747 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
8748 - { { 6 /* art */ }, 'm' }
8751 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
8752 - { { STATE_PSWOE }, 'm' },
8753 - { { STATE_PSCALLINC }, 'm' },
8754 - { { STATE_PSOWB }, 'm' },
8755 - { { STATE_PSRING }, 'm' },
8756 - { { STATE_PSUM }, 'm' },
8757 - { { STATE_PSEXCM }, 'm' },
8758 - { { STATE_PSINTLEVEL }, 'm' }
8761 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
8762 - { { 6 /* art */ }, 'o' }
8765 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
8766 - { { STATE_PSEXCM }, 'i' },
8767 - { { STATE_PSRING }, 'i' },
8768 - { { STATE_EPC1 }, 'i' }
8771 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
8772 - { { 6 /* art */ }, 'i' }
8775 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
8776 - { { STATE_PSEXCM }, 'i' },
8777 - { { STATE_PSRING }, 'i' },
8778 - { { STATE_EPC1 }, 'o' }
8781 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
8782 - { { 6 /* art */ }, 'm' }
8785 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
8786 - { { STATE_PSEXCM }, 'i' },
8787 - { { STATE_PSRING }, 'i' },
8788 - { { STATE_EPC1 }, 'm' }
8791 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
8792 - { { 6 /* art */ }, 'o' }
8795 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
8796 - { { STATE_PSEXCM }, 'i' },
8797 - { { STATE_PSRING }, 'i' },
8798 - { { STATE_EXCSAVE1 }, 'i' }
8801 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
8802 - { { 6 /* art */ }, 'i' }
8805 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
8806 - { { STATE_PSEXCM }, 'i' },
8807 - { { STATE_PSRING }, 'i' },
8808 - { { STATE_EXCSAVE1 }, 'o' }
8811 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
8812 - { { 6 /* art */ }, 'm' }
8815 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
8816 - { { STATE_PSEXCM }, 'i' },
8817 - { { STATE_PSRING }, 'i' },
8818 - { { STATE_EXCSAVE1 }, 'm' }
8821 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
8822 - { { 6 /* art */ }, 'o' }
8825 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
8826 - { { STATE_PSEXCM }, 'i' },
8827 - { { STATE_PSRING }, 'i' },
8828 - { { STATE_EPC2 }, 'i' }
8831 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
8832 - { { 6 /* art */ }, 'i' }
8835 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
8836 - { { STATE_PSEXCM }, 'i' },
8837 - { { STATE_PSRING }, 'i' },
8838 - { { STATE_EPC2 }, 'o' }
8841 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
8842 - { { 6 /* art */ }, 'm' }
8845 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
8846 - { { STATE_PSEXCM }, 'i' },
8847 - { { STATE_PSRING }, 'i' },
8848 - { { STATE_EPC2 }, 'm' }
8851 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
8852 - { { 6 /* art */ }, 'o' }
8855 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
8856 - { { STATE_PSEXCM }, 'i' },
8857 - { { STATE_PSRING }, 'i' },
8858 - { { STATE_EXCSAVE2 }, 'i' }
8861 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
8862 - { { 6 /* art */ }, 'i' }
8865 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
8866 - { { STATE_PSEXCM }, 'i' },
8867 - { { STATE_PSRING }, 'i' },
8868 - { { STATE_EXCSAVE2 }, 'o' }
8871 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
8872 - { { 6 /* art */ }, 'm' }
8875 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
8876 - { { STATE_PSEXCM }, 'i' },
8877 - { { STATE_PSRING }, 'i' },
8878 - { { STATE_EXCSAVE2 }, 'm' }
8881 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
8882 - { { 6 /* art */ }, 'o' }
8885 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
8886 - { { STATE_PSEXCM }, 'i' },
8887 - { { STATE_PSRING }, 'i' },
8888 - { { STATE_EPC3 }, 'i' }
8891 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
8892 - { { 6 /* art */ }, 'i' }
8895 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
8896 - { { STATE_PSEXCM }, 'i' },
8897 - { { STATE_PSRING }, 'i' },
8898 - { { STATE_EPC3 }, 'o' }
8901 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
8902 - { { 6 /* art */ }, 'm' }
8905 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
8906 - { { STATE_PSEXCM }, 'i' },
8907 - { { STATE_PSRING }, 'i' },
8908 - { { STATE_EPC3 }, 'm' }
8911 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
8912 - { { 6 /* art */ }, 'o' }
8915 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
8916 - { { STATE_PSEXCM }, 'i' },
8917 - { { STATE_PSRING }, 'i' },
8918 - { { STATE_EXCSAVE3 }, 'i' }
8921 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
8922 - { { 6 /* art */ }, 'i' }
8925 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
8926 - { { STATE_PSEXCM }, 'i' },
8927 - { { STATE_PSRING }, 'i' },
8928 - { { STATE_EXCSAVE3 }, 'o' }
8931 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
8932 - { { 6 /* art */ }, 'm' }
8935 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
8936 - { { STATE_PSEXCM }, 'i' },
8937 - { { STATE_PSRING }, 'i' },
8938 - { { STATE_EXCSAVE3 }, 'm' }
8941 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
8942 - { { 6 /* art */ }, 'o' }
8945 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
8946 - { { STATE_PSEXCM }, 'i' },
8947 - { { STATE_PSRING }, 'i' },
8948 - { { STATE_EPC4 }, 'i' }
8951 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
8952 - { { 6 /* art */ }, 'i' }
8955 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
8956 - { { STATE_PSEXCM }, 'i' },
8957 - { { STATE_PSRING }, 'i' },
8958 - { { STATE_EPC4 }, 'o' }
8961 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
8962 - { { 6 /* art */ }, 'm' }
8965 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
8966 - { { STATE_PSEXCM }, 'i' },
8967 - { { STATE_PSRING }, 'i' },
8968 - { { STATE_EPC4 }, 'm' }
8971 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
8972 - { { 6 /* art */ }, 'o' }
8975 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
8976 - { { STATE_PSEXCM }, 'i' },
8977 - { { STATE_PSRING }, 'i' },
8978 - { { STATE_EXCSAVE4 }, 'i' }
8981 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
8982 - { { 6 /* art */ }, 'i' }
8985 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
8986 - { { STATE_PSEXCM }, 'i' },
8987 - { { STATE_PSRING }, 'i' },
8988 - { { STATE_EXCSAVE4 }, 'o' }
8991 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
8992 - { { 6 /* art */ }, 'm' }
8995 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
8996 - { { STATE_PSEXCM }, 'i' },
8997 - { { STATE_PSRING }, 'i' },
8998 - { { STATE_EXCSAVE4 }, 'm' }
9001 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
9002 - { { 6 /* art */ }, 'o' }
9005 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
9006 - { { STATE_PSEXCM }, 'i' },
9007 - { { STATE_PSRING }, 'i' },
9008 - { { STATE_EPC5 }, 'i' }
9011 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
9012 - { { 6 /* art */ }, 'i' }
9015 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
9016 - { { STATE_PSEXCM }, 'i' },
9017 - { { STATE_PSRING }, 'i' },
9018 - { { STATE_EPC5 }, 'o' }
9021 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
9022 - { { 6 /* art */ }, 'm' }
9025 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
9026 - { { STATE_PSEXCM }, 'i' },
9027 - { { STATE_PSRING }, 'i' },
9028 - { { STATE_EPC5 }, 'm' }
9031 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
9032 - { { 6 /* art */ }, 'o' }
9035 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
9036 - { { STATE_PSEXCM }, 'i' },
9037 - { { STATE_PSRING }, 'i' },
9038 - { { STATE_EXCSAVE5 }, 'i' }
9041 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
9042 - { { 6 /* art */ }, 'i' }
9045 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
9046 - { { STATE_PSEXCM }, 'i' },
9047 - { { STATE_PSRING }, 'i' },
9048 - { { STATE_EXCSAVE5 }, 'o' }
9051 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
9052 - { { 6 /* art */ }, 'm' }
9055 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
9056 - { { STATE_PSEXCM }, 'i' },
9057 - { { STATE_PSRING }, 'i' },
9058 - { { STATE_EXCSAVE5 }, 'm' }
9061 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
9062 - { { 6 /* art */ }, 'o' }
9065 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
9066 - { { STATE_PSEXCM }, 'i' },
9067 - { { STATE_PSRING }, 'i' },
9068 - { { STATE_EPC6 }, 'i' }
9071 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
9072 - { { 6 /* art */ }, 'i' }
9075 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
9076 - { { STATE_PSEXCM }, 'i' },
9077 - { { STATE_PSRING }, 'i' },
9078 - { { STATE_EPC6 }, 'o' }
9081 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
9082 - { { 6 /* art */ }, 'm' }
9085 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
9086 - { { STATE_PSEXCM }, 'i' },
9087 - { { STATE_PSRING }, 'i' },
9088 - { { STATE_EPC6 }, 'm' }
9091 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
9092 - { { 6 /* art */ }, 'o' }
9095 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
9096 - { { STATE_PSEXCM }, 'i' },
9097 - { { STATE_PSRING }, 'i' },
9098 - { { STATE_EXCSAVE6 }, 'i' }
9101 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
9102 - { { 6 /* art */ }, 'i' }
9105 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
9106 - { { STATE_PSEXCM }, 'i' },
9107 - { { STATE_PSRING }, 'i' },
9108 - { { STATE_EXCSAVE6 }, 'o' }
9111 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
9112 - { { 6 /* art */ }, 'm' }
9115 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
9116 - { { STATE_PSEXCM }, 'i' },
9117 - { { STATE_PSRING }, 'i' },
9118 - { { STATE_EXCSAVE6 }, 'm' }
9121 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
9122 - { { 6 /* art */ }, 'o' }
9125 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
9126 - { { STATE_PSEXCM }, 'i' },
9127 - { { STATE_PSRING }, 'i' },
9128 - { { STATE_EPC7 }, 'i' }
9131 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
9132 - { { 6 /* art */ }, 'i' }
9135 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
9136 - { { STATE_PSEXCM }, 'i' },
9137 - { { STATE_PSRING }, 'i' },
9138 - { { STATE_EPC7 }, 'o' }
9141 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
9142 - { { 6 /* art */ }, 'm' }
9145 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
9146 - { { STATE_PSEXCM }, 'i' },
9147 - { { STATE_PSRING }, 'i' },
9148 - { { STATE_EPC7 }, 'm' }
9151 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
9152 - { { 6 /* art */ }, 'o' }
9155 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
9156 - { { STATE_PSEXCM }, 'i' },
9157 - { { STATE_PSRING }, 'i' },
9158 - { { STATE_EXCSAVE7 }, 'i' }
9161 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
9162 - { { 6 /* art */ }, 'i' }
9165 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
9166 - { { STATE_PSEXCM }, 'i' },
9167 - { { STATE_PSRING }, 'i' },
9168 - { { STATE_EXCSAVE7 }, 'o' }
9171 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
9172 - { { 6 /* art */ }, 'm' }
9175 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
9176 - { { STATE_PSEXCM }, 'i' },
9177 - { { STATE_PSRING }, 'i' },
9178 - { { STATE_EXCSAVE7 }, 'm' }
9181 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
9182 - { { 6 /* art */ }, 'o' }
9185 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
9186 - { { STATE_PSEXCM }, 'i' },
9187 - { { STATE_PSRING }, 'i' },
9188 - { { STATE_EPS2 }, 'i' }
9191 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
9192 - { { 6 /* art */ }, 'i' }
9195 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
9196 - { { STATE_PSEXCM }, 'i' },
9197 - { { STATE_PSRING }, 'i' },
9198 - { { STATE_EPS2 }, 'o' }
9201 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
9202 - { { 6 /* art */ }, 'm' }
9205 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
9206 - { { STATE_PSEXCM }, 'i' },
9207 - { { STATE_PSRING }, 'i' },
9208 - { { STATE_EPS2 }, 'm' }
9211 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
9212 - { { 6 /* art */ }, 'o' }
9215 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
9216 - { { STATE_PSEXCM }, 'i' },
9217 - { { STATE_PSRING }, 'i' },
9218 - { { STATE_EPS3 }, 'i' }
9221 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
9222 - { { 6 /* art */ }, 'i' }
9225 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
9226 - { { STATE_PSEXCM }, 'i' },
9227 - { { STATE_PSRING }, 'i' },
9228 - { { STATE_EPS3 }, 'o' }
9231 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
9232 - { { 6 /* art */ }, 'm' }
9235 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
9236 - { { STATE_PSEXCM }, 'i' },
9237 - { { STATE_PSRING }, 'i' },
9238 - { { STATE_EPS3 }, 'm' }
9241 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
9242 - { { 6 /* art */ }, 'o' }
9245 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
9246 - { { STATE_PSEXCM }, 'i' },
9247 - { { STATE_PSRING }, 'i' },
9248 - { { STATE_EPS4 }, 'i' }
9251 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
9252 - { { 6 /* art */ }, 'i' }
9255 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
9256 - { { STATE_PSEXCM }, 'i' },
9257 - { { STATE_PSRING }, 'i' },
9258 - { { STATE_EPS4 }, 'o' }
9261 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
9262 - { { 6 /* art */ }, 'm' }
9265 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
9266 - { { STATE_PSEXCM }, 'i' },
9267 - { { STATE_PSRING }, 'i' },
9268 - { { STATE_EPS4 }, 'm' }
9271 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
9272 - { { 6 /* art */ }, 'o' }
9275 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
9276 - { { STATE_PSEXCM }, 'i' },
9277 - { { STATE_PSRING }, 'i' },
9278 - { { STATE_EPS5 }, 'i' }
9281 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
9282 - { { 6 /* art */ }, 'i' }
9285 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
9286 - { { STATE_PSEXCM }, 'i' },
9287 - { { STATE_PSRING }, 'i' },
9288 - { { STATE_EPS5 }, 'o' }
9291 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
9292 - { { 6 /* art */ }, 'm' }
9295 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
9296 - { { STATE_PSEXCM }, 'i' },
9297 - { { STATE_PSRING }, 'i' },
9298 - { { STATE_EPS5 }, 'm' }
9301 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
9302 - { { 6 /* art */ }, 'o' }
9305 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
9306 - { { STATE_PSEXCM }, 'i' },
9307 - { { STATE_PSRING }, 'i' },
9308 - { { STATE_EPS6 }, 'i' }
9311 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
9312 - { { 6 /* art */ }, 'i' }
9315 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
9316 - { { STATE_PSEXCM }, 'i' },
9317 - { { STATE_PSRING }, 'i' },
9318 - { { STATE_EPS6 }, 'o' }
9321 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
9322 - { { 6 /* art */ }, 'm' }
9325 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
9326 - { { STATE_PSEXCM }, 'i' },
9327 - { { STATE_PSRING }, 'i' },
9328 - { { STATE_EPS6 }, 'm' }
9331 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
9332 - { { 6 /* art */ }, 'o' }
9335 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
9336 - { { STATE_PSEXCM }, 'i' },
9337 - { { STATE_PSRING }, 'i' },
9338 - { { STATE_EPS7 }, 'i' }
9341 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
9342 - { { 6 /* art */ }, 'i' }
9345 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
9346 - { { STATE_PSEXCM }, 'i' },
9347 - { { STATE_PSRING }, 'i' },
9348 - { { STATE_EPS7 }, 'o' }
9351 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
9352 - { { 6 /* art */ }, 'm' }
9355 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
9356 - { { STATE_PSEXCM }, 'i' },
9357 - { { STATE_PSRING }, 'i' },
9358 - { { STATE_EPS7 }, 'm' }
9361 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
9362 - { { 6 /* art */ }, 'o' }
9365 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
9366 - { { STATE_PSEXCM }, 'i' },
9367 - { { STATE_PSRING }, 'i' },
9368 - { { STATE_EXCVADDR }, 'i' }
9371 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
9372 - { { 6 /* art */ }, 'i' }
9375 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
9376 - { { STATE_PSEXCM }, 'i' },
9377 - { { STATE_PSRING }, 'i' },
9378 - { { STATE_EXCVADDR }, 'o' }
9381 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
9382 - { { 6 /* art */ }, 'm' }
9385 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
9386 - { { STATE_PSEXCM }, 'i' },
9387 - { { STATE_PSRING }, 'i' },
9388 - { { STATE_EXCVADDR }, 'm' }
9391 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
9392 - { { 6 /* art */ }, 'o' }
9395 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
9396 - { { STATE_PSEXCM }, 'i' },
9397 - { { STATE_PSRING }, 'i' },
9398 - { { STATE_DEPC }, 'i' }
9401 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
9402 - { { 6 /* art */ }, 'i' }
9405 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
9406 - { { STATE_PSEXCM }, 'i' },
9407 - { { STATE_PSRING }, 'i' },
9408 - { { STATE_DEPC }, 'o' }
9411 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
9412 - { { 6 /* art */ }, 'm' }
9415 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
9416 - { { STATE_PSEXCM }, 'i' },
9417 - { { STATE_PSRING }, 'i' },
9418 - { { STATE_DEPC }, 'm' }
9421 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
9422 - { { 6 /* art */ }, 'o' }
9425 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
9426 - { { STATE_PSEXCM }, 'i' },
9427 - { { STATE_PSRING }, 'i' },
9428 - { { STATE_EXCCAUSE }, 'i' },
9429 - { { STATE_XTSYNC }, 'i' }
9432 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
9433 - { { 6 /* art */ }, 'i' }
9436 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
9437 - { { STATE_PSEXCM }, 'i' },
9438 - { { STATE_PSRING }, 'i' },
9439 - { { STATE_EXCCAUSE }, 'o' }
9442 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
9443 - { { 6 /* art */ }, 'm' }
9446 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
9447 - { { STATE_PSEXCM }, 'i' },
9448 - { { STATE_PSRING }, 'i' },
9449 - { { STATE_EXCCAUSE }, 'm' }
9452 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
9453 - { { 6 /* art */ }, 'o' }
9456 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
9457 - { { STATE_PSEXCM }, 'i' },
9458 - { { STATE_PSRING }, 'i' },
9459 - { { STATE_MISC0 }, 'i' }
9462 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
9463 - { { 6 /* art */ }, 'i' }
9466 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
9467 - { { STATE_PSEXCM }, 'i' },
9468 - { { STATE_PSRING }, 'i' },
9469 - { { STATE_MISC0 }, 'o' }
9472 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
9473 - { { 6 /* art */ }, 'm' }
9476 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
9477 - { { STATE_PSEXCM }, 'i' },
9478 - { { STATE_PSRING }, 'i' },
9479 - { { STATE_MISC0 }, 'm' }
9482 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
9483 - { { 6 /* art */ }, 'o' }
9486 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
9487 - { { STATE_PSEXCM }, 'i' },
9488 - { { STATE_PSRING }, 'i' },
9489 - { { STATE_MISC1 }, 'i' }
9492 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
9493 - { { 6 /* art */ }, 'i' }
9496 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
9497 - { { STATE_PSEXCM }, 'i' },
9498 - { { STATE_PSRING }, 'i' },
9499 - { { STATE_MISC1 }, 'o' }
9502 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
9503 - { { 6 /* art */ }, 'm' }
9506 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
9507 - { { STATE_PSEXCM }, 'i' },
9508 - { { STATE_PSRING }, 'i' },
9509 - { { STATE_MISC1 }, 'm' }
9512 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
9513 - { { 6 /* art */ }, 'o' }
9516 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
9517 - { { STATE_PSEXCM }, 'i' },
9518 - { { STATE_PSRING }, 'i' },
9519 - { { STATE_MISC2 }, 'i' }
9522 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
9523 - { { 6 /* art */ }, 'i' }
9526 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
9527 - { { STATE_PSEXCM }, 'i' },
9528 - { { STATE_PSRING }, 'i' },
9529 - { { STATE_MISC2 }, 'o' }
9532 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
9533 - { { 6 /* art */ }, 'm' }
9536 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
9537 - { { STATE_PSEXCM }, 'i' },
9538 - { { STATE_PSRING }, 'i' },
9539 - { { STATE_MISC2 }, 'm' }
9542 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
9543 - { { 6 /* art */ }, 'o' }
9546 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
9547 - { { STATE_PSEXCM }, 'i' },
9548 - { { STATE_PSRING }, 'i' },
9549 - { { STATE_MISC3 }, 'i' }
9552 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
9553 - { { 6 /* art */ }, 'i' }
9556 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
9557 - { { STATE_PSEXCM }, 'i' },
9558 - { { STATE_PSRING }, 'i' },
9559 - { { STATE_MISC3 }, 'o' }
9562 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
9563 - { { 6 /* art */ }, 'm' }
9566 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
9567 - { { STATE_PSEXCM }, 'i' },
9568 - { { STATE_PSRING }, 'i' },
9569 - { { STATE_MISC3 }, 'm' }
9572 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
9573 - { { 6 /* art */ }, 'o' }
9576 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
9577 - { { STATE_PSEXCM }, 'i' },
9578 - { { STATE_PSRING }, 'i' }
9581 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
9582 - { { 6 /* art */ }, 'o' }
9585 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
9586 - { { STATE_PSEXCM }, 'i' },
9587 - { { STATE_PSRING }, 'i' },
9588 - { { STATE_VECBASE }, 'i' }
9591 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
9592 - { { 6 /* art */ }, 'i' }
9595 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
9596 - { { STATE_PSEXCM }, 'i' },
9597 - { { STATE_PSRING }, 'i' },
9598 - { { STATE_VECBASE }, 'o' }
9601 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
9602 - { { 6 /* art */ }, 'm' }
9605 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
9606 - { { STATE_PSEXCM }, 'i' },
9607 - { { STATE_PSRING }, 'i' },
9608 - { { STATE_VECBASE }, 'm' }
9611 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
9612 - { { 4 /* ars */ }, 'i' },
9613 - { { 6 /* art */ }, 'i' }
9616 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
9617 - { { STATE_ACC }, 'o' }
9620 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
9621 - { { 4 /* ars */ }, 'i' },
9622 - { { 34 /* my */ }, 'i' }
9625 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
9626 - { { STATE_ACC }, 'o' }
9629 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
9630 - { { 33 /* mx */ }, 'i' },
9631 - { { 6 /* art */ }, 'i' }
9634 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
9635 - { { STATE_ACC }, 'o' }
9638 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
9639 - { { 33 /* mx */ }, 'i' },
9640 - { { 34 /* my */ }, 'i' }
9643 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
9644 - { { STATE_ACC }, 'o' }
9647 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
9648 - { { 4 /* ars */ }, 'i' },
9649 - { { 6 /* art */ }, 'i' }
9652 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
9653 - { { STATE_ACC }, 'm' }
9656 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
9657 - { { 4 /* ars */ }, 'i' },
9658 - { { 34 /* my */ }, 'i' }
9661 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
9662 - { { STATE_ACC }, 'm' }
9665 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
9666 - { { 33 /* mx */ }, 'i' },
9667 - { { 6 /* art */ }, 'i' }
9670 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
9671 - { { STATE_ACC }, 'm' }
9674 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
9675 - { { 33 /* mx */ }, 'i' },
9676 - { { 34 /* my */ }, 'i' }
9679 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
9680 - { { STATE_ACC }, 'm' }
9683 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
9684 - { { 35 /* mw */ }, 'o' },
9685 - { { 4 /* ars */ }, 'm' },
9686 - { { 33 /* mx */ }, 'i' },
9687 - { { 6 /* art */ }, 'i' }
9690 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
9691 - { { STATE_ACC }, 'm' }
9694 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
9695 - { { 35 /* mw */ }, 'o' },
9696 - { { 4 /* ars */ }, 'm' },
9697 - { { 33 /* mx */ }, 'i' },
9698 - { { 34 /* my */ }, 'i' }
9701 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
9702 - { { STATE_ACC }, 'm' }
9705 -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
9706 - { { 35 /* mw */ }, 'o' },
9707 - { { 4 /* ars */ }, 'm' }
9710 -static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
9711 - { { 3 /* arr */ }, 'o' },
9712 - { { 4 /* ars */ }, 'i' },
9713 - { { 6 /* art */ }, 'i' }
9716 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
9717 - { { 6 /* art */ }, 'o' },
9718 - { { 36 /* mr0 */ }, 'i' }
9721 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
9722 - { { 6 /* art */ }, 'i' },
9723 - { { 36 /* mr0 */ }, 'o' }
9726 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
9727 - { { 6 /* art */ }, 'm' },
9728 - { { 36 /* mr0 */ }, 'm' }
9731 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
9732 - { { 6 /* art */ }, 'o' },
9733 - { { 37 /* mr1 */ }, 'i' }
9736 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
9737 - { { 6 /* art */ }, 'i' },
9738 - { { 37 /* mr1 */ }, 'o' }
9741 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
9742 - { { 6 /* art */ }, 'm' },
9743 - { { 37 /* mr1 */ }, 'm' }
9746 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
9747 - { { 6 /* art */ }, 'o' },
9748 - { { 38 /* mr2 */ }, 'i' }
9751 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
9752 - { { 6 /* art */ }, 'i' },
9753 - { { 38 /* mr2 */ }, 'o' }
9756 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
9757 - { { 6 /* art */ }, 'm' },
9758 - { { 38 /* mr2 */ }, 'm' }
9761 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
9762 - { { 6 /* art */ }, 'o' },
9763 - { { 39 /* mr3 */ }, 'i' }
9766 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
9767 - { { 6 /* art */ }, 'i' },
9768 - { { 39 /* mr3 */ }, 'o' }
9771 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
9772 - { { 6 /* art */ }, 'm' },
9773 - { { 39 /* mr3 */ }, 'm' }
9776 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
9777 - { { 6 /* art */ }, 'o' }
9780 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
9781 - { { STATE_ACC }, 'i' }
9784 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
9785 - { { 6 /* art */ }, 'i' }
9788 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
9789 - { { STATE_ACC }, 'm' }
9792 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
9793 - { { 6 /* art */ }, 'm' }
9796 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
9797 - { { STATE_ACC }, 'm' }
9800 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
9801 - { { 6 /* art */ }, 'o' }
9804 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
9805 - { { STATE_ACC }, 'i' }
9808 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
9809 - { { 6 /* art */ }, 'i' }
9812 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
9813 - { { STATE_ACC }, 'm' }
9816 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
9817 - { { 6 /* art */ }, 'm' }
9820 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
9821 - { { STATE_ACC }, 'm' }
9824 -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
9825 - { { 70 /* s */ }, 'i' }
9828 -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
9829 - { { STATE_PSWOE }, 'o' },
9830 - { { STATE_PSCALLINC }, 'o' },
9831 - { { STATE_PSOWB }, 'o' },
9832 - { { STATE_PSRING }, 'm' },
9833 - { { STATE_PSUM }, 'o' },
9834 - { { STATE_PSEXCM }, 'm' },
9835 - { { STATE_PSINTLEVEL }, 'o' },
9836 - { { STATE_EPC1 }, 'i' },
9837 - { { STATE_EPC2 }, 'i' },
9838 - { { STATE_EPC3 }, 'i' },
9839 - { { STATE_EPC4 }, 'i' },
9840 - { { STATE_EPC5 }, 'i' },
9841 - { { STATE_EPC6 }, 'i' },
9842 - { { STATE_EPC7 }, 'i' },
9843 - { { STATE_EPS2 }, 'i' },
9844 - { { STATE_EPS3 }, 'i' },
9845 - { { STATE_EPS4 }, 'i' },
9846 - { { STATE_EPS5 }, 'i' },
9847 - { { STATE_EPS6 }, 'i' },
9848 - { { STATE_EPS7 }, 'i' },
9849 - { { STATE_InOCDMode }, 'm' }
9852 -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
9853 - { { 70 /* s */ }, 'i' }
9856 -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
9857 - { { STATE_PSEXCM }, 'i' },
9858 - { { STATE_PSRING }, 'i' },
9859 - { { STATE_PSINTLEVEL }, 'o' }
9862 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
9863 - { { 6 /* art */ }, 'o' }
9866 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
9867 - { { STATE_PSEXCM }, 'i' },
9868 - { { STATE_PSRING }, 'i' },
9869 - { { STATE_INTERRUPT }, 'i' }
9872 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
9873 - { { 6 /* art */ }, 'i' }
9876 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
9877 - { { STATE_PSEXCM }, 'i' },
9878 - { { STATE_PSRING }, 'i' },
9879 - { { STATE_XTSYNC }, 'o' },
9880 - { { STATE_INTERRUPT }, 'm' }
9883 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
9884 - { { 6 /* art */ }, 'i' }
9887 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
9888 - { { STATE_PSEXCM }, 'i' },
9889 - { { STATE_PSRING }, 'i' },
9890 - { { STATE_XTSYNC }, 'o' },
9891 - { { STATE_INTERRUPT }, 'm' }
9894 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
9895 - { { 6 /* art */ }, 'o' }
9898 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
9899 - { { STATE_PSEXCM }, 'i' },
9900 - { { STATE_PSRING }, 'i' },
9901 - { { STATE_INTENABLE }, 'i' }
9904 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
9905 - { { 6 /* art */ }, 'i' }
9908 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
9909 - { { STATE_PSEXCM }, 'i' },
9910 - { { STATE_PSRING }, 'i' },
9911 - { { STATE_INTENABLE }, 'o' }
9914 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
9915 - { { 6 /* art */ }, 'm' }
9918 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
9919 - { { STATE_PSEXCM }, 'i' },
9920 - { { STATE_PSRING }, 'i' },
9921 - { { STATE_INTENABLE }, 'm' }
9924 -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
9925 - { { 41 /* imms */ }, 'i' },
9926 - { { 40 /* immt */ }, 'i' }
9929 -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
9930 - { { STATE_PSEXCM }, 'i' },
9931 - { { STATE_PSINTLEVEL }, 'i' }
9934 -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
9935 - { { 41 /* imms */ }, 'i' }
9938 -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
9939 - { { STATE_PSEXCM }, 'i' },
9940 - { { STATE_PSINTLEVEL }, 'i' }
9943 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
9944 - { { 6 /* art */ }, 'o' }
9947 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
9948 - { { STATE_PSEXCM }, 'i' },
9949 - { { STATE_PSRING }, 'i' },
9950 - { { STATE_DBREAKA0 }, 'i' }
9953 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
9954 - { { 6 /* art */ }, 'i' }
9957 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
9958 - { { STATE_PSEXCM }, 'i' },
9959 - { { STATE_PSRING }, 'i' },
9960 - { { STATE_DBREAKA0 }, 'o' },
9961 - { { STATE_XTSYNC }, 'o' }
9964 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
9965 - { { 6 /* art */ }, 'm' }
9968 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
9969 - { { STATE_PSEXCM }, 'i' },
9970 - { { STATE_PSRING }, 'i' },
9971 - { { STATE_DBREAKA0 }, 'm' },
9972 - { { STATE_XTSYNC }, 'o' }
9975 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
9976 - { { 6 /* art */ }, 'o' }
9979 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
9980 - { { STATE_PSEXCM }, 'i' },
9981 - { { STATE_PSRING }, 'i' },
9982 - { { STATE_DBREAKC0 }, 'i' }
9985 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
9986 - { { 6 /* art */ }, 'i' }
9989 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
9990 - { { STATE_PSEXCM }, 'i' },
9991 - { { STATE_PSRING }, 'i' },
9992 - { { STATE_DBREAKC0 }, 'o' },
9993 - { { STATE_XTSYNC }, 'o' }
9996 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
9997 - { { 6 /* art */ }, 'm' }
10000 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
10001 - { { STATE_PSEXCM }, 'i' },
10002 - { { STATE_PSRING }, 'i' },
10003 - { { STATE_DBREAKC0 }, 'm' },
10004 - { { STATE_XTSYNC }, 'o' }
10007 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
10008 - { { 6 /* art */ }, 'o' }
10011 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
10012 - { { STATE_PSEXCM }, 'i' },
10013 - { { STATE_PSRING }, 'i' },
10014 - { { STATE_DBREAKA1 }, 'i' }
10017 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
10018 - { { 6 /* art */ }, 'i' }
10021 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
10022 - { { STATE_PSEXCM }, 'i' },
10023 - { { STATE_PSRING }, 'i' },
10024 - { { STATE_DBREAKA1 }, 'o' },
10025 - { { STATE_XTSYNC }, 'o' }
10028 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
10029 - { { 6 /* art */ }, 'm' }
10032 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
10033 - { { STATE_PSEXCM }, 'i' },
10034 - { { STATE_PSRING }, 'i' },
10035 - { { STATE_DBREAKA1 }, 'm' },
10036 - { { STATE_XTSYNC }, 'o' }
10039 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
10040 - { { 6 /* art */ }, 'o' }
10043 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
10044 - { { STATE_PSEXCM }, 'i' },
10045 - { { STATE_PSRING }, 'i' },
10046 - { { STATE_DBREAKC1 }, 'i' }
10049 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
10050 - { { 6 /* art */ }, 'i' }
10053 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
10054 - { { STATE_PSEXCM }, 'i' },
10055 - { { STATE_PSRING }, 'i' },
10056 - { { STATE_DBREAKC1 }, 'o' },
10057 - { { STATE_XTSYNC }, 'o' }
10060 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
10061 - { { 6 /* art */ }, 'm' }
10064 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
10065 - { { STATE_PSEXCM }, 'i' },
10066 - { { STATE_PSRING }, 'i' },
10067 - { { STATE_DBREAKC1 }, 'm' },
10068 - { { STATE_XTSYNC }, 'o' }
10071 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
10072 - { { 6 /* art */ }, 'o' }
10075 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
10076 - { { STATE_PSEXCM }, 'i' },
10077 - { { STATE_PSRING }, 'i' },
10078 - { { STATE_IBREAKA0 }, 'i' }
10081 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
10082 - { { 6 /* art */ }, 'i' }
10085 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
10086 - { { STATE_PSEXCM }, 'i' },
10087 - { { STATE_PSRING }, 'i' },
10088 - { { STATE_IBREAKA0 }, 'o' }
10091 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
10092 - { { 6 /* art */ }, 'm' }
10095 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
10096 - { { STATE_PSEXCM }, 'i' },
10097 - { { STATE_PSRING }, 'i' },
10098 - { { STATE_IBREAKA0 }, 'm' }
10101 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
10102 - { { 6 /* art */ }, 'o' }
10105 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
10106 - { { STATE_PSEXCM }, 'i' },
10107 - { { STATE_PSRING }, 'i' },
10108 - { { STATE_IBREAKA1 }, 'i' }
10111 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
10112 - { { 6 /* art */ }, 'i' }
10115 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
10116 - { { STATE_PSEXCM }, 'i' },
10117 - { { STATE_PSRING }, 'i' },
10118 - { { STATE_IBREAKA1 }, 'o' }
10121 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
10122 - { { 6 /* art */ }, 'm' }
10125 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
10126 - { { STATE_PSEXCM }, 'i' },
10127 - { { STATE_PSRING }, 'i' },
10128 - { { STATE_IBREAKA1 }, 'm' }
10131 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
10132 - { { 6 /* art */ }, 'o' }
10135 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
10136 - { { STATE_PSEXCM }, 'i' },
10137 - { { STATE_PSRING }, 'i' },
10138 - { { STATE_IBREAKENABLE }, 'i' }
10141 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
10142 - { { 6 /* art */ }, 'i' }
10145 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
10146 - { { STATE_PSEXCM }, 'i' },
10147 - { { STATE_PSRING }, 'i' },
10148 - { { STATE_IBREAKENABLE }, 'o' }
10151 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
10152 - { { 6 /* art */ }, 'm' }
10155 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
10156 - { { STATE_PSEXCM }, 'i' },
10157 - { { STATE_PSRING }, 'i' },
10158 - { { STATE_IBREAKENABLE }, 'm' }
10161 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
10162 - { { 6 /* art */ }, 'o' }
10165 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
10166 - { { STATE_PSEXCM }, 'i' },
10167 - { { STATE_PSRING }, 'i' },
10168 - { { STATE_DEBUGCAUSE }, 'i' },
10169 - { { STATE_DBNUM }, 'i' }
10172 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
10173 - { { 6 /* art */ }, 'i' }
10176 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
10177 - { { STATE_PSEXCM }, 'i' },
10178 - { { STATE_PSRING }, 'i' },
10179 - { { STATE_DEBUGCAUSE }, 'o' },
10180 - { { STATE_DBNUM }, 'o' }
10183 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
10184 - { { 6 /* art */ }, 'm' }
10187 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
10188 - { { STATE_PSEXCM }, 'i' },
10189 - { { STATE_PSRING }, 'i' },
10190 - { { STATE_DEBUGCAUSE }, 'm' },
10191 - { { STATE_DBNUM }, 'm' }
10194 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
10195 - { { 6 /* art */ }, 'o' }
10198 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
10199 - { { STATE_PSEXCM }, 'i' },
10200 - { { STATE_PSRING }, 'i' },
10201 - { { STATE_ICOUNT }, 'i' }
10204 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
10205 - { { 6 /* art */ }, 'i' }
10208 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
10209 - { { STATE_PSEXCM }, 'i' },
10210 - { { STATE_PSRING }, 'i' },
10211 - { { STATE_XTSYNC }, 'o' },
10212 - { { STATE_ICOUNT }, 'o' }
10215 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
10216 - { { 6 /* art */ }, 'm' }
10219 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
10220 - { { STATE_PSEXCM }, 'i' },
10221 - { { STATE_PSRING }, 'i' },
10222 - { { STATE_XTSYNC }, 'o' },
10223 - { { STATE_ICOUNT }, 'm' }
10226 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
10227 - { { 6 /* art */ }, 'o' }
10230 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
10231 - { { STATE_PSEXCM }, 'i' },
10232 - { { STATE_PSRING }, 'i' },
10233 - { { STATE_ICOUNTLEVEL }, 'i' }
10236 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
10237 - { { 6 /* art */ }, 'i' }
10240 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
10241 - { { STATE_PSEXCM }, 'i' },
10242 - { { STATE_PSRING }, 'i' },
10243 - { { STATE_ICOUNTLEVEL }, 'o' }
10246 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
10247 - { { 6 /* art */ }, 'm' }
10250 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
10251 - { { STATE_PSEXCM }, 'i' },
10252 - { { STATE_PSRING }, 'i' },
10253 - { { STATE_ICOUNTLEVEL }, 'm' }
10256 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
10257 - { { 6 /* art */ }, 'o' }
10260 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
10261 - { { STATE_PSEXCM }, 'i' },
10262 - { { STATE_PSRING }, 'i' },
10263 - { { STATE_DDR }, 'i' }
10266 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
10267 - { { 6 /* art */ }, 'i' }
10270 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
10271 - { { STATE_PSEXCM }, 'i' },
10272 - { { STATE_PSRING }, 'i' },
10273 - { { STATE_XTSYNC }, 'o' },
10274 - { { STATE_DDR }, 'o' }
10277 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
10278 - { { 6 /* art */ }, 'm' }
10281 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
10282 - { { STATE_PSEXCM }, 'i' },
10283 - { { STATE_PSRING }, 'i' },
10284 - { { STATE_XTSYNC }, 'o' },
10285 - { { STATE_DDR }, 'm' }
10288 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
10289 - { { 41 /* imms */ }, 'i' }
10292 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
10293 - { { STATE_InOCDMode }, 'm' },
10294 - { { STATE_EPC6 }, 'i' },
10295 - { { STATE_PSWOE }, 'o' },
10296 - { { STATE_PSCALLINC }, 'o' },
10297 - { { STATE_PSOWB }, 'o' },
10298 - { { STATE_PSRING }, 'o' },
10299 - { { STATE_PSUM }, 'o' },
10300 - { { STATE_PSEXCM }, 'o' },
10301 - { { STATE_PSINTLEVEL }, 'o' },
10302 - { { STATE_EPS6 }, 'i' }
10305 -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
10306 - { { STATE_InOCDMode }, 'm' }
10309 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
10310 - { { 6 /* art */ }, 'i' }
10313 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
10314 - { { STATE_PSEXCM }, 'i' },
10315 - { { STATE_PSRING }, 'i' },
10316 - { { STATE_XTSYNC }, 'o' }
10319 -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
10320 - { { 44 /* br */ }, 'o' },
10321 - { { 43 /* bs */ }, 'i' },
10322 - { { 42 /* bt */ }, 'i' }
10325 -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
10326 - { { 42 /* bt */ }, 'o' },
10327 - { { 49 /* bs4 */ }, 'i' }
10330 -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
10331 - { { 42 /* bt */ }, 'o' },
10332 - { { 52 /* bs8 */ }, 'i' }
10335 -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
10336 - { { 43 /* bs */ }, 'i' },
10337 - { { 28 /* label8 */ }, 'i' }
10340 -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
10341 - { { 3 /* arr */ }, 'm' },
10342 - { { 4 /* ars */ }, 'i' },
10343 - { { 42 /* bt */ }, 'i' }
10346 -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
10347 - { { 6 /* art */ }, 'o' },
10348 - { { 57 /* brall */ }, 'i' }
10351 -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
10352 - { { 6 /* art */ }, 'i' },
10353 - { { 57 /* brall */ }, 'o' }
10356 -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
10357 - { { 6 /* art */ }, 'm' },
10358 - { { 57 /* brall */ }, 'm' }
10361 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
10362 - { { 6 /* art */ }, 'o' }
10365 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
10366 - { { STATE_PSEXCM }, 'i' },
10367 - { { STATE_PSRING }, 'i' },
10368 - { { STATE_CCOUNT }, 'i' }
10371 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
10372 - { { 6 /* art */ }, 'i' }
10375 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
10376 - { { STATE_PSEXCM }, 'i' },
10377 - { { STATE_PSRING }, 'i' },
10378 - { { STATE_XTSYNC }, 'o' },
10379 - { { STATE_CCOUNT }, 'o' }
10382 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
10383 - { { 6 /* art */ }, 'm' }
10386 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
10387 - { { STATE_PSEXCM }, 'i' },
10388 - { { STATE_PSRING }, 'i' },
10389 - { { STATE_XTSYNC }, 'o' },
10390 - { { STATE_CCOUNT }, 'm' }
10393 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
10394 - { { 6 /* art */ }, 'o' }
10397 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
10398 - { { STATE_PSEXCM }, 'i' },
10399 - { { STATE_PSRING }, 'i' },
10400 - { { STATE_CCOMPARE0 }, 'i' }
10403 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
10404 - { { 6 /* art */ }, 'i' }
10407 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
10408 - { { STATE_PSEXCM }, 'i' },
10409 - { { STATE_PSRING }, 'i' },
10410 - { { STATE_CCOMPARE0 }, 'o' },
10411 - { { STATE_INTERRUPT }, 'm' }
10414 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
10415 - { { 6 /* art */ }, 'm' }
10418 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
10419 - { { STATE_PSEXCM }, 'i' },
10420 - { { STATE_PSRING }, 'i' },
10421 - { { STATE_CCOMPARE0 }, 'm' },
10422 - { { STATE_INTERRUPT }, 'm' }
10425 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
10426 - { { 6 /* art */ }, 'o' }
10429 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
10430 - { { STATE_PSEXCM }, 'i' },
10431 - { { STATE_PSRING }, 'i' },
10432 - { { STATE_CCOMPARE1 }, 'i' }
10435 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
10436 - { { 6 /* art */ }, 'i' }
10439 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
10440 - { { STATE_PSEXCM }, 'i' },
10441 - { { STATE_PSRING }, 'i' },
10442 - { { STATE_CCOMPARE1 }, 'o' },
10443 - { { STATE_INTERRUPT }, 'm' }
10446 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
10447 - { { 6 /* art */ }, 'm' }
10450 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
10451 - { { STATE_PSEXCM }, 'i' },
10452 - { { STATE_PSRING }, 'i' },
10453 - { { STATE_CCOMPARE1 }, 'm' },
10454 - { { STATE_INTERRUPT }, 'm' }
10457 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
10458 - { { 6 /* art */ }, 'o' }
10461 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
10462 - { { STATE_PSEXCM }, 'i' },
10463 - { { STATE_PSRING }, 'i' },
10464 - { { STATE_CCOMPARE2 }, 'i' }
10467 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
10468 - { { 6 /* art */ }, 'i' }
10471 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
10472 - { { STATE_PSEXCM }, 'i' },
10473 - { { STATE_PSRING }, 'i' },
10474 - { { STATE_CCOMPARE2 }, 'o' },
10475 - { { STATE_INTERRUPT }, 'm' }
10478 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
10479 - { { 6 /* art */ }, 'm' }
10482 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
10483 - { { STATE_PSEXCM }, 'i' },
10484 - { { STATE_PSRING }, 'i' },
10485 - { { STATE_CCOMPARE2 }, 'm' },
10486 - { { STATE_INTERRUPT }, 'm' }
10489 -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
10490 - { { 4 /* ars */ }, 'i' },
10491 - { { 21 /* uimm8x4 */ }, 'i' }
10494 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
10495 - { { 4 /* ars */ }, 'i' },
10496 - { { 22 /* uimm4x16 */ }, 'i' }
10499 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
10500 - { { STATE_PSEXCM }, 'i' },
10501 - { { STATE_PSRING }, 'i' }
10504 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
10505 - { { 4 /* ars */ }, 'i' },
10506 - { { 21 /* uimm8x4 */ }, 'i' }
10509 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
10510 - { { STATE_PSEXCM }, 'i' },
10511 - { { STATE_PSRING }, 'i' }
10514 -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
10515 - { { 6 /* art */ }, 'o' },
10516 - { { 4 /* ars */ }, 'i' }
10519 -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
10520 - { { STATE_PSEXCM }, 'i' },
10521 - { { STATE_PSRING }, 'i' }
10524 -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
10525 - { { 6 /* art */ }, 'i' },
10526 - { { 4 /* ars */ }, 'i' }
10529 -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
10530 - { { STATE_PSEXCM }, 'i' },
10531 - { { STATE_PSRING }, 'i' }
10534 -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
10535 - { { 4 /* ars */ }, 'i' },
10536 - { { 21 /* uimm8x4 */ }, 'i' }
10539 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
10540 - { { 4 /* ars */ }, 'i' },
10541 - { { 22 /* uimm4x16 */ }, 'i' }
10544 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
10545 - { { STATE_PSEXCM }, 'i' },
10546 - { { STATE_PSRING }, 'i' }
10549 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
10550 - { { 4 /* ars */ }, 'i' },
10551 - { { 21 /* uimm8x4 */ }, 'i' }
10554 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
10555 - { { STATE_PSEXCM }, 'i' },
10556 - { { STATE_PSRING }, 'i' }
10559 -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
10560 - { { 4 /* ars */ }, 'i' },
10561 - { { 21 /* uimm8x4 */ }, 'i' }
10564 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
10565 - { { 4 /* ars */ }, 'i' },
10566 - { { 22 /* uimm4x16 */ }, 'i' }
10569 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
10570 - { { STATE_PSEXCM }, 'i' },
10571 - { { STATE_PSRING }, 'i' }
10574 -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
10575 - { { 6 /* art */ }, 'i' },
10576 - { { 4 /* ars */ }, 'i' }
10579 -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
10580 - { { STATE_PSEXCM }, 'i' },
10581 - { { STATE_PSRING }, 'i' }
10584 -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
10585 - { { 6 /* art */ }, 'o' },
10586 - { { 4 /* ars */ }, 'i' }
10589 -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
10590 - { { STATE_PSEXCM }, 'i' },
10591 - { { STATE_PSRING }, 'i' }
10594 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
10595 - { { 6 /* art */ }, 'i' }
10598 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
10599 - { { STATE_PSEXCM }, 'i' },
10600 - { { STATE_PSRING }, 'i' },
10601 - { { STATE_PTBASE }, 'o' },
10602 - { { STATE_XTSYNC }, 'o' }
10605 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
10606 - { { 6 /* art */ }, 'o' }
10609 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
10610 - { { STATE_PSEXCM }, 'i' },
10611 - { { STATE_PSRING }, 'i' },
10612 - { { STATE_PTBASE }, 'i' },
10613 - { { STATE_EXCVADDR }, 'i' }
10616 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
10617 - { { 6 /* art */ }, 'm' }
10620 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
10621 - { { STATE_PSEXCM }, 'i' },
10622 - { { STATE_PSRING }, 'i' },
10623 - { { STATE_PTBASE }, 'm' },
10624 - { { STATE_EXCVADDR }, 'i' },
10625 - { { STATE_XTSYNC }, 'o' }
10628 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
10629 - { { 6 /* art */ }, 'o' }
10632 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
10633 - { { STATE_PSEXCM }, 'i' },
10634 - { { STATE_PSRING }, 'i' },
10635 - { { STATE_ASID3 }, 'i' },
10636 - { { STATE_ASID2 }, 'i' },
10637 - { { STATE_ASID1 }, 'i' }
10640 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
10641 - { { 6 /* art */ }, 'i' }
10644 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
10645 - { { STATE_XTSYNC }, 'o' },
10646 - { { STATE_PSEXCM }, 'i' },
10647 - { { STATE_PSRING }, 'i' },
10648 - { { STATE_ASID3 }, 'o' },
10649 - { { STATE_ASID2 }, 'o' },
10650 - { { STATE_ASID1 }, 'o' }
10653 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
10654 - { { 6 /* art */ }, 'm' }
10657 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
10658 - { { STATE_XTSYNC }, 'o' },
10659 - { { STATE_PSEXCM }, 'i' },
10660 - { { STATE_PSRING }, 'i' },
10661 - { { STATE_ASID3 }, 'm' },
10662 - { { STATE_ASID2 }, 'm' },
10663 - { { STATE_ASID1 }, 'm' }
10666 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
10667 - { { 6 /* art */ }, 'o' }
10670 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
10671 - { { STATE_PSEXCM }, 'i' },
10672 - { { STATE_PSRING }, 'i' },
10673 - { { STATE_INSTPGSZID4 }, 'i' }
10676 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
10677 - { { 6 /* art */ }, 'i' }
10680 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
10681 - { { STATE_XTSYNC }, 'o' },
10682 - { { STATE_PSEXCM }, 'i' },
10683 - { { STATE_PSRING }, 'i' },
10684 - { { STATE_INSTPGSZID4 }, 'o' }
10687 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
10688 - { { 6 /* art */ }, 'm' }
10691 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
10692 - { { STATE_XTSYNC }, 'o' },
10693 - { { STATE_PSEXCM }, 'i' },
10694 - { { STATE_PSRING }, 'i' },
10695 - { { STATE_INSTPGSZID4 }, 'm' }
10698 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
10699 - { { 6 /* art */ }, 'o' }
10702 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
10703 - { { STATE_PSEXCM }, 'i' },
10704 - { { STATE_PSRING }, 'i' },
10705 - { { STATE_DATAPGSZID4 }, 'i' }
10708 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
10709 - { { 6 /* art */ }, 'i' }
10712 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
10713 - { { STATE_XTSYNC }, 'o' },
10714 - { { STATE_PSEXCM }, 'i' },
10715 - { { STATE_PSRING }, 'i' },
10716 - { { STATE_DATAPGSZID4 }, 'o' }
10719 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
10720 - { { 6 /* art */ }, 'm' }
10723 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
10724 - { { STATE_XTSYNC }, 'o' },
10725 - { { STATE_PSEXCM }, 'i' },
10726 - { { STATE_PSRING }, 'i' },
10727 - { { STATE_DATAPGSZID4 }, 'm' }
10730 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
10731 - { { 4 /* ars */ }, 'i' }
10734 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
10735 - { { STATE_PSEXCM }, 'i' },
10736 - { { STATE_PSRING }, 'i' },
10737 - { { STATE_XTSYNC }, 'o' }
10740 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
10741 - { { 6 /* art */ }, 'o' },
10742 - { { 4 /* ars */ }, 'i' }
10745 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
10746 - { { STATE_PSEXCM }, 'i' },
10747 - { { STATE_PSRING }, 'i' }
10750 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
10751 - { { 6 /* art */ }, 'i' },
10752 - { { 4 /* ars */ }, 'i' }
10755 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
10756 - { { STATE_PSEXCM }, 'i' },
10757 - { { STATE_PSRING }, 'i' },
10758 - { { STATE_XTSYNC }, 'o' }
10761 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
10762 - { { 4 /* ars */ }, 'i' }
10765 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
10766 - { { STATE_PSEXCM }, 'i' },
10767 - { { STATE_PSRING }, 'i' }
10770 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
10771 - { { 6 /* art */ }, 'o' },
10772 - { { 4 /* ars */ }, 'i' }
10775 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
10776 - { { STATE_PSEXCM }, 'i' },
10777 - { { STATE_PSRING }, 'i' }
10780 -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
10781 - { { 6 /* art */ }, 'i' },
10782 - { { 4 /* ars */ }, 'i' }
10785 -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
10786 - { { STATE_PSEXCM }, 'i' },
10787 - { { STATE_PSRING }, 'i' }
10790 -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
10791 - { { STATE_PTBASE }, 'i' },
10792 - { { STATE_EXCVADDR }, 'i' }
10795 -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
10796 - { { STATE_EXCVADDR }, 'i' }
10799 -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
10800 - { { STATE_EXCVADDR }, 'i' }
10803 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
10804 - { { 6 /* art */ }, 'o' }
10807 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
10808 - { { STATE_PSEXCM }, 'i' },
10809 - { { STATE_PSRING }, 'i' },
10810 - { { STATE_CPENABLE }, 'i' }
10813 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
10814 - { { 6 /* art */ }, 'i' }
10817 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
10818 - { { STATE_PSEXCM }, 'i' },
10819 - { { STATE_PSRING }, 'i' },
10820 - { { STATE_CPENABLE }, 'o' }
10823 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
10824 - { { 6 /* art */ }, 'm' }
10827 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
10828 - { { STATE_PSEXCM }, 'i' },
10829 - { { STATE_PSRING }, 'i' },
10830 - { { STATE_CPENABLE }, 'm' }
10833 -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
10834 - { { 3 /* arr */ }, 'o' },
10835 - { { 4 /* ars */ }, 'i' },
10836 - { { 58 /* tp7 */ }, 'i' }
10839 -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
10840 - { { 3 /* arr */ }, 'o' },
10841 - { { 4 /* ars */ }, 'i' },
10842 - { { 6 /* art */ }, 'i' }
10845 -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
10846 - { { 6 /* art */ }, 'o' },
10847 - { { 4 /* ars */ }, 'i' }
10850 -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
10851 - { { 3 /* arr */ }, 'o' },
10852 - { { 4 /* ars */ }, 'i' },
10853 - { { 58 /* tp7 */ }, 'i' }
10856 -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
10857 - { { 6 /* art */ }, 'o' },
10858 - { { 4 /* ars */ }, 'i' },
10859 - { { 21 /* uimm8x4 */ }, 'i' }
10862 -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
10863 - { { 6 /* art */ }, 'i' },
10864 - { { 4 /* ars */ }, 'i' },
10865 - { { 21 /* uimm8x4 */ }, 'i' }
10868 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
10869 - { { 6 /* art */ }, 'm' },
10870 - { { 4 /* ars */ }, 'i' },
10871 - { { 21 /* uimm8x4 */ }, 'i' }
10874 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
10875 - { { STATE_SCOMPARE1 }, 'i' },
10876 - { { STATE_SCOMPARE1 }, 'i' }
10879 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
10880 - { { 6 /* art */ }, 'o' }
10883 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
10884 - { { STATE_SCOMPARE1 }, 'i' }
10887 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
10888 - { { 6 /* art */ }, 'i' }
10891 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
10892 - { { STATE_SCOMPARE1 }, 'o' }
10895 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
10896 - { { 6 /* art */ }, 'm' }
10899 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
10900 - { { STATE_SCOMPARE1 }, 'm' }
10903 -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
10904 - { { 3 /* arr */ }, 'o' },
10905 - { { 4 /* ars */ }, 'i' },
10906 - { { 6 /* art */ }, 'i' }
10909 -static xtensa_arg_internal Iclass_xt_mul32_args[] = {
10910 - { { 3 /* arr */ }, 'o' },
10911 - { { 4 /* ars */ }, 'i' },
10912 - { { 6 /* art */ }, 'i' }
10915 -static xtensa_arg_internal Iclass_rur_fcr_args[] = {
10916 - { { 3 /* arr */ }, 'o' }
10919 -static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
10920 - { { STATE_RoundMode }, 'i' },
10921 - { { STATE_InvalidEnable }, 'i' },
10922 - { { STATE_DivZeroEnable }, 'i' },
10923 - { { STATE_OverflowEnable }, 'i' },
10924 - { { STATE_UnderflowEnable }, 'i' },
10925 - { { STATE_InexactEnable }, 'i' },
10926 - { { STATE_FPreserved20 }, 'i' },
10927 - { { STATE_FPreserved5 }, 'i' },
10928 - { { STATE_CPENABLE }, 'i' }
10931 -static xtensa_arg_internal Iclass_wur_fcr_args[] = {
10932 - { { 6 /* art */ }, 'i' }
10935 -static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
10936 - { { STATE_RoundMode }, 'o' },
10937 - { { STATE_InvalidEnable }, 'o' },
10938 - { { STATE_DivZeroEnable }, 'o' },
10939 - { { STATE_OverflowEnable }, 'o' },
10940 - { { STATE_UnderflowEnable }, 'o' },
10941 - { { STATE_InexactEnable }, 'o' },
10942 - { { STATE_FPreserved20 }, 'o' },
10943 - { { STATE_FPreserved5 }, 'o' },
10944 - { { STATE_CPENABLE }, 'i' }
10947 -static xtensa_arg_internal Iclass_rur_fsr_args[] = {
10948 - { { 3 /* arr */ }, 'o' }
10951 -static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
10952 - { { STATE_InvalidFlag }, 'i' },
10953 - { { STATE_DivZeroFlag }, 'i' },
10954 - { { STATE_OverflowFlag }, 'i' },
10955 - { { STATE_UnderflowFlag }, 'i' },
10956 - { { STATE_InexactFlag }, 'i' },
10957 - { { STATE_FPreserved20a }, 'i' },
10958 - { { STATE_FPreserved7 }, 'i' },
10959 - { { STATE_CPENABLE }, 'i' }
10962 -static xtensa_arg_internal Iclass_wur_fsr_args[] = {
10963 - { { 6 /* art */ }, 'i' }
10966 -static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
10967 - { { STATE_InvalidFlag }, 'o' },
10968 - { { STATE_DivZeroFlag }, 'o' },
10969 - { { STATE_OverflowFlag }, 'o' },
10970 - { { STATE_UnderflowFlag }, 'o' },
10971 - { { STATE_InexactFlag }, 'o' },
10972 - { { STATE_FPreserved20a }, 'o' },
10973 - { { STATE_FPreserved7 }, 'o' },
10974 - { { STATE_CPENABLE }, 'i' }
10977 -static xtensa_arg_internal Iclass_fp_args[] = {
10978 - { { 62 /* frr */ }, 'o' },
10979 - { { 63 /* frs */ }, 'i' },
10980 - { { 64 /* frt */ }, 'i' }
10983 -static xtensa_arg_internal Iclass_fp_stateArgs[] = {
10984 - { { STATE_RoundMode }, 'i' },
10985 - { { STATE_CPENABLE }, 'i' }
10988 -static xtensa_arg_internal Iclass_fp_mac_args[] = {
10989 - { { 62 /* frr */ }, 'm' },
10990 - { { 63 /* frs */ }, 'i' },
10991 - { { 64 /* frt */ }, 'i' }
10994 -static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
10995 - { { STATE_RoundMode }, 'i' },
10996 - { { STATE_CPENABLE }, 'i' }
10999 -static xtensa_arg_internal Iclass_fp_cmov_args[] = {
11000 - { { 62 /* frr */ }, 'm' },
11001 - { { 63 /* frs */ }, 'i' },
11002 - { { 42 /* bt */ }, 'i' }
11005 -static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
11006 - { { STATE_CPENABLE }, 'i' }
11009 -static xtensa_arg_internal Iclass_fp_mov_args[] = {
11010 - { { 62 /* frr */ }, 'm' },
11011 - { { 63 /* frs */ }, 'i' },
11012 - { { 6 /* art */ }, 'i' }
11015 -static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
11016 - { { STATE_CPENABLE }, 'i' }
11019 -static xtensa_arg_internal Iclass_fp_mov2_args[] = {
11020 - { { 62 /* frr */ }, 'o' },
11021 - { { 63 /* frs */ }, 'i' }
11024 -static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
11025 - { { STATE_CPENABLE }, 'i' }
11028 -static xtensa_arg_internal Iclass_fp_cmp_args[] = {
11029 - { { 44 /* br */ }, 'o' },
11030 - { { 63 /* frs */ }, 'i' },
11031 - { { 64 /* frt */ }, 'i' }
11034 -static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
11035 - { { STATE_CPENABLE }, 'i' }
11038 -static xtensa_arg_internal Iclass_fp_float_args[] = {
11039 - { { 62 /* frr */ }, 'o' },
11040 - { { 4 /* ars */ }, 'i' },
11041 - { { 65 /* t */ }, 'i' }
11044 -static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
11045 - { { STATE_RoundMode }, 'i' },
11046 - { { STATE_CPENABLE }, 'i' }
11049 -static xtensa_arg_internal Iclass_fp_int_args[] = {
11050 - { { 3 /* arr */ }, 'o' },
11051 - { { 63 /* frs */ }, 'i' },
11052 - { { 65 /* t */ }, 'i' }
11055 -static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
11056 - { { STATE_CPENABLE }, 'i' }
11059 -static xtensa_arg_internal Iclass_fp_rfr_args[] = {
11060 - { { 3 /* arr */ }, 'o' },
11061 - { { 63 /* frs */ }, 'i' }
11064 -static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
11065 - { { STATE_CPENABLE }, 'i' }
11068 -static xtensa_arg_internal Iclass_fp_wfr_args[] = {
11069 - { { 62 /* frr */ }, 'o' },
11070 - { { 4 /* ars */ }, 'i' }
11073 -static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
11074 - { { STATE_CPENABLE }, 'i' }
11077 -static xtensa_arg_internal Iclass_fp_lsi_args[] = {
11078 - { { 64 /* frt */ }, 'o' },
11079 - { { 4 /* ars */ }, 'i' },
11080 - { { 61 /* cimm8x4 */ }, 'i' }
11083 -static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
11084 - { { STATE_CPENABLE }, 'i' }
11087 -static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
11088 - { { 64 /* frt */ }, 'o' },
11089 - { { 4 /* ars */ }, 'm' },
11090 - { { 61 /* cimm8x4 */ }, 'i' }
11093 -static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
11094 - { { STATE_CPENABLE }, 'i' }
11097 -static xtensa_arg_internal Iclass_fp_lsx_args[] = {
11098 - { { 62 /* frr */ }, 'o' },
11099 - { { 4 /* ars */ }, 'i' },
11100 - { { 6 /* art */ }, 'i' }
11103 -static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
11104 - { { STATE_CPENABLE }, 'i' }
11107 -static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
11108 - { { 62 /* frr */ }, 'o' },
11109 - { { 4 /* ars */ }, 'm' },
11110 - { { 6 /* art */ }, 'i' }
11113 -static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
11114 - { { STATE_CPENABLE }, 'i' }
11117 -static xtensa_arg_internal Iclass_fp_ssi_args[] = {
11118 - { { 64 /* frt */ }, 'i' },
11119 - { { 4 /* ars */ }, 'i' },
11120 - { { 61 /* cimm8x4 */ }, 'i' }
11123 -static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
11124 - { { STATE_CPENABLE }, 'i' }
11127 -static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
11128 - { { 64 /* frt */ }, 'i' },
11129 - { { 4 /* ars */ }, 'm' },
11130 - { { 61 /* cimm8x4 */ }, 'i' }
11133 -static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
11134 - { { STATE_CPENABLE }, 'i' }
11137 -static xtensa_arg_internal Iclass_fp_ssx_args[] = {
11138 - { { 62 /* frr */ }, 'i' },
11139 - { { 4 /* ars */ }, 'i' },
11140 - { { 6 /* art */ }, 'i' }
11143 -static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
11144 - { { STATE_CPENABLE }, 'i' }
11147 -static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
11148 - { { 62 /* frr */ }, 'i' },
11149 - { { 4 /* ars */ }, 'm' },
11150 - { { 6 /* art */ }, 'i' }
11153 -static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
11154 - { { STATE_CPENABLE }, 'i' }
11157 -static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
11158 - { { 4 /* ars */ }, 'i' },
11159 - { { 60 /* xt_wbr18_label */ }, 'i' }
11162 -static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
11163 - { { 4 /* ars */ }, 'i' },
11164 - { { 17 /* b4const */ }, 'i' },
11165 - { { 60 /* xt_wbr18_label */ }, 'i' }
11168 -static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
11169 - { { 4 /* ars */ }, 'i' },
11170 - { { 18 /* b4constu */ }, 'i' },
11171 - { { 60 /* xt_wbr18_label */ }, 'i' }
11174 -static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
11175 - { { 4 /* ars */ }, 'i' },
11176 - { { 67 /* bbi */ }, 'i' },
11177 - { { 60 /* xt_wbr18_label */ }, 'i' }
11180 -static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
11181 - { { 4 /* ars */ }, 'i' },
11182 - { { 6 /* art */ }, 'i' },
11183 - { { 60 /* xt_wbr18_label */ }, 'i' }
11186 -static xtensa_iclass_internal iclasses[] = {
11187 - { 0, 0 /* xt_iclass_excw */,
11189 - { 0, 0 /* xt_iclass_rfe */,
11190 - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
11191 - { 0, 0 /* xt_iclass_rfde */,
11192 - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
11193 - { 0, 0 /* xt_iclass_syscall */,
11195 - { 0, 0 /* xt_iclass_simcall */,
11197 - { 2, Iclass_xt_iclass_call12_args,
11198 - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
11199 - { 2, Iclass_xt_iclass_call8_args,
11200 - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
11201 - { 2, Iclass_xt_iclass_call4_args,
11202 - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
11203 - { 2, Iclass_xt_iclass_callx12_args,
11204 - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
11205 - { 2, Iclass_xt_iclass_callx8_args,
11206 - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
11207 - { 2, Iclass_xt_iclass_callx4_args,
11208 - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
11209 - { 3, Iclass_xt_iclass_entry_args,
11210 - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
11211 - { 2, Iclass_xt_iclass_movsp_args,
11212 - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
11213 - { 1, Iclass_xt_iclass_rotw_args,
11214 - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
11215 - { 1, Iclass_xt_iclass_retw_args,
11216 - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
11217 - { 0, 0 /* xt_iclass_rfwou */,
11218 - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
11219 - { 3, Iclass_xt_iclass_l32e_args,
11220 - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
11221 - { 3, Iclass_xt_iclass_s32e_args,
11222 - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
11223 - { 1, Iclass_xt_iclass_rsr_windowbase_args,
11224 - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
11225 - { 1, Iclass_xt_iclass_wsr_windowbase_args,
11226 - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
11227 - { 1, Iclass_xt_iclass_xsr_windowbase_args,
11228 - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
11229 - { 1, Iclass_xt_iclass_rsr_windowstart_args,
11230 - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
11231 - { 1, Iclass_xt_iclass_wsr_windowstart_args,
11232 - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
11233 - { 1, Iclass_xt_iclass_xsr_windowstart_args,
11234 - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
11235 - { 3, Iclass_xt_iclass_add_n_args,
11237 - { 3, Iclass_xt_iclass_addi_n_args,
11239 - { 2, Iclass_xt_iclass_bz6_args,
11241 - { 0, 0 /* xt_iclass_ill_n */,
11243 - { 3, Iclass_xt_iclass_loadi4_args,
11245 - { 2, Iclass_xt_iclass_mov_n_args,
11247 - { 2, Iclass_xt_iclass_movi_n_args,
11249 - { 0, 0 /* xt_iclass_nopn */,
11251 - { 1, Iclass_xt_iclass_retn_args,
11253 - { 3, Iclass_xt_iclass_storei4_args,
11255 - { 1, Iclass_rur_threadptr_args,
11256 - 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
11257 - { 1, Iclass_wur_threadptr_args,
11258 - 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
11259 - { 3, Iclass_xt_iclass_addi_args,
11261 - { 3, Iclass_xt_iclass_addmi_args,
11263 - { 3, Iclass_xt_iclass_addsub_args,
11265 - { 3, Iclass_xt_iclass_bit_args,
11267 - { 3, Iclass_xt_iclass_bsi8_args,
11269 - { 3, Iclass_xt_iclass_bsi8b_args,
11271 - { 3, Iclass_xt_iclass_bsi8u_args,
11273 - { 3, Iclass_xt_iclass_bst8_args,
11275 - { 2, Iclass_xt_iclass_bsz12_args,
11277 - { 2, Iclass_xt_iclass_call0_args,
11279 - { 2, Iclass_xt_iclass_callx0_args,
11281 - { 4, Iclass_xt_iclass_exti_args,
11283 - { 0, 0 /* xt_iclass_ill */,
11285 - { 1, Iclass_xt_iclass_jump_args,
11287 - { 1, Iclass_xt_iclass_jumpx_args,
11289 - { 3, Iclass_xt_iclass_l16ui_args,
11291 - { 3, Iclass_xt_iclass_l16si_args,
11293 - { 3, Iclass_xt_iclass_l32i_args,
11295 - { 2, Iclass_xt_iclass_l32r_args,
11296 - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
11297 - { 3, Iclass_xt_iclass_l8i_args,
11299 - { 2, Iclass_xt_iclass_loop_args,
11300 - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
11301 - { 2, Iclass_xt_iclass_loopz_args,
11302 - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
11303 - { 2, Iclass_xt_iclass_movi_args,
11305 - { 3, Iclass_xt_iclass_movz_args,
11307 - { 2, Iclass_xt_iclass_neg_args,
11309 - { 0, 0 /* xt_iclass_nop */,
11311 - { 1, Iclass_xt_iclass_return_args,
11313 - { 3, Iclass_xt_iclass_s16i_args,
11315 - { 3, Iclass_xt_iclass_s32i_args,
11317 - { 3, Iclass_xt_iclass_s8i_args,
11319 - { 1, Iclass_xt_iclass_sar_args,
11320 - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
11321 - { 1, Iclass_xt_iclass_sari_args,
11322 - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
11323 - { 2, Iclass_xt_iclass_shifts_args,
11324 - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
11325 - { 3, Iclass_xt_iclass_shiftst_args,
11326 - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
11327 - { 2, Iclass_xt_iclass_shiftt_args,
11328 - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
11329 - { 3, Iclass_xt_iclass_slli_args,
11331 - { 3, Iclass_xt_iclass_srai_args,
11333 - { 3, Iclass_xt_iclass_srli_args,
11335 - { 0, 0 /* xt_iclass_memw */,
11337 - { 0, 0 /* xt_iclass_extw */,
11339 - { 0, 0 /* xt_iclass_isync */,
11341 - { 0, 0 /* xt_iclass_sync */,
11342 - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
11343 - { 2, Iclass_xt_iclass_rsil_args,
11344 - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
11345 - { 1, Iclass_xt_iclass_rsr_lend_args,
11346 - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
11347 - { 1, Iclass_xt_iclass_wsr_lend_args,
11348 - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
11349 - { 1, Iclass_xt_iclass_xsr_lend_args,
11350 - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
11351 - { 1, Iclass_xt_iclass_rsr_lcount_args,
11352 - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
11353 - { 1, Iclass_xt_iclass_wsr_lcount_args,
11354 - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
11355 - { 1, Iclass_xt_iclass_xsr_lcount_args,
11356 - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
11357 - { 1, Iclass_xt_iclass_rsr_lbeg_args,
11358 - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
11359 - { 1, Iclass_xt_iclass_wsr_lbeg_args,
11360 - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
11361 - { 1, Iclass_xt_iclass_xsr_lbeg_args,
11362 - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
11363 - { 1, Iclass_xt_iclass_rsr_sar_args,
11364 - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
11365 - { 1, Iclass_xt_iclass_wsr_sar_args,
11366 - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
11367 - { 1, Iclass_xt_iclass_xsr_sar_args,
11368 - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
11369 - { 1, Iclass_xt_iclass_rsr_litbase_args,
11370 - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
11371 - { 1, Iclass_xt_iclass_wsr_litbase_args,
11372 - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
11373 - { 1, Iclass_xt_iclass_xsr_litbase_args,
11374 - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
11375 - { 1, Iclass_xt_iclass_rsr_176_args,
11376 - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
11377 - { 1, Iclass_xt_iclass_rsr_208_args,
11378 - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
11379 - { 1, Iclass_xt_iclass_rsr_ps_args,
11380 - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
11381 - { 1, Iclass_xt_iclass_wsr_ps_args,
11382 - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
11383 - { 1, Iclass_xt_iclass_xsr_ps_args,
11384 - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
11385 - { 1, Iclass_xt_iclass_rsr_epc1_args,
11386 - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
11387 - { 1, Iclass_xt_iclass_wsr_epc1_args,
11388 - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
11389 - { 1, Iclass_xt_iclass_xsr_epc1_args,
11390 - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
11391 - { 1, Iclass_xt_iclass_rsr_excsave1_args,
11392 - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
11393 - { 1, Iclass_xt_iclass_wsr_excsave1_args,
11394 - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
11395 - { 1, Iclass_xt_iclass_xsr_excsave1_args,
11396 - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
11397 - { 1, Iclass_xt_iclass_rsr_epc2_args,
11398 - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
11399 - { 1, Iclass_xt_iclass_wsr_epc2_args,
11400 - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
11401 - { 1, Iclass_xt_iclass_xsr_epc2_args,
11402 - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
11403 - { 1, Iclass_xt_iclass_rsr_excsave2_args,
11404 - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
11405 - { 1, Iclass_xt_iclass_wsr_excsave2_args,
11406 - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
11407 - { 1, Iclass_xt_iclass_xsr_excsave2_args,
11408 - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
11409 - { 1, Iclass_xt_iclass_rsr_epc3_args,
11410 - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
11411 - { 1, Iclass_xt_iclass_wsr_epc3_args,
11412 - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
11413 - { 1, Iclass_xt_iclass_xsr_epc3_args,
11414 - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
11415 - { 1, Iclass_xt_iclass_rsr_excsave3_args,
11416 - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
11417 - { 1, Iclass_xt_iclass_wsr_excsave3_args,
11418 - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
11419 - { 1, Iclass_xt_iclass_xsr_excsave3_args,
11420 - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
11421 - { 1, Iclass_xt_iclass_rsr_epc4_args,
11422 - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
11423 - { 1, Iclass_xt_iclass_wsr_epc4_args,
11424 - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
11425 - { 1, Iclass_xt_iclass_xsr_epc4_args,
11426 - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
11427 - { 1, Iclass_xt_iclass_rsr_excsave4_args,
11428 - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
11429 - { 1, Iclass_xt_iclass_wsr_excsave4_args,
11430 - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
11431 - { 1, Iclass_xt_iclass_xsr_excsave4_args,
11432 - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
11433 - { 1, Iclass_xt_iclass_rsr_epc5_args,
11434 - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
11435 - { 1, Iclass_xt_iclass_wsr_epc5_args,
11436 - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
11437 - { 1, Iclass_xt_iclass_xsr_epc5_args,
11438 - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
11439 - { 1, Iclass_xt_iclass_rsr_excsave5_args,
11440 - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
11441 - { 1, Iclass_xt_iclass_wsr_excsave5_args,
11442 - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
11443 - { 1, Iclass_xt_iclass_xsr_excsave5_args,
11444 - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
11445 - { 1, Iclass_xt_iclass_rsr_epc6_args,
11446 - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
11447 - { 1, Iclass_xt_iclass_wsr_epc6_args,
11448 - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
11449 - { 1, Iclass_xt_iclass_xsr_epc6_args,
11450 - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
11451 - { 1, Iclass_xt_iclass_rsr_excsave6_args,
11452 - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
11453 - { 1, Iclass_xt_iclass_wsr_excsave6_args,
11454 - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
11455 - { 1, Iclass_xt_iclass_xsr_excsave6_args,
11456 - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
11457 - { 1, Iclass_xt_iclass_rsr_epc7_args,
11458 - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
11459 - { 1, Iclass_xt_iclass_wsr_epc7_args,
11460 - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
11461 - { 1, Iclass_xt_iclass_xsr_epc7_args,
11462 - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
11463 - { 1, Iclass_xt_iclass_rsr_excsave7_args,
11464 - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
11465 - { 1, Iclass_xt_iclass_wsr_excsave7_args,
11466 - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
11467 - { 1, Iclass_xt_iclass_xsr_excsave7_args,
11468 - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
11469 - { 1, Iclass_xt_iclass_rsr_eps2_args,
11470 - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
11471 - { 1, Iclass_xt_iclass_wsr_eps2_args,
11472 - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
11473 - { 1, Iclass_xt_iclass_xsr_eps2_args,
11474 - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
11475 - { 1, Iclass_xt_iclass_rsr_eps3_args,
11476 - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
11477 - { 1, Iclass_xt_iclass_wsr_eps3_args,
11478 - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
11479 - { 1, Iclass_xt_iclass_xsr_eps3_args,
11480 - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
11481 - { 1, Iclass_xt_iclass_rsr_eps4_args,
11482 - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
11483 - { 1, Iclass_xt_iclass_wsr_eps4_args,
11484 - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
11485 - { 1, Iclass_xt_iclass_xsr_eps4_args,
11486 - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
11487 - { 1, Iclass_xt_iclass_rsr_eps5_args,
11488 - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
11489 - { 1, Iclass_xt_iclass_wsr_eps5_args,
11490 - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
11491 - { 1, Iclass_xt_iclass_xsr_eps5_args,
11492 - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
11493 - { 1, Iclass_xt_iclass_rsr_eps6_args,
11494 - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
11495 - { 1, Iclass_xt_iclass_wsr_eps6_args,
11496 - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
11497 - { 1, Iclass_xt_iclass_xsr_eps6_args,
11498 - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
11499 - { 1, Iclass_xt_iclass_rsr_eps7_args,
11500 - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
11501 - { 1, Iclass_xt_iclass_wsr_eps7_args,
11502 - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
11503 - { 1, Iclass_xt_iclass_xsr_eps7_args,
11504 - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
11505 - { 1, Iclass_xt_iclass_rsr_excvaddr_args,
11506 - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
11507 - { 1, Iclass_xt_iclass_wsr_excvaddr_args,
11508 - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
11509 - { 1, Iclass_xt_iclass_xsr_excvaddr_args,
11510 - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
11511 - { 1, Iclass_xt_iclass_rsr_depc_args,
11512 - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
11513 - { 1, Iclass_xt_iclass_wsr_depc_args,
11514 - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
11515 - { 1, Iclass_xt_iclass_xsr_depc_args,
11516 - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
11517 - { 1, Iclass_xt_iclass_rsr_exccause_args,
11518 - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
11519 - { 1, Iclass_xt_iclass_wsr_exccause_args,
11520 - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
11521 - { 1, Iclass_xt_iclass_xsr_exccause_args,
11522 - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
11523 - { 1, Iclass_xt_iclass_rsr_misc0_args,
11524 - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
11525 - { 1, Iclass_xt_iclass_wsr_misc0_args,
11526 - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
11527 - { 1, Iclass_xt_iclass_xsr_misc0_args,
11528 - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
11529 - { 1, Iclass_xt_iclass_rsr_misc1_args,
11530 - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
11531 - { 1, Iclass_xt_iclass_wsr_misc1_args,
11532 - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
11533 - { 1, Iclass_xt_iclass_xsr_misc1_args,
11534 - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
11535 - { 1, Iclass_xt_iclass_rsr_misc2_args,
11536 - 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
11537 - { 1, Iclass_xt_iclass_wsr_misc2_args,
11538 - 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
11539 - { 1, Iclass_xt_iclass_xsr_misc2_args,
11540 - 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
11541 - { 1, Iclass_xt_iclass_rsr_misc3_args,
11542 - 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
11543 - { 1, Iclass_xt_iclass_wsr_misc3_args,
11544 - 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
11545 - { 1, Iclass_xt_iclass_xsr_misc3_args,
11546 - 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
11547 - { 1, Iclass_xt_iclass_rsr_prid_args,
11548 - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
11549 - { 1, Iclass_xt_iclass_rsr_vecbase_args,
11550 - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
11551 - { 1, Iclass_xt_iclass_wsr_vecbase_args,
11552 - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
11553 - { 1, Iclass_xt_iclass_xsr_vecbase_args,
11554 - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
11555 - { 2, Iclass_xt_iclass_mac16_aa_args,
11556 - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
11557 - { 2, Iclass_xt_iclass_mac16_ad_args,
11558 - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
11559 - { 2, Iclass_xt_iclass_mac16_da_args,
11560 - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
11561 - { 2, Iclass_xt_iclass_mac16_dd_args,
11562 - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
11563 - { 2, Iclass_xt_iclass_mac16a_aa_args,
11564 - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
11565 - { 2, Iclass_xt_iclass_mac16a_ad_args,
11566 - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
11567 - { 2, Iclass_xt_iclass_mac16a_da_args,
11568 - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
11569 - { 2, Iclass_xt_iclass_mac16a_dd_args,
11570 - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
11571 - { 4, Iclass_xt_iclass_mac16al_da_args,
11572 - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
11573 - { 4, Iclass_xt_iclass_mac16al_dd_args,
11574 - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
11575 - { 2, Iclass_xt_iclass_mac16_l_args,
11577 - { 3, Iclass_xt_iclass_mul16_args,
11579 - { 2, Iclass_xt_iclass_rsr_m0_args,
11581 - { 2, Iclass_xt_iclass_wsr_m0_args,
11583 - { 2, Iclass_xt_iclass_xsr_m0_args,
11585 - { 2, Iclass_xt_iclass_rsr_m1_args,
11587 - { 2, Iclass_xt_iclass_wsr_m1_args,
11589 - { 2, Iclass_xt_iclass_xsr_m1_args,
11591 - { 2, Iclass_xt_iclass_rsr_m2_args,
11593 - { 2, Iclass_xt_iclass_wsr_m2_args,
11595 - { 2, Iclass_xt_iclass_xsr_m2_args,
11597 - { 2, Iclass_xt_iclass_rsr_m3_args,
11599 - { 2, Iclass_xt_iclass_wsr_m3_args,
11601 - { 2, Iclass_xt_iclass_xsr_m3_args,
11603 - { 1, Iclass_xt_iclass_rsr_acclo_args,
11604 - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
11605 - { 1, Iclass_xt_iclass_wsr_acclo_args,
11606 - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
11607 - { 1, Iclass_xt_iclass_xsr_acclo_args,
11608 - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
11609 - { 1, Iclass_xt_iclass_rsr_acchi_args,
11610 - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
11611 - { 1, Iclass_xt_iclass_wsr_acchi_args,
11612 - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
11613 - { 1, Iclass_xt_iclass_xsr_acchi_args,
11614 - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
11615 - { 1, Iclass_xt_iclass_rfi_args,
11616 - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
11617 - { 1, Iclass_xt_iclass_wait_args,
11618 - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
11619 - { 1, Iclass_xt_iclass_rsr_interrupt_args,
11620 - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
11621 - { 1, Iclass_xt_iclass_wsr_intset_args,
11622 - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
11623 - { 1, Iclass_xt_iclass_wsr_intclear_args,
11624 - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
11625 - { 1, Iclass_xt_iclass_rsr_intenable_args,
11626 - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
11627 - { 1, Iclass_xt_iclass_wsr_intenable_args,
11628 - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
11629 - { 1, Iclass_xt_iclass_xsr_intenable_args,
11630 - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
11631 - { 2, Iclass_xt_iclass_break_args,
11632 - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
11633 - { 1, Iclass_xt_iclass_break_n_args,
11634 - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
11635 - { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
11636 - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
11637 - { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
11638 - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
11639 - { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
11640 - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
11641 - { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
11642 - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
11643 - { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
11644 - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
11645 - { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
11646 - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
11647 - { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
11648 - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
11649 - { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
11650 - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
11651 - { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
11652 - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
11653 - { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
11654 - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
11655 - { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
11656 - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
11657 - { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
11658 - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
11659 - { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
11660 - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
11661 - { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
11662 - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
11663 - { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
11664 - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
11665 - { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
11666 - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
11667 - { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
11668 - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
11669 - { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
11670 - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
11671 - { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
11672 - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
11673 - { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
11674 - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
11675 - { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
11676 - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
11677 - { 1, Iclass_xt_iclass_rsr_debugcause_args,
11678 - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
11679 - { 1, Iclass_xt_iclass_wsr_debugcause_args,
11680 - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
11681 - { 1, Iclass_xt_iclass_xsr_debugcause_args,
11682 - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
11683 - { 1, Iclass_xt_iclass_rsr_icount_args,
11684 - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
11685 - { 1, Iclass_xt_iclass_wsr_icount_args,
11686 - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
11687 - { 1, Iclass_xt_iclass_xsr_icount_args,
11688 - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
11689 - { 1, Iclass_xt_iclass_rsr_icountlevel_args,
11690 - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
11691 - { 1, Iclass_xt_iclass_wsr_icountlevel_args,
11692 - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
11693 - { 1, Iclass_xt_iclass_xsr_icountlevel_args,
11694 - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
11695 - { 1, Iclass_xt_iclass_rsr_ddr_args,
11696 - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
11697 - { 1, Iclass_xt_iclass_wsr_ddr_args,
11698 - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
11699 - { 1, Iclass_xt_iclass_xsr_ddr_args,
11700 - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
11701 - { 1, Iclass_xt_iclass_rfdo_args,
11702 - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
11703 - { 0, 0 /* xt_iclass_rfdd */,
11704 - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
11705 - { 1, Iclass_xt_iclass_wsr_mmid_args,
11706 - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
11707 - { 3, Iclass_xt_iclass_bbool1_args,
11709 - { 2, Iclass_xt_iclass_bbool4_args,
11711 - { 2, Iclass_xt_iclass_bbool8_args,
11713 - { 2, Iclass_xt_iclass_bbranch_args,
11715 - { 3, Iclass_xt_iclass_bmove_args,
11717 - { 2, Iclass_xt_iclass_RSR_BR_args,
11719 - { 2, Iclass_xt_iclass_WSR_BR_args,
11721 - { 2, Iclass_xt_iclass_XSR_BR_args,
11723 - { 1, Iclass_xt_iclass_rsr_ccount_args,
11724 - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
11725 - { 1, Iclass_xt_iclass_wsr_ccount_args,
11726 - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
11727 - { 1, Iclass_xt_iclass_xsr_ccount_args,
11728 - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
11729 - { 1, Iclass_xt_iclass_rsr_ccompare0_args,
11730 - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
11731 - { 1, Iclass_xt_iclass_wsr_ccompare0_args,
11732 - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
11733 - { 1, Iclass_xt_iclass_xsr_ccompare0_args,
11734 - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
11735 - { 1, Iclass_xt_iclass_rsr_ccompare1_args,
11736 - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
11737 - { 1, Iclass_xt_iclass_wsr_ccompare1_args,
11738 - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
11739 - { 1, Iclass_xt_iclass_xsr_ccompare1_args,
11740 - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
11741 - { 1, Iclass_xt_iclass_rsr_ccompare2_args,
11742 - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
11743 - { 1, Iclass_xt_iclass_wsr_ccompare2_args,
11744 - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
11745 - { 1, Iclass_xt_iclass_xsr_ccompare2_args,
11746 - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
11747 - { 2, Iclass_xt_iclass_icache_args,
11749 - { 2, Iclass_xt_iclass_icache_lock_args,
11750 - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
11751 - { 2, Iclass_xt_iclass_icache_inv_args,
11752 - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
11753 - { 2, Iclass_xt_iclass_licx_args,
11754 - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
11755 - { 2, Iclass_xt_iclass_sicx_args,
11756 - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
11757 - { 2, Iclass_xt_iclass_dcache_args,
11759 - { 2, Iclass_xt_iclass_dcache_ind_args,
11760 - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
11761 - { 2, Iclass_xt_iclass_dcache_inv_args,
11762 - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
11763 - { 2, Iclass_xt_iclass_dpf_args,
11765 - { 2, Iclass_xt_iclass_dcache_lock_args,
11766 - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
11767 - { 2, Iclass_xt_iclass_sdct_args,
11768 - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
11769 - { 2, Iclass_xt_iclass_ldct_args,
11770 - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
11771 - { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
11772 - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
11773 - { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
11774 - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
11775 - { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
11776 - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
11777 - { 1, Iclass_xt_iclass_rsr_rasid_args,
11778 - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
11779 - { 1, Iclass_xt_iclass_wsr_rasid_args,
11780 - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
11781 - { 1, Iclass_xt_iclass_xsr_rasid_args,
11782 - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
11783 - { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
11784 - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
11785 - { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
11786 - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
11787 - { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
11788 - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
11789 - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
11790 - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
11791 - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
11792 - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
11793 - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
11794 - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
11795 - { 1, Iclass_xt_iclass_idtlb_args,
11796 - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
11797 - { 2, Iclass_xt_iclass_rdtlb_args,
11798 - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
11799 - { 2, Iclass_xt_iclass_wdtlb_args,
11800 - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
11801 - { 1, Iclass_xt_iclass_iitlb_args,
11802 - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
11803 - { 2, Iclass_xt_iclass_ritlb_args,
11804 - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
11805 - { 2, Iclass_xt_iclass_witlb_args,
11806 - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
11807 - { 0, 0 /* xt_iclass_ldpte */,
11808 - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
11809 - { 0, 0 /* xt_iclass_hwwitlba */,
11810 - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
11811 - { 0, 0 /* xt_iclass_hwwdtlba */,
11812 - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
11813 - { 1, Iclass_xt_iclass_rsr_cpenable_args,
11814 - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
11815 - { 1, Iclass_xt_iclass_wsr_cpenable_args,
11816 - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
11817 - { 1, Iclass_xt_iclass_xsr_cpenable_args,
11818 - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
11819 - { 3, Iclass_xt_iclass_clamp_args,
11821 - { 3, Iclass_xt_iclass_minmax_args,
11823 - { 2, Iclass_xt_iclass_nsa_args,
11825 - { 3, Iclass_xt_iclass_sx_args,
11827 - { 3, Iclass_xt_iclass_l32ai_args,
11829 - { 3, Iclass_xt_iclass_s32ri_args,
11831 - { 3, Iclass_xt_iclass_s32c1i_args,
11832 - 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
11833 - { 1, Iclass_xt_iclass_rsr_scompare1_args,
11834 - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
11835 - { 1, Iclass_xt_iclass_wsr_scompare1_args,
11836 - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
11837 - { 1, Iclass_xt_iclass_xsr_scompare1_args,
11838 - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
11839 - { 3, Iclass_xt_iclass_div_args,
11841 - { 3, Iclass_xt_mul32_args,
11843 - { 1, Iclass_rur_fcr_args,
11844 - 9, Iclass_rur_fcr_stateArgs, 0, 0 },
11845 - { 1, Iclass_wur_fcr_args,
11846 - 9, Iclass_wur_fcr_stateArgs, 0, 0 },
11847 - { 1, Iclass_rur_fsr_args,
11848 - 8, Iclass_rur_fsr_stateArgs, 0, 0 },
11849 - { 1, Iclass_wur_fsr_args,
11850 - 8, Iclass_wur_fsr_stateArgs, 0, 0 },
11851 - { 3, Iclass_fp_args,
11852 - 2, Iclass_fp_stateArgs, 0, 0 },
11853 - { 3, Iclass_fp_mac_args,
11854 - 2, Iclass_fp_mac_stateArgs, 0, 0 },
11855 - { 3, Iclass_fp_cmov_args,
11856 - 1, Iclass_fp_cmov_stateArgs, 0, 0 },
11857 - { 3, Iclass_fp_mov_args,
11858 - 1, Iclass_fp_mov_stateArgs, 0, 0 },
11859 - { 2, Iclass_fp_mov2_args,
11860 - 1, Iclass_fp_mov2_stateArgs, 0, 0 },
11861 - { 3, Iclass_fp_cmp_args,
11862 - 1, Iclass_fp_cmp_stateArgs, 0, 0 },
11863 - { 3, Iclass_fp_float_args,
11864 - 2, Iclass_fp_float_stateArgs, 0, 0 },
11865 - { 3, Iclass_fp_int_args,
11866 - 1, Iclass_fp_int_stateArgs, 0, 0 },
11867 - { 2, Iclass_fp_rfr_args,
11868 - 1, Iclass_fp_rfr_stateArgs, 0, 0 },
11869 - { 2, Iclass_fp_wfr_args,
11870 - 1, Iclass_fp_wfr_stateArgs, 0, 0 },
11871 - { 3, Iclass_fp_lsi_args,
11872 - 1, Iclass_fp_lsi_stateArgs, 0, 0 },
11873 - { 3, Iclass_fp_lsiu_args,
11874 - 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
11875 - { 3, Iclass_fp_lsx_args,
11876 - 1, Iclass_fp_lsx_stateArgs, 0, 0 },
11877 - { 3, Iclass_fp_lsxu_args,
11878 - 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
11879 - { 3, Iclass_fp_ssi_args,
11880 - 1, Iclass_fp_ssi_stateArgs, 0, 0 },
11881 - { 3, Iclass_fp_ssiu_args,
11882 - 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
11883 - { 3, Iclass_fp_ssx_args,
11884 - 1, Iclass_fp_ssx_stateArgs, 0, 0 },
11885 - { 3, Iclass_fp_ssxu_args,
11886 - 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
11887 - { 2, Iclass_xt_iclass_wb18_0_args,
11889 - { 3, Iclass_xt_iclass_wb18_1_args,
11891 - { 3, Iclass_xt_iclass_wb18_2_args,
11893 - { 3, Iclass_xt_iclass_wb18_3_args,
11895 - { 3, Iclass_xt_iclass_wb18_4_args,
11900 -/* Opcode encodings. */
11903 -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11905 - slotbuf[0] = 0x2080;
11909 -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
11911 - slotbuf[0] = 0x3000;
11915 -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
11917 - slotbuf[0] = 0x3200;
11921 -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11923 - slotbuf[0] = 0x5000;
11927 -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11929 - slotbuf[0] = 0x5100;
11933 -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11935 - slotbuf[0] = 0x35;
11939 -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11941 - slotbuf[0] = 0x25;
11945 -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11947 - slotbuf[0] = 0x15;
11951 -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11953 - slotbuf[0] = 0xf0;
11957 -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11959 - slotbuf[0] = 0xe0;
11963 -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11965 - slotbuf[0] = 0xd0;
11969 -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
11971 - slotbuf[0] = 0x36;
11975 -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
11977 - slotbuf[0] = 0x1000;
11981 -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11983 - slotbuf[0] = 0x408000;
11987 -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11989 - slotbuf[0] = 0x90;
11993 -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
11995 - slotbuf[0] = 0xf01d;
11999 -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12001 - slotbuf[0] = 0x3400;
12005 -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12007 - slotbuf[0] = 0x3500;
12011 -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12013 - slotbuf[0] = 0x90000;
12017 -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12019 - slotbuf[0] = 0x490000;
12023 -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12025 - slotbuf[0] = 0x34800;
12029 -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12031 - slotbuf[0] = 0x134800;
12035 -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12037 - slotbuf[0] = 0x614800;
12041 -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12043 - slotbuf[0] = 0x34900;
12047 -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12049 - slotbuf[0] = 0x134900;
12053 -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12055 - slotbuf[0] = 0x614900;
12059 -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12061 - slotbuf[0] = 0xa;
12065 -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12067 - slotbuf[0] = 0xb;
12071 -Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12073 - slotbuf[0] = 0x3000;
12077 -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12079 - slotbuf[0] = 0x8c;
12083 -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12085 - slotbuf[0] = 0xcc;
12089 -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12091 - slotbuf[0] = 0xf06d;
12095 -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12097 - slotbuf[0] = 0x8;
12101 -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12103 - slotbuf[0] = 0xd;
12107 -Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12109 - slotbuf[0] = 0x6000;
12113 -Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12115 - slotbuf[0] = 0xa3000;
12119 -Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12121 - slotbuf[0] = 0xc080;
12125 -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12127 - slotbuf[0] = 0xc;
12131 -Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12133 - slotbuf[0] = 0xc000;
12137 -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12139 - slotbuf[0] = 0xf03d;
12143 -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12145 - slotbuf[0] = 0xf00d;
12149 -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12151 - slotbuf[0] = 0x9;
12155 -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12157 - slotbuf[0] = 0xe30e70;
12161 -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12163 - slotbuf[0] = 0xf3e700;
12167 -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12169 - slotbuf[0] = 0xc002;
12173 -Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12175 - slotbuf[0] = 0x60000;
12179 -Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12181 - slotbuf[0] = 0x200c00;
12185 -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12187 - slotbuf[0] = 0xd002;
12191 -Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12193 - slotbuf[0] = 0x70000;
12197 -Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12199 - slotbuf[0] = 0x200d00;
12203 -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
12205 - slotbuf[0] = 0x800000;
12209 -Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12211 - slotbuf[0] = 0x92000;
12215 -Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12217 - slotbuf[0] = 0x2000;
12221 -Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12223 - slotbuf[0] = 0x80000;
12227 -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
12229 - slotbuf[0] = 0xc00000;
12233 -Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12235 - slotbuf[0] = 0xa8000;
12239 -Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12241 - slotbuf[0] = 0xa000;
12245 -Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12247 - slotbuf[0] = 0xc0000;
12251 -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12253 - slotbuf[0] = 0x900000;
12257 -Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12259 - slotbuf[0] = 0x94000;
12263 -Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12265 - slotbuf[0] = 0x4000;
12269 -Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12271 - slotbuf[0] = 0x90000;
12275 -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12277 - slotbuf[0] = 0xa00000;
12281 -Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12283 - slotbuf[0] = 0x98000;
12287 -Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12289 - slotbuf[0] = 0x5000;
12293 -Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12295 - slotbuf[0] = 0xa0000;
12299 -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12301 - slotbuf[0] = 0xb00000;
12305 -Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12307 - slotbuf[0] = 0x93000;
12311 -Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12313 - slotbuf[0] = 0xb0000;
12317 -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12319 - slotbuf[0] = 0xd00000;
12323 -Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12325 - slotbuf[0] = 0xd0000;
12329 -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12331 - slotbuf[0] = 0xe00000;
12335 -Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12337 - slotbuf[0] = 0xe0000;
12341 -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12343 - slotbuf[0] = 0xf00000;
12347 -Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12349 - slotbuf[0] = 0xf0000;
12353 -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
12355 - slotbuf[0] = 0x100000;
12359 -Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12361 - slotbuf[0] = 0x95000;
12365 -Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12367 - slotbuf[0] = 0x6000;
12371 -Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12373 - slotbuf[0] = 0x10000;
12377 -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
12379 - slotbuf[0] = 0x200000;
12383 -Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12385 - slotbuf[0] = 0x9e000;
12389 -Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12391 - slotbuf[0] = 0x7000;
12395 -Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12397 - slotbuf[0] = 0x20000;
12401 -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
12403 - slotbuf[0] = 0x300000;
12407 -Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12409 - slotbuf[0] = 0xb0000;
12413 -Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12415 - slotbuf[0] = 0xb000;
12419 -Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12421 - slotbuf[0] = 0x30000;
12425 -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12427 - slotbuf[0] = 0x26;
12431 -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12433 - slotbuf[0] = 0x66;
12437 -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12439 - slotbuf[0] = 0xe6;
12443 -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
12445 - slotbuf[0] = 0xa6;
12449 -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
12451 - slotbuf[0] = 0x6007;
12455 -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12457 - slotbuf[0] = 0xe007;
12461 -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12463 - slotbuf[0] = 0xf6;
12467 -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12469 - slotbuf[0] = 0xb6;
12473 -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
12475 - slotbuf[0] = 0x1007;
12479 -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
12481 - slotbuf[0] = 0x9007;
12485 -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
12487 - slotbuf[0] = 0xa007;
12491 -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12493 - slotbuf[0] = 0x2007;
12497 -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12499 - slotbuf[0] = 0xb007;
12503 -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12505 - slotbuf[0] = 0x3007;
12509 -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
12511 - slotbuf[0] = 0x8007;
12515 -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
12517 - slotbuf[0] = 0x7;
12521 -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
12523 - slotbuf[0] = 0x4007;
12527 -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
12529 - slotbuf[0] = 0xc007;
12533 -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12535 - slotbuf[0] = 0x5007;
12539 -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12541 - slotbuf[0] = 0xd007;
12545 -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12547 - slotbuf[0] = 0x16;
12551 -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12553 - slotbuf[0] = 0x56;
12557 -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12559 - slotbuf[0] = 0xd6;
12563 -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12565 - slotbuf[0] = 0x96;
12569 -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12571 - slotbuf[0] = 0x5;
12575 -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12577 - slotbuf[0] = 0xc0;
12581 -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12583 - slotbuf[0] = 0x40000;
12587 -Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12589 - slotbuf[0] = 0x40000;
12593 -Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12595 - slotbuf[0] = 0x4000;
12599 -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
12605 -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
12607 - slotbuf[0] = 0x6;
12611 -Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12613 - slotbuf[0] = 0xc0000;
12617 -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
12619 - slotbuf[0] = 0xa0;
12623 -Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12625 - slotbuf[0] = 0xa3010;
12629 -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12631 - slotbuf[0] = 0x1002;
12635 -Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12637 - slotbuf[0] = 0x200100;
12641 -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
12643 - slotbuf[0] = 0x9002;
12647 -Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12649 - slotbuf[0] = 0x200900;
12653 -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12655 - slotbuf[0] = 0x2002;
12659 -Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12661 - slotbuf[0] = 0x200200;
12665 -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
12667 - slotbuf[0] = 0x1;
12671 -Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12673 - slotbuf[0] = 0x100000;
12677 -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12679 - slotbuf[0] = 0x2;
12683 -Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12685 - slotbuf[0] = 0x200000;
12689 -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12691 - slotbuf[0] = 0x8076;
12695 -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12697 - slotbuf[0] = 0x9076;
12701 -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12703 - slotbuf[0] = 0xa076;
12707 -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12709 - slotbuf[0] = 0xa002;
12713 -Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12715 - slotbuf[0] = 0x80000;
12719 -Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12721 - slotbuf[0] = 0x200a00;
12725 -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12727 - slotbuf[0] = 0x830000;
12731 -Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12733 - slotbuf[0] = 0x96000;
12737 -Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12739 - slotbuf[0] = 0x83000;
12743 -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12745 - slotbuf[0] = 0x930000;
12749 -Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12751 - slotbuf[0] = 0x9a000;
12755 -Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12757 - slotbuf[0] = 0x93000;
12761 -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12763 - slotbuf[0] = 0xa30000;
12767 -Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12769 - slotbuf[0] = 0x99000;
12773 -Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12775 - slotbuf[0] = 0xa3000;
12779 -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12781 - slotbuf[0] = 0xb30000;
12785 -Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12787 - slotbuf[0] = 0x97000;
12791 -Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12793 - slotbuf[0] = 0xb3000;
12797 -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12799 - slotbuf[0] = 0x600000;
12803 -Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12805 - slotbuf[0] = 0xa5000;
12809 -Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12811 - slotbuf[0] = 0xd100;
12815 -Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12817 - slotbuf[0] = 0x60000;
12821 -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12823 - slotbuf[0] = 0x600100;
12827 -Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12829 - slotbuf[0] = 0xd000;
12833 -Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12835 - slotbuf[0] = 0x60010;
12839 -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12841 - slotbuf[0] = 0x20f0;
12845 -Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12847 - slotbuf[0] = 0xa3040;
12851 -Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12853 - slotbuf[0] = 0xc090;
12857 -Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12859 - slotbuf[0] = 0xc8000000;
12864 -Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12866 - slotbuf[0] = 0x20f;
12870 -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
12872 - slotbuf[0] = 0x80;
12876 -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12878 - slotbuf[0] = 0x5002;
12882 -Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12884 - slotbuf[0] = 0x200500;
12888 -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12890 - slotbuf[0] = 0x6002;
12894 -Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12896 - slotbuf[0] = 0x200600;
12900 -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12902 - slotbuf[0] = 0x4002;
12906 -Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12908 - slotbuf[0] = 0x200400;
12912 -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12914 - slotbuf[0] = 0x400000;
12918 -Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12920 - slotbuf[0] = 0x40000;
12924 -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12926 - slotbuf[0] = 0x401000;
12930 -Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12932 - slotbuf[0] = 0xa3020;
12936 -Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12938 - slotbuf[0] = 0x40100;
12942 -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
12944 - slotbuf[0] = 0x402000;
12948 -Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12950 - slotbuf[0] = 0x40200;
12954 -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
12956 - slotbuf[0] = 0x403000;
12960 -Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12962 - slotbuf[0] = 0x40300;
12966 -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12968 - slotbuf[0] = 0x404000;
12972 -Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12974 - slotbuf[0] = 0x40400;
12978 -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
12980 - slotbuf[0] = 0xa10000;
12984 -Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12986 - slotbuf[0] = 0xa6000;
12990 -Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12992 - slotbuf[0] = 0xa1000;
12996 -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
12998 - slotbuf[0] = 0x810000;
13002 -Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13004 - slotbuf[0] = 0xa2000;
13008 -Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13010 - slotbuf[0] = 0x81000;
13014 -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13016 - slotbuf[0] = 0x910000;
13020 -Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13022 - slotbuf[0] = 0xa5200;
13026 -Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13028 - slotbuf[0] = 0xd400;
13032 -Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13034 - slotbuf[0] = 0x91000;
13038 -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
13040 - slotbuf[0] = 0xb10000;
13044 -Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13046 - slotbuf[0] = 0xa5100;
13050 -Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13052 - slotbuf[0] = 0xd200;
13056 -Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13058 - slotbuf[0] = 0xb1000;
13062 -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13064 - slotbuf[0] = 0x10000;
13068 -Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13070 - slotbuf[0] = 0x90000;
13074 -Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13076 - slotbuf[0] = 0x1000;
13080 -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
13082 - slotbuf[0] = 0x210000;
13086 -Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13088 - slotbuf[0] = 0xa0000;
13092 -Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13094 - slotbuf[0] = 0xe000;
13098 -Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13100 - slotbuf[0] = 0x21000;
13104 -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13106 - slotbuf[0] = 0x410000;
13110 -Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13112 - slotbuf[0] = 0xa4000;
13116 -Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13118 - slotbuf[0] = 0x9000;
13122 -Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13124 - slotbuf[0] = 0x41000;
13128 -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13130 - slotbuf[0] = 0x20c0;
13134 -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13136 - slotbuf[0] = 0x20d0;
13140 -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13142 - slotbuf[0] = 0x2000;
13146 -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13148 - slotbuf[0] = 0x2010;
13152 -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13154 - slotbuf[0] = 0x2020;
13158 -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13160 - slotbuf[0] = 0x2030;
13164 -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
13166 - slotbuf[0] = 0x6000;
13170 -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13172 - slotbuf[0] = 0x30100;
13176 -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13178 - slotbuf[0] = 0x130100;
13182 -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13184 - slotbuf[0] = 0x610100;
13188 -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13190 - slotbuf[0] = 0x30200;
13194 -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13196 - slotbuf[0] = 0x130200;
13200 -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13202 - slotbuf[0] = 0x610200;
13206 -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13208 - slotbuf[0] = 0x30000;
13212 -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13214 - slotbuf[0] = 0x130000;
13218 -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13220 - slotbuf[0] = 0x610000;
13224 -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13226 - slotbuf[0] = 0x30300;
13230 -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13232 - slotbuf[0] = 0x130300;
13236 -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13238 - slotbuf[0] = 0x610300;
13242 -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13244 - slotbuf[0] = 0x30500;
13248 -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13250 - slotbuf[0] = 0x130500;
13254 -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13256 - slotbuf[0] = 0x610500;
13260 -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
13262 - slotbuf[0] = 0x3b000;
13266 -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
13268 - slotbuf[0] = 0x3d000;
13272 -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13274 - slotbuf[0] = 0x3e600;
13278 -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13280 - slotbuf[0] = 0x13e600;
13284 -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13286 - slotbuf[0] = 0x61e600;
13290 -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13292 - slotbuf[0] = 0x3b100;
13296 -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13298 - slotbuf[0] = 0x13b100;
13302 -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13304 - slotbuf[0] = 0x61b100;
13308 -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13310 - slotbuf[0] = 0x3d100;
13314 -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13316 - slotbuf[0] = 0x13d100;
13320 -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13322 - slotbuf[0] = 0x61d100;
13326 -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13328 - slotbuf[0] = 0x3b200;
13332 -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13334 - slotbuf[0] = 0x13b200;
13338 -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13340 - slotbuf[0] = 0x61b200;
13344 -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13346 - slotbuf[0] = 0x3d200;
13350 -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13352 - slotbuf[0] = 0x13d200;
13356 -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13358 - slotbuf[0] = 0x61d200;
13362 -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13364 - slotbuf[0] = 0x3b300;
13368 -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13370 - slotbuf[0] = 0x13b300;
13374 -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13376 - slotbuf[0] = 0x61b300;
13380 -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13382 - slotbuf[0] = 0x3d300;
13386 -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13388 - slotbuf[0] = 0x13d300;
13392 -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13394 - slotbuf[0] = 0x61d300;
13398 -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13400 - slotbuf[0] = 0x3b400;
13404 -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13406 - slotbuf[0] = 0x13b400;
13410 -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13412 - slotbuf[0] = 0x61b400;
13416 -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13418 - slotbuf[0] = 0x3d400;
13422 -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13424 - slotbuf[0] = 0x13d400;
13428 -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13430 - slotbuf[0] = 0x61d400;
13434 -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13436 - slotbuf[0] = 0x3b500;
13440 -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13442 - slotbuf[0] = 0x13b500;
13446 -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13448 - slotbuf[0] = 0x61b500;
13452 -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13454 - slotbuf[0] = 0x3d500;
13458 -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13460 - slotbuf[0] = 0x13d500;
13464 -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13466 - slotbuf[0] = 0x61d500;
13470 -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13472 - slotbuf[0] = 0x3b600;
13476 -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13478 - slotbuf[0] = 0x13b600;
13482 -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13484 - slotbuf[0] = 0x61b600;
13488 -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13490 - slotbuf[0] = 0x3d600;
13494 -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13496 - slotbuf[0] = 0x13d600;
13500 -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13502 - slotbuf[0] = 0x61d600;
13506 -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13508 - slotbuf[0] = 0x3b700;
13512 -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13514 - slotbuf[0] = 0x13b700;
13518 -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13520 - slotbuf[0] = 0x61b700;
13524 -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13526 - slotbuf[0] = 0x3d700;
13530 -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13532 - slotbuf[0] = 0x13d700;
13536 -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13538 - slotbuf[0] = 0x61d700;
13542 -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13544 - slotbuf[0] = 0x3c200;
13548 -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13550 - slotbuf[0] = 0x13c200;
13554 -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13556 - slotbuf[0] = 0x61c200;
13560 -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13562 - slotbuf[0] = 0x3c300;
13566 -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13568 - slotbuf[0] = 0x13c300;
13572 -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13574 - slotbuf[0] = 0x61c300;
13578 -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13580 - slotbuf[0] = 0x3c400;
13584 -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13586 - slotbuf[0] = 0x13c400;
13590 -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13592 - slotbuf[0] = 0x61c400;
13596 -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13598 - slotbuf[0] = 0x3c500;
13602 -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13604 - slotbuf[0] = 0x13c500;
13608 -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13610 - slotbuf[0] = 0x61c500;
13614 -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13616 - slotbuf[0] = 0x3c600;
13620 -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13622 - slotbuf[0] = 0x13c600;
13626 -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13628 - slotbuf[0] = 0x61c600;
13632 -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13634 - slotbuf[0] = 0x3c700;
13638 -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13640 - slotbuf[0] = 0x13c700;
13644 -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13646 - slotbuf[0] = 0x61c700;
13650 -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13652 - slotbuf[0] = 0x3ee00;
13656 -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13658 - slotbuf[0] = 0x13ee00;
13662 -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13664 - slotbuf[0] = 0x61ee00;
13668 -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13670 - slotbuf[0] = 0x3c000;
13674 -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13676 - slotbuf[0] = 0x13c000;
13680 -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13682 - slotbuf[0] = 0x61c000;
13686 -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13688 - slotbuf[0] = 0x3e800;
13692 -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13694 - slotbuf[0] = 0x13e800;
13698 -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13700 - slotbuf[0] = 0x61e800;
13704 -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13706 - slotbuf[0] = 0x3f400;
13710 -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13712 - slotbuf[0] = 0x13f400;
13716 -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13718 - slotbuf[0] = 0x61f400;
13722 -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13724 - slotbuf[0] = 0x3f500;
13728 -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13730 - slotbuf[0] = 0x13f500;
13734 -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13736 - slotbuf[0] = 0x61f500;
13740 -Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13742 - slotbuf[0] = 0x3f600;
13746 -Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13748 - slotbuf[0] = 0x13f600;
13752 -Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13754 - slotbuf[0] = 0x61f600;
13758 -Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13760 - slotbuf[0] = 0x3f700;
13764 -Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13766 - slotbuf[0] = 0x13f700;
13770 -Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13772 - slotbuf[0] = 0x61f700;
13776 -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
13778 - slotbuf[0] = 0x3eb00;
13782 -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13784 - slotbuf[0] = 0x3e700;
13788 -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13790 - slotbuf[0] = 0x13e700;
13794 -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13796 - slotbuf[0] = 0x61e700;
13800 -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13802 - slotbuf[0] = 0x740004;
13806 -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13808 - slotbuf[0] = 0x750004;
13812 -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13814 - slotbuf[0] = 0x760004;
13818 -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13820 - slotbuf[0] = 0x770004;
13824 -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13826 - slotbuf[0] = 0x700004;
13830 -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13832 - slotbuf[0] = 0x710004;
13836 -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13838 - slotbuf[0] = 0x720004;
13842 -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13844 - slotbuf[0] = 0x730004;
13848 -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13850 - slotbuf[0] = 0x340004;
13854 -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13856 - slotbuf[0] = 0x350004;
13860 -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13862 - slotbuf[0] = 0x360004;
13866 -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13868 - slotbuf[0] = 0x370004;
13872 -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13874 - slotbuf[0] = 0x640004;
13878 -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13880 - slotbuf[0] = 0x650004;
13884 -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13886 - slotbuf[0] = 0x660004;
13890 -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13892 - slotbuf[0] = 0x670004;
13896 -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13898 - slotbuf[0] = 0x240004;
13902 -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13904 - slotbuf[0] = 0x250004;
13908 -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13910 - slotbuf[0] = 0x260004;
13914 -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13916 - slotbuf[0] = 0x270004;
13920 -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13922 - slotbuf[0] = 0x780004;
13926 -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13928 - slotbuf[0] = 0x790004;
13932 -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13934 - slotbuf[0] = 0x7a0004;
13938 -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13940 - slotbuf[0] = 0x7b0004;
13944 -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13946 - slotbuf[0] = 0x7c0004;
13950 -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13952 - slotbuf[0] = 0x7d0004;
13956 -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13958 - slotbuf[0] = 0x7e0004;
13962 -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13964 - slotbuf[0] = 0x7f0004;
13968 -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13970 - slotbuf[0] = 0x380004;
13974 -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13976 - slotbuf[0] = 0x390004;
13980 -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13982 - slotbuf[0] = 0x3a0004;
13986 -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13988 - slotbuf[0] = 0x3b0004;
13992 -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13994 - slotbuf[0] = 0x3c0004;
13998 -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14000 - slotbuf[0] = 0x3d0004;
14004 -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14006 - slotbuf[0] = 0x3e0004;
14010 -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14012 - slotbuf[0] = 0x3f0004;
14016 -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14018 - slotbuf[0] = 0x680004;
14022 -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14024 - slotbuf[0] = 0x690004;
14028 -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14030 - slotbuf[0] = 0x6a0004;
14034 -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14036 - slotbuf[0] = 0x6b0004;
14040 -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14042 - slotbuf[0] = 0x6c0004;
14046 -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14048 - slotbuf[0] = 0x6d0004;
14052 -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14054 - slotbuf[0] = 0x6e0004;
14058 -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14060 - slotbuf[0] = 0x6f0004;
14064 -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14066 - slotbuf[0] = 0x280004;
14070 -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14072 - slotbuf[0] = 0x290004;
14076 -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14078 - slotbuf[0] = 0x2a0004;
14082 -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14084 - slotbuf[0] = 0x2b0004;
14088 -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14090 - slotbuf[0] = 0x2c0004;
14094 -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14096 - slotbuf[0] = 0x2d0004;
14100 -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14102 - slotbuf[0] = 0x2e0004;
14106 -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14108 - slotbuf[0] = 0x2f0004;
14112 -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14114 - slotbuf[0] = 0x580004;
14118 -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14120 - slotbuf[0] = 0x480004;
14124 -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14126 - slotbuf[0] = 0x590004;
14130 -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14132 - slotbuf[0] = 0x490004;
14136 -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14138 - slotbuf[0] = 0x5a0004;
14142 -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14144 - slotbuf[0] = 0x4a0004;
14148 -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14150 - slotbuf[0] = 0x5b0004;
14154 -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14156 - slotbuf[0] = 0x4b0004;
14160 -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14162 - slotbuf[0] = 0x180004;
14166 -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14168 - slotbuf[0] = 0x80004;
14172 -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14174 - slotbuf[0] = 0x190004;
14178 -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14180 - slotbuf[0] = 0x90004;
14184 -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14186 - slotbuf[0] = 0x1a0004;
14190 -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14192 - slotbuf[0] = 0xa0004;
14196 -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14198 - slotbuf[0] = 0x1b0004;
14202 -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14204 - slotbuf[0] = 0xb0004;
14208 -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14210 - slotbuf[0] = 0x900004;
14214 -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14216 - slotbuf[0] = 0x800004;
14220 -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
14222 - slotbuf[0] = 0xc10000;
14226 -Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14228 - slotbuf[0] = 0x9b000;
14232 -Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14234 - slotbuf[0] = 0xc1000;
14238 -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
14240 - slotbuf[0] = 0xd10000;
14244 -Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14246 - slotbuf[0] = 0x9c000;
14250 -Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14252 - slotbuf[0] = 0xd1000;
14256 -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14258 - slotbuf[0] = 0x32000;
14262 -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14264 - slotbuf[0] = 0x132000;
14268 -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14270 - slotbuf[0] = 0x612000;
14274 -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14276 - slotbuf[0] = 0x32100;
14280 -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14282 - slotbuf[0] = 0x132100;
14286 -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14288 - slotbuf[0] = 0x612100;
14292 -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14294 - slotbuf[0] = 0x32200;
14298 -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14300 - slotbuf[0] = 0x132200;
14304 -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14306 - slotbuf[0] = 0x612200;
14310 -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14312 - slotbuf[0] = 0x32300;
14316 -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14318 - slotbuf[0] = 0x132300;
14322 -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14324 - slotbuf[0] = 0x612300;
14328 -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14330 - slotbuf[0] = 0x31000;
14334 -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14336 - slotbuf[0] = 0x131000;
14340 -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14342 - slotbuf[0] = 0x611000;
14346 -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14348 - slotbuf[0] = 0x31100;
14352 -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14354 - slotbuf[0] = 0x131100;
14358 -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14360 - slotbuf[0] = 0x611100;
14364 -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14366 - slotbuf[0] = 0x3010;
14370 -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
14372 - slotbuf[0] = 0x7000;
14376 -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14378 - slotbuf[0] = 0x3e200;
14382 -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
14384 - slotbuf[0] = 0x13e200;
14388 -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
14390 - slotbuf[0] = 0x13e300;
14394 -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14396 - slotbuf[0] = 0x3e400;
14400 -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14402 - slotbuf[0] = 0x13e400;
14406 -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14408 - slotbuf[0] = 0x61e400;
14412 -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
14414 - slotbuf[0] = 0x4000;
14418 -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
14420 - slotbuf[0] = 0xf02d;
14424 -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14426 - slotbuf[0] = 0x39000;
14430 -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14432 - slotbuf[0] = 0x139000;
14436 -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14438 - slotbuf[0] = 0x619000;
14442 -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14444 - slotbuf[0] = 0x3a000;
14448 -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14450 - slotbuf[0] = 0x13a000;
14454 -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14456 - slotbuf[0] = 0x61a000;
14460 -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14462 - slotbuf[0] = 0x39100;
14466 -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14468 - slotbuf[0] = 0x139100;
14472 -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14474 - slotbuf[0] = 0x619100;
14478 -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14480 - slotbuf[0] = 0x3a100;
14484 -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14486 - slotbuf[0] = 0x13a100;
14490 -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14492 - slotbuf[0] = 0x61a100;
14496 -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14498 - slotbuf[0] = 0x38000;
14502 -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14504 - slotbuf[0] = 0x138000;
14508 -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14510 - slotbuf[0] = 0x618000;
14514 -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14516 - slotbuf[0] = 0x38100;
14520 -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14522 - slotbuf[0] = 0x138100;
14526 -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14528 - slotbuf[0] = 0x618100;
14532 -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14534 - slotbuf[0] = 0x36000;
14538 -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14540 - slotbuf[0] = 0x136000;
14544 -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14546 - slotbuf[0] = 0x616000;
14550 -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14552 - slotbuf[0] = 0x3e900;
14556 -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14558 - slotbuf[0] = 0x13e900;
14562 -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14564 - slotbuf[0] = 0x61e900;
14568 -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14570 - slotbuf[0] = 0x3ec00;
14574 -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14576 - slotbuf[0] = 0x13ec00;
14580 -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14582 - slotbuf[0] = 0x61ec00;
14586 -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14588 - slotbuf[0] = 0x3ed00;
14592 -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14594 - slotbuf[0] = 0x13ed00;
14598 -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14600 - slotbuf[0] = 0x61ed00;
14604 -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14606 - slotbuf[0] = 0x36800;
14610 -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14612 - slotbuf[0] = 0x136800;
14616 -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14618 - slotbuf[0] = 0x616800;
14622 -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14624 - slotbuf[0] = 0xf1e000;
14628 -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
14630 - slotbuf[0] = 0xf1e010;
14634 -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14636 - slotbuf[0] = 0x135900;
14640 -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14642 - slotbuf[0] = 0x20000;
14646 -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14648 - slotbuf[0] = 0x120000;
14652 -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14654 - slotbuf[0] = 0x220000;
14658 -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14660 - slotbuf[0] = 0x320000;
14664 -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14666 - slotbuf[0] = 0x420000;
14670 -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14672 - slotbuf[0] = 0x8000;
14676 -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14678 - slotbuf[0] = 0x9000;
14682 -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14684 - slotbuf[0] = 0xa000;
14688 -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14690 - slotbuf[0] = 0xb000;
14694 -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14696 - slotbuf[0] = 0x76;
14700 -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14702 - slotbuf[0] = 0x1076;
14706 -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14708 - slotbuf[0] = 0xc30000;
14712 -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14714 - slotbuf[0] = 0xd30000;
14718 -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14720 - slotbuf[0] = 0x30400;
14724 -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14726 - slotbuf[0] = 0x130400;
14730 -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14732 - slotbuf[0] = 0x610400;
14736 -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14738 - slotbuf[0] = 0x3ea00;
14742 -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14744 - slotbuf[0] = 0x13ea00;
14748 -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14750 - slotbuf[0] = 0x61ea00;
14754 -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14756 - slotbuf[0] = 0x3f000;
14760 -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14762 - slotbuf[0] = 0x13f000;
14766 -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14768 - slotbuf[0] = 0x61f000;
14772 -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14774 - slotbuf[0] = 0x3f100;
14778 -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14780 - slotbuf[0] = 0x13f100;
14784 -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14786 - slotbuf[0] = 0x61f100;
14790 -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14792 - slotbuf[0] = 0x3f200;
14796 -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14798 - slotbuf[0] = 0x13f200;
14802 -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14804 - slotbuf[0] = 0x61f200;
14808 -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14810 - slotbuf[0] = 0x70c2;
14814 -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14816 - slotbuf[0] = 0x70e2;
14820 -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14822 - slotbuf[0] = 0x70d2;
14826 -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14828 - slotbuf[0] = 0x270d2;
14832 -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14834 - slotbuf[0] = 0x370d2;
14838 -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14840 - slotbuf[0] = 0x70f2;
14844 -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14846 - slotbuf[0] = 0xf10000;
14850 -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14852 - slotbuf[0] = 0xf12000;
14856 -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14858 - slotbuf[0] = 0xf11000;
14862 -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14864 - slotbuf[0] = 0xf13000;
14868 -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14870 - slotbuf[0] = 0x7042;
14874 -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14876 - slotbuf[0] = 0x7052;
14880 -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14882 - slotbuf[0] = 0x47082;
14886 -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14888 - slotbuf[0] = 0x57082;
14892 -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14894 - slotbuf[0] = 0x7062;
14898 -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14900 - slotbuf[0] = 0x7072;
14904 -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14906 - slotbuf[0] = 0x7002;
14910 -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14912 - slotbuf[0] = 0x7012;
14916 -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
14918 - slotbuf[0] = 0x7022;
14922 -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14924 - slotbuf[0] = 0x7032;
14928 -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14930 - slotbuf[0] = 0x7082;
14934 -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14936 - slotbuf[0] = 0x27082;
14940 -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14942 - slotbuf[0] = 0x37082;
14946 -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14948 - slotbuf[0] = 0xf19000;
14952 -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14954 - slotbuf[0] = 0xf18000;
14958 -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14960 - slotbuf[0] = 0x135300;
14964 -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14966 - slotbuf[0] = 0x35300;
14970 -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14972 - slotbuf[0] = 0x615300;
14976 -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14978 - slotbuf[0] = 0x35a00;
14982 -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14984 - slotbuf[0] = 0x135a00;
14988 -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14990 - slotbuf[0] = 0x615a00;
14994 -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
14996 - slotbuf[0] = 0x35b00;
15000 -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15002 - slotbuf[0] = 0x135b00;
15006 -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15008 - slotbuf[0] = 0x615b00;
15012 -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15014 - slotbuf[0] = 0x35c00;
15018 -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15020 - slotbuf[0] = 0x135c00;
15024 -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15026 - slotbuf[0] = 0x615c00;
15030 -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15032 - slotbuf[0] = 0x50c000;
15036 -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15038 - slotbuf[0] = 0x50d000;
15042 -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15044 - slotbuf[0] = 0x50b000;
15048 -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15050 - slotbuf[0] = 0x50f000;
15054 -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15056 - slotbuf[0] = 0x50e000;
15060 -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15062 - slotbuf[0] = 0x504000;
15066 -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15068 - slotbuf[0] = 0x505000;
15072 -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15074 - slotbuf[0] = 0x503000;
15078 -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15080 - slotbuf[0] = 0x507000;
15084 -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15086 - slotbuf[0] = 0x506000;
15090 -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
15092 - slotbuf[0] = 0xf1f000;
15096 -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15098 - slotbuf[0] = 0x501000;
15102 -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15104 - slotbuf[0] = 0x509000;
15108 -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15110 - slotbuf[0] = 0x3e000;
15114 -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15116 - slotbuf[0] = 0x13e000;
15120 -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15122 - slotbuf[0] = 0x61e000;
15126 -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
15128 - slotbuf[0] = 0x330000;
15132 -Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15134 - slotbuf[0] = 0x33000;
15138 -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
15140 - slotbuf[0] = 0x430000;
15144 -Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15146 - slotbuf[0] = 0x43000;
15150 -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
15152 - slotbuf[0] = 0x530000;
15156 -Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15158 - slotbuf[0] = 0x53000;
15162 -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15164 - slotbuf[0] = 0x630000;
15168 -Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15170 - slotbuf[0] = 0x63000;
15174 -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15176 - slotbuf[0] = 0x730000;
15180 -Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15182 - slotbuf[0] = 0x73000;
15186 -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
15188 - slotbuf[0] = 0x40e000;
15192 -Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15194 - slotbuf[0] = 0x40e00;
15198 -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
15200 - slotbuf[0] = 0x40f000;
15204 -Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15206 - slotbuf[0] = 0x40f00;
15210 -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
15212 - slotbuf[0] = 0x230000;
15216 -Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15218 - slotbuf[0] = 0x9f000;
15222 -Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
15224 - slotbuf[0] = 0x8000;
15228 -Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15230 - slotbuf[0] = 0x23000;
15234 -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
15236 - slotbuf[0] = 0xb002;
15240 -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
15242 - slotbuf[0] = 0xf002;
15246 -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
15248 - slotbuf[0] = 0xe002;
15252 -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15254 - slotbuf[0] = 0x30c00;
15258 -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15260 - slotbuf[0] = 0x130c00;
15264 -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15266 - slotbuf[0] = 0x610c00;
15270 -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
15272 - slotbuf[0] = 0xc20000;
15276 -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
15278 - slotbuf[0] = 0xd20000;
15282 -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15284 - slotbuf[0] = 0xe20000;
15288 -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
15290 - slotbuf[0] = 0xf20000;
15294 -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
15296 - slotbuf[0] = 0x820000;
15300 -Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15302 - slotbuf[0] = 0x9d000;
15306 -Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15308 - slotbuf[0] = 0x82000;
15312 -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15314 - slotbuf[0] = 0xa20000;
15318 -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15320 - slotbuf[0] = 0xb20000;
15324 -Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15326 - slotbuf[0] = 0xe30e80;
15330 -Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15332 - slotbuf[0] = 0xf3e800;
15336 -Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15338 - slotbuf[0] = 0xe30e90;
15342 -Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15344 - slotbuf[0] = 0xf3e900;
15348 -Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15350 - slotbuf[0] = 0xa0000;
15354 -Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15356 - slotbuf[0] = 0x1a0000;
15360 -Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15362 - slotbuf[0] = 0x2a0000;
15366 -Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15368 - slotbuf[0] = 0x4a0000;
15372 -Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15374 - slotbuf[0] = 0x5a0000;
15378 -Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15380 - slotbuf[0] = 0xcb0000;
15384 -Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15386 - slotbuf[0] = 0xdb0000;
15390 -Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15392 - slotbuf[0] = 0x8b0000;
15396 -Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15398 - slotbuf[0] = 0x9b0000;
15402 -Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15404 - slotbuf[0] = 0xab0000;
15408 -Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15410 - slotbuf[0] = 0xbb0000;
15414 -Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15416 - slotbuf[0] = 0xfa0010;
15420 -Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15422 - slotbuf[0] = 0xfa0000;
15426 -Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15428 - slotbuf[0] = 0xfa0060;
15432 -Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15434 - slotbuf[0] = 0x1b0000;
15438 -Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15440 - slotbuf[0] = 0x2b0000;
15444 -Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15446 - slotbuf[0] = 0x3b0000;
15450 -Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15452 - slotbuf[0] = 0x4b0000;
15456 -Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15458 - slotbuf[0] = 0x5b0000;
15462 -Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15464 - slotbuf[0] = 0x6b0000;
15468 -Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15470 - slotbuf[0] = 0x7b0000;
15474 -Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15476 - slotbuf[0] = 0xca0000;
15480 -Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15482 - slotbuf[0] = 0xda0000;
15486 -Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15488 - slotbuf[0] = 0x8a0000;
15492 -Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15494 - slotbuf[0] = 0xba0000;
15498 -Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15500 - slotbuf[0] = 0xaa0000;
15504 -Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15506 - slotbuf[0] = 0x9a0000;
15510 -Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15512 - slotbuf[0] = 0xea0000;
15516 -Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15518 - slotbuf[0] = 0xfa0040;
15522 -Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15524 - slotbuf[0] = 0xfa0050;
15528 -Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15530 - slotbuf[0] = 0x3;
15534 -Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15536 - slotbuf[0] = 0x8003;
15540 -Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15542 - slotbuf[0] = 0x80000;
15546 -Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15548 - slotbuf[0] = 0x180000;
15552 -Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15554 - slotbuf[0] = 0x4003;
15558 -Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15560 - slotbuf[0] = 0xc003;
15564 -Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15566 - slotbuf[0] = 0x480000;
15570 -Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15572 - slotbuf[0] = 0x580000;
15576 -Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15578 - slotbuf[0] = 0xa8000000;
15583 -Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15585 - slotbuf[0] = 0xc0000000;
15590 -Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15592 - slotbuf[0] = 0xb0000000;
15597 -Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15599 - slotbuf[0] = 0xb8000000;
15604 -Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15606 - slotbuf[0] = 0x40000000;
15611 -Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15613 - slotbuf[0] = 0x98000000;
15618 -Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15620 - slotbuf[0] = 0x50000000;
15625 -Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15627 - slotbuf[0] = 0x70000000;
15632 -Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15634 - slotbuf[0] = 0x60000000;
15639 -Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15641 - slotbuf[0] = 0x80000000;
15646 -Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15648 - slotbuf[0] = 0x8000000;
15653 -Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15655 - slotbuf[0] = 0x10000000;
15660 -Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15662 - slotbuf[0] = 0x38000000;
15667 -Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15669 - slotbuf[0] = 0x90000000;
15674 -Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15676 - slotbuf[0] = 0x48000000;
15681 -Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15683 - slotbuf[0] = 0x68000000;
15688 -Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15690 - slotbuf[0] = 0x58000000;
15695 -Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15697 - slotbuf[0] = 0x78000000;
15702 -Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15704 - slotbuf[0] = 0x20000000;
15709 -Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15711 - slotbuf[0] = 0xa0000000;
15716 -Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15718 - slotbuf[0] = 0x18000000;
15723 -Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15725 - slotbuf[0] = 0x88000000;
15730 -Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15732 - slotbuf[0] = 0x28000000;
15737 -Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15739 - slotbuf[0] = 0x30000000;
15743 -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
15744 - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15747 -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
15748 - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15751 -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
15752 - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15755 -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
15756 - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15759 -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
15760 - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15763 -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
15764 - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15767 -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
15768 - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15771 -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
15772 - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15775 -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
15776 - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15779 -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
15780 - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15783 -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
15784 - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15787 -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
15788 - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15791 -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
15792 - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15795 -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
15796 - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15799 -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
15800 - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15803 -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
15804 - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15807 -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
15808 - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15811 -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
15812 - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15815 -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
15816 - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15819 -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
15820 - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15823 -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
15824 - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15827 -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
15828 - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15831 -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
15832 - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15835 -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
15836 - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15839 -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
15840 - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15843 -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
15844 - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15847 -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
15848 - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15851 -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
15852 - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
15855 -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
15856 - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15859 -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
15860 - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15863 -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
15864 - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15867 -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
15868 - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15871 -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
15872 - 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
15875 -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
15876 - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
15879 -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
15880 - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15883 -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
15884 - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15887 -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
15888 - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15891 -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
15892 - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15895 -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
15896 - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15899 -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
15900 - Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
15903 -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
15904 - Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
15907 -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
15908 - Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
15911 -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
15912 - Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
15915 -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
15916 - Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
15919 -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
15920 - Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
15923 -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
15924 - Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
15927 -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
15928 - Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
15931 -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
15932 - Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
15935 -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
15936 - Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
15939 -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
15940 - Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
15943 -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
15944 - Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
15947 -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
15948 - Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
15951 -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
15952 - Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15955 -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
15956 - Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15959 -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
15960 - Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15963 -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
15964 - Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15967 -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
15968 - Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15971 -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
15972 - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15975 -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
15976 - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15979 -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
15980 - Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15983 -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
15984 - Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15987 -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
15988 - Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15991 -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
15992 - Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15995 -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
15996 - Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15999 -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
16000 - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16003 -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
16004 - Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16007 -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
16008 - Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16011 -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
16012 - Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16015 -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
16016 - Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16019 -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
16020 - Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16023 -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
16024 - Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16027 -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
16028 - Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16031 -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
16032 - Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16035 -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
16036 - Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16039 -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
16040 - Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16043 -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
16044 - Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16047 -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
16048 - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16051 -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
16052 - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16055 -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
16056 - Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
16059 -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
16060 - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16063 -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
16064 - Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
16067 -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
16068 - Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
16071 -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
16072 - Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16075 -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
16076 - Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
16079 -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
16080 - Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16083 -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
16084 - Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
16087 -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
16088 - Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16091 -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
16092 - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16095 -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
16096 - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16099 -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
16100 - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16103 -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
16104 - Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
16107 -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
16108 - Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
16111 -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
16112 - Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
16115 -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
16116 - Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
16119 -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
16120 - Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
16123 -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
16124 - Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
16127 -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
16128 - Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
16131 -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
16132 - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
16135 -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
16136 - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16139 -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
16140 - Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16143 -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
16144 - Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16147 -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
16148 - Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16151 -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
16152 - Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
16155 -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
16156 - Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
16159 -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
16160 - Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
16163 -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
16164 - Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
16167 -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
16168 - Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
16171 -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
16172 - Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
16175 -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
16176 - Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
16179 -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
16180 - Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
16183 -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
16184 - Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
16187 -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
16188 - Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
16191 -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
16192 - Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
16195 -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
16196 - Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
16199 -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
16200 - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16203 -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
16204 - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16207 -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
16208 - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16211 -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
16212 - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16215 -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
16216 - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16219 -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
16220 - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16223 -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
16224 - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16227 -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
16228 - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16231 -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
16232 - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16235 -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
16236 - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16239 -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
16240 - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16243 -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
16244 - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16247 -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
16248 - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16251 -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
16252 - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16255 -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
16256 - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16259 -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
16260 - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16263 -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
16264 - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16267 -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
16268 - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16271 -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
16272 - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16275 -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
16276 - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16279 -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
16280 - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16283 -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
16284 - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16287 -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
16288 - Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16291 -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
16292 - Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16295 -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
16296 - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16299 -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
16300 - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16303 -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
16304 - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16307 -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
16308 - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16311 -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
16312 - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16315 -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
16316 - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16319 -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
16320 - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16323 -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
16324 - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16327 -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
16328 - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16331 -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
16332 - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16335 -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
16336 - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16339 -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
16340 - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16343 -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
16344 - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16347 -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
16348 - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16351 -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
16352 - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16355 -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
16356 - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16359 -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
16360 - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16363 -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
16364 - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16367 -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
16368 - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16371 -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
16372 - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16375 -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
16376 - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16379 -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
16380 - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16383 -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
16384 - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16387 -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
16388 - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16391 -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
16392 - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16395 -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
16396 - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16399 -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
16400 - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16403 -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
16404 - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16407 -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
16408 - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16411 -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
16412 - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16415 -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
16416 - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16419 -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
16420 - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16423 -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
16424 - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16427 -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
16428 - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16431 -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
16432 - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16435 -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
16436 - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16439 -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
16440 - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16443 -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
16444 - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16447 -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
16448 - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16451 -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
16452 - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16455 -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
16456 - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16459 -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
16460 - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16463 -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
16464 - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16467 -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
16468 - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16471 -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
16472 - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16475 -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
16476 - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16479 -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
16480 - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16483 -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
16484 - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16487 -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
16488 - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16491 -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
16492 - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16495 -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
16496 - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16499 -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
16500 - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16503 -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
16504 - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16507 -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
16508 - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16511 -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
16512 - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16515 -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
16516 - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16519 -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
16520 - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16523 -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
16524 - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16527 -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
16528 - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16531 -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
16532 - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16535 -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
16536 - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16539 -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
16540 - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16543 -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
16544 - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16547 -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
16548 - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16551 -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
16552 - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16555 -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
16556 - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16559 -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
16560 - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16563 -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
16564 - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16567 -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
16568 - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16571 -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
16572 - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16575 -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
16576 - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16579 -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
16580 - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16583 -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
16584 - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16587 -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
16588 - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16591 -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
16592 - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16595 -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
16596 - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16599 -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
16600 - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16603 -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
16604 - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16607 -xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
16608 - Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16611 -xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
16612 - Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16615 -xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
16616 - Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16619 -xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
16620 - Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16623 -xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
16624 - Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16627 -xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
16628 - Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16631 -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
16632 - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16635 -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
16636 - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16639 -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
16640 - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16643 -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
16644 - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16647 -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
16648 - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16651 -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
16652 - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16655 -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
16656 - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16659 -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
16660 - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16663 -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
16664 - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16667 -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
16668 - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16671 -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
16672 - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16675 -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
16676 - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16679 -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
16680 - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16683 -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
16684 - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16687 -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
16688 - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16691 -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
16692 - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16695 -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
16696 - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16699 -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
16700 - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16703 -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
16704 - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16707 -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
16708 - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16711 -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
16712 - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16715 -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
16716 - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16719 -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
16720 - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16723 -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
16724 - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16727 -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
16728 - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16731 -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
16732 - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16735 -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
16736 - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16739 -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
16740 - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16743 -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
16744 - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16747 -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
16748 - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16751 -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
16752 - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16755 -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
16756 - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16759 -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
16760 - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16763 -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
16764 - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16767 -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
16768 - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16771 -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
16772 - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16775 -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
16776 - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16779 -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
16780 - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16783 -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
16784 - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16787 -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
16788 - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16791 -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
16792 - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16795 -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
16796 - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16799 -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
16800 - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16803 -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
16804 - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16807 -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
16808 - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16811 -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
16812 - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16815 -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
16816 - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16819 -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
16820 - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16823 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
16824 - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16827 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
16828 - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16831 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
16832 - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16835 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
16836 - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16839 -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
16840 - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16843 -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
16844 - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16847 -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
16848 - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16851 -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
16852 - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16855 -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
16856 - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16859 -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
16860 - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16863 -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
16864 - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16867 -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
16868 - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16871 -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
16872 - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16875 -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
16876 - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16879 -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
16880 - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16883 -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
16884 - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16887 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
16888 - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16891 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
16892 - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16895 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
16896 - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16899 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
16900 - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16903 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
16904 - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16907 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
16908 - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16911 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
16912 - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16915 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
16916 - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16919 -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
16920 - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16923 -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
16924 - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16927 -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
16928 - Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
16931 -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
16932 - Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
16935 -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
16936 - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16939 -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
16940 - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16943 -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
16944 - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16947 -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
16948 - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16951 -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
16952 - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16955 -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
16956 - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16959 -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
16960 - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16963 -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
16964 - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16967 -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
16968 - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16971 -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
16972 - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16975 -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
16976 - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16979 -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
16980 - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16983 -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
16984 - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16987 -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
16988 - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16991 -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
16992 - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16995 -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
16996 - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16999 -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
17000 - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17003 -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
17004 - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17007 -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
17008 - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17011 -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
17012 - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17015 -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
17016 - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17019 -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
17020 - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17023 -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
17024 - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17027 -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
17028 - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17031 -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
17032 - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17035 -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
17036 - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17039 -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
17040 - Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17043 -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
17044 - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
17047 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
17048 - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17051 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
17052 - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17055 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
17056 - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17059 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
17060 - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17063 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
17064 - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17067 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
17068 - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17071 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
17072 - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17075 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
17076 - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17079 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
17080 - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17083 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
17084 - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17087 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
17088 - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17091 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
17092 - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17095 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
17096 - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17099 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
17100 - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17103 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
17104 - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17107 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
17108 - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17111 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
17112 - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17115 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
17116 - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17119 -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
17120 - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17123 -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
17124 - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17127 -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
17128 - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17131 -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
17132 - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17135 -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
17136 - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17139 -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
17140 - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17143 -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
17144 - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17147 -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
17148 - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17151 -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
17152 - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17155 -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
17156 - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17159 -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
17160 - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17163 -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
17164 - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17167 -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
17168 - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17171 -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
17172 - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17175 -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
17176 - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17179 -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
17180 - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17183 -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
17184 - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17187 -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
17188 - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17191 -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
17192 - Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17195 -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
17196 - Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17199 -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
17200 - Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17203 -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
17204 - Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17207 -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
17208 - Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17211 -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
17212 - Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17215 -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
17216 - Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17219 -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
17220 - Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17223 -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
17224 - Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17227 -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
17228 - Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17231 -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
17232 - Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17235 -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
17236 - Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17239 -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
17240 - Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17243 -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
17244 - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17247 -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
17248 - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17251 -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
17252 - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17255 -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
17256 - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17259 -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
17260 - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17263 -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
17264 - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17267 -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
17268 - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17271 -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
17272 - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17275 -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
17276 - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17279 -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
17280 - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17283 -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
17284 - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17287 -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
17288 - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17291 -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
17292 - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17295 -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
17296 - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17299 -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
17300 - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17303 -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
17304 - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17307 -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
17308 - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17311 -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
17312 - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17315 -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
17316 - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17319 -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
17320 - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17323 -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
17324 - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17327 -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
17328 - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17331 -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
17332 - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17335 -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
17336 - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17339 -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
17340 - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17343 -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
17344 - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17347 -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
17348 - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17351 -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
17352 - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17355 -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
17356 - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17359 -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
17360 - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17363 -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
17364 - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17367 -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
17368 - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17371 -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
17372 - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17375 -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
17376 - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17379 -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
17380 - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17383 -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
17384 - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17387 -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
17388 - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17391 -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
17392 - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17395 -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
17396 - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17399 -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
17400 - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17403 -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
17404 - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17407 -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
17408 - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17411 -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
17412 - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17415 -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
17416 - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17419 -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
17420 - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17423 -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
17424 - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17427 -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
17428 - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17431 -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
17432 - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17435 -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
17436 - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17439 -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
17440 - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17443 -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
17444 - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17447 -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
17448 - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17451 -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
17452 - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17455 -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
17456 - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17459 -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
17460 - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17463 -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
17464 - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17467 -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
17468 - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17471 -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
17472 - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17475 -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
17476 - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17479 -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
17480 - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17483 -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
17484 - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17487 -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
17488 - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17491 -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
17492 - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17495 -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
17496 - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17499 -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
17500 - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17503 -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
17504 - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17507 -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
17508 - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17511 -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
17512 - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17515 -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
17516 - Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
17519 -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
17520 - Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
17523 -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
17524 - Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
17527 -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
17528 - Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17531 -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
17532 - Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17535 -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
17536 - Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
17539 -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
17540 - Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
17543 -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
17544 - Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
17547 -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
17548 - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17551 -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
17552 - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17555 -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
17556 - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17559 -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
17560 - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17563 -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
17564 - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17567 -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
17568 - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17571 -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
17572 - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17575 -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
17576 - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17579 -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
17580 - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17583 -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
17584 - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17587 -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
17588 - Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
17591 -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
17592 - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17595 -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
17596 - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17599 -xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
17600 - Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17603 -xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
17604 - Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17607 -xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
17608 - Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17611 -xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
17612 - Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17615 -xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
17616 - Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17619 -xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
17620 - Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17623 -xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
17624 - Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17627 -xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
17628 - Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17631 -xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
17632 - Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17635 -xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
17636 - Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17639 -xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
17640 - Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17643 -xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
17644 - Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17647 -xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
17648 - Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17651 -xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
17652 - Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17655 -xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
17656 - Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17659 -xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
17660 - Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17663 -xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
17664 - Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17667 -xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
17668 - Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17671 -xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
17672 - Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17675 -xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
17676 - Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17679 -xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
17680 - Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17683 -xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
17684 - Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17687 -xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
17688 - Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17691 -xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
17692 - Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17695 -xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
17696 - Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17699 -xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
17700 - Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17703 -xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
17704 - Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17707 -xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
17708 - Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17711 -xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
17712 - Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17715 -xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
17716 - Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17719 -xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
17720 - Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17723 -xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
17724 - Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17727 -xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
17728 - Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17731 -xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
17732 - Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17735 -xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
17736 - Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17739 -xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
17740 - Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17743 -xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
17744 - Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17747 -xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
17748 - Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17751 -xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
17752 - Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17755 -xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
17756 - Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17759 -xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
17760 - Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17763 -xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
17764 - Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17767 -xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
17768 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
17771 -xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
17772 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
17775 -xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
17776 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
17779 -xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
17780 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
17783 -xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
17784 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
17787 -xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
17788 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
17791 -xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
17792 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
17795 -xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
17796 - 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
17799 -xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
17800 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
17803 -xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
17804 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
17807 -xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
17808 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
17811 -xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
17812 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
17815 -xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
17816 - 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
17819 -xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
17820 - 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
17823 -xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
17824 - 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
17827 -xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
17828 - 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
17831 -xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
17832 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
17835 -xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
17836 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
17839 -xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
17840 - 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
17843 -xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
17844 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
17847 -xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
17848 - 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
17851 -xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
17852 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
17855 -xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
17856 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
17859 -xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
17860 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
17864 -/* Opcode table. */
17866 -static xtensa_opcode_internal opcodes[] = {
17867 - { "excw", 0 /* xt_iclass_excw */,
17869 - Opcode_excw_encode_fns, 0, 0 },
17870 - { "rfe", 1 /* xt_iclass_rfe */,
17871 - XTENSA_OPCODE_IS_JUMP,
17872 - Opcode_rfe_encode_fns, 0, 0 },
17873 - { "rfde", 2 /* xt_iclass_rfde */,
17874 - XTENSA_OPCODE_IS_JUMP,
17875 - Opcode_rfde_encode_fns, 0, 0 },
17876 - { "syscall", 3 /* xt_iclass_syscall */,
17878 - Opcode_syscall_encode_fns, 0, 0 },
17879 - { "simcall", 4 /* xt_iclass_simcall */,
17881 - Opcode_simcall_encode_fns, 0, 0 },
17882 - { "call12", 5 /* xt_iclass_call12 */,
17883 - XTENSA_OPCODE_IS_CALL,
17884 - Opcode_call12_encode_fns, 0, 0 },
17885 - { "call8", 6 /* xt_iclass_call8 */,
17886 - XTENSA_OPCODE_IS_CALL,
17887 - Opcode_call8_encode_fns, 0, 0 },
17888 - { "call4", 7 /* xt_iclass_call4 */,
17889 - XTENSA_OPCODE_IS_CALL,
17890 - Opcode_call4_encode_fns, 0, 0 },
17891 - { "callx12", 8 /* xt_iclass_callx12 */,
17892 - XTENSA_OPCODE_IS_CALL,
17893 - Opcode_callx12_encode_fns, 0, 0 },
17894 - { "callx8", 9 /* xt_iclass_callx8 */,
17895 - XTENSA_OPCODE_IS_CALL,
17896 - Opcode_callx8_encode_fns, 0, 0 },
17897 - { "callx4", 10 /* xt_iclass_callx4 */,
17898 - XTENSA_OPCODE_IS_CALL,
17899 - Opcode_callx4_encode_fns, 0, 0 },
17900 - { "entry", 11 /* xt_iclass_entry */,
17902 - Opcode_entry_encode_fns, 0, 0 },
17903 - { "movsp", 12 /* xt_iclass_movsp */,
17905 - Opcode_movsp_encode_fns, 0, 0 },
17906 - { "rotw", 13 /* xt_iclass_rotw */,
17908 - Opcode_rotw_encode_fns, 0, 0 },
17909 - { "retw", 14 /* xt_iclass_retw */,
17910 - XTENSA_OPCODE_IS_JUMP,
17911 - Opcode_retw_encode_fns, 0, 0 },
17912 - { "retw.n", 14 /* xt_iclass_retw */,
17913 - XTENSA_OPCODE_IS_JUMP,
17914 - Opcode_retw_n_encode_fns, 0, 0 },
17915 - { "rfwo", 15 /* xt_iclass_rfwou */,
17916 - XTENSA_OPCODE_IS_JUMP,
17917 - Opcode_rfwo_encode_fns, 0, 0 },
17918 - { "rfwu", 15 /* xt_iclass_rfwou */,
17919 - XTENSA_OPCODE_IS_JUMP,
17920 - Opcode_rfwu_encode_fns, 0, 0 },
17921 - { "l32e", 16 /* xt_iclass_l32e */,
17923 - Opcode_l32e_encode_fns, 0, 0 },
17924 - { "s32e", 17 /* xt_iclass_s32e */,
17926 - Opcode_s32e_encode_fns, 0, 0 },
17927 - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
17929 - Opcode_rsr_windowbase_encode_fns, 0, 0 },
17930 - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
17932 - Opcode_wsr_windowbase_encode_fns, 0, 0 },
17933 - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
17935 - Opcode_xsr_windowbase_encode_fns, 0, 0 },
17936 - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
17938 - Opcode_rsr_windowstart_encode_fns, 0, 0 },
17939 - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
17941 - Opcode_wsr_windowstart_encode_fns, 0, 0 },
17942 - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
17944 - Opcode_xsr_windowstart_encode_fns, 0, 0 },
17945 - { "add.n", 24 /* xt_iclass_add.n */,
17947 - Opcode_add_n_encode_fns, 0, 0 },
17948 - { "addi.n", 25 /* xt_iclass_addi.n */,
17950 - Opcode_addi_n_encode_fns, 0, 0 },
17951 - { "beqz.n", 26 /* xt_iclass_bz6 */,
17952 - XTENSA_OPCODE_IS_BRANCH,
17953 - Opcode_beqz_n_encode_fns, 0, 0 },
17954 - { "bnez.n", 26 /* xt_iclass_bz6 */,
17955 - XTENSA_OPCODE_IS_BRANCH,
17956 - Opcode_bnez_n_encode_fns, 0, 0 },
17957 - { "ill.n", 27 /* xt_iclass_ill.n */,
17959 - Opcode_ill_n_encode_fns, 0, 0 },
17960 - { "l32i.n", 28 /* xt_iclass_loadi4 */,
17962 - Opcode_l32i_n_encode_fns, 0, 0 },
17963 - { "mov.n", 29 /* xt_iclass_mov.n */,
17965 - Opcode_mov_n_encode_fns, 0, 0 },
17966 - { "movi.n", 30 /* xt_iclass_movi.n */,
17968 - Opcode_movi_n_encode_fns, 0, 0 },
17969 - { "nop.n", 31 /* xt_iclass_nopn */,
17971 - Opcode_nop_n_encode_fns, 0, 0 },
17972 - { "ret.n", 32 /* xt_iclass_retn */,
17973 - XTENSA_OPCODE_IS_JUMP,
17974 - Opcode_ret_n_encode_fns, 0, 0 },
17975 - { "s32i.n", 33 /* xt_iclass_storei4 */,
17977 - Opcode_s32i_n_encode_fns, 0, 0 },
17978 - { "rur.threadptr", 34 /* rur_threadptr */,
17980 - Opcode_rur_threadptr_encode_fns, 0, 0 },
17981 - { "wur.threadptr", 35 /* wur_threadptr */,
17983 - Opcode_wur_threadptr_encode_fns, 0, 0 },
17984 - { "addi", 36 /* xt_iclass_addi */,
17986 - Opcode_addi_encode_fns, 0, 0 },
17987 - { "addmi", 37 /* xt_iclass_addmi */,
17989 - Opcode_addmi_encode_fns, 0, 0 },
17990 - { "add", 38 /* xt_iclass_addsub */,
17992 - Opcode_add_encode_fns, 0, 0 },
17993 - { "sub", 38 /* xt_iclass_addsub */,
17995 - Opcode_sub_encode_fns, 0, 0 },
17996 - { "addx2", 38 /* xt_iclass_addsub */,
17998 - Opcode_addx2_encode_fns, 0, 0 },
17999 - { "addx4", 38 /* xt_iclass_addsub */,
18001 - Opcode_addx4_encode_fns, 0, 0 },
18002 - { "addx8", 38 /* xt_iclass_addsub */,
18004 - Opcode_addx8_encode_fns, 0, 0 },
18005 - { "subx2", 38 /* xt_iclass_addsub */,
18007 - Opcode_subx2_encode_fns, 0, 0 },
18008 - { "subx4", 38 /* xt_iclass_addsub */,
18010 - Opcode_subx4_encode_fns, 0, 0 },
18011 - { "subx8", 38 /* xt_iclass_addsub */,
18013 - Opcode_subx8_encode_fns, 0, 0 },
18014 - { "and", 39 /* xt_iclass_bit */,
18016 - Opcode_and_encode_fns, 0, 0 },
18017 - { "or", 39 /* xt_iclass_bit */,
18019 - Opcode_or_encode_fns, 0, 0 },
18020 - { "xor", 39 /* xt_iclass_bit */,
18022 - Opcode_xor_encode_fns, 0, 0 },
18023 - { "beqi", 40 /* xt_iclass_bsi8 */,
18024 - XTENSA_OPCODE_IS_BRANCH,
18025 - Opcode_beqi_encode_fns, 0, 0 },
18026 - { "bnei", 40 /* xt_iclass_bsi8 */,
18027 - XTENSA_OPCODE_IS_BRANCH,
18028 - Opcode_bnei_encode_fns, 0, 0 },
18029 - { "bgei", 40 /* xt_iclass_bsi8 */,
18030 - XTENSA_OPCODE_IS_BRANCH,
18031 - Opcode_bgei_encode_fns, 0, 0 },
18032 - { "blti", 40 /* xt_iclass_bsi8 */,
18033 - XTENSA_OPCODE_IS_BRANCH,
18034 - Opcode_blti_encode_fns, 0, 0 },
18035 - { "bbci", 41 /* xt_iclass_bsi8b */,
18036 - XTENSA_OPCODE_IS_BRANCH,
18037 - Opcode_bbci_encode_fns, 0, 0 },
18038 - { "bbsi", 41 /* xt_iclass_bsi8b */,
18039 - XTENSA_OPCODE_IS_BRANCH,
18040 - Opcode_bbsi_encode_fns, 0, 0 },
18041 - { "bgeui", 42 /* xt_iclass_bsi8u */,
18042 - XTENSA_OPCODE_IS_BRANCH,
18043 - Opcode_bgeui_encode_fns, 0, 0 },
18044 - { "bltui", 42 /* xt_iclass_bsi8u */,
18045 - XTENSA_OPCODE_IS_BRANCH,
18046 - Opcode_bltui_encode_fns, 0, 0 },
18047 - { "beq", 43 /* xt_iclass_bst8 */,
18048 - XTENSA_OPCODE_IS_BRANCH,
18049 - Opcode_beq_encode_fns, 0, 0 },
18050 - { "bne", 43 /* xt_iclass_bst8 */,
18051 - XTENSA_OPCODE_IS_BRANCH,
18052 - Opcode_bne_encode_fns, 0, 0 },
18053 - { "bge", 43 /* xt_iclass_bst8 */,
18054 - XTENSA_OPCODE_IS_BRANCH,
18055 - Opcode_bge_encode_fns, 0, 0 },
18056 - { "blt", 43 /* xt_iclass_bst8 */,
18057 - XTENSA_OPCODE_IS_BRANCH,
18058 - Opcode_blt_encode_fns, 0, 0 },
18059 - { "bgeu", 43 /* xt_iclass_bst8 */,
18060 - XTENSA_OPCODE_IS_BRANCH,
18061 - Opcode_bgeu_encode_fns, 0, 0 },
18062 - { "bltu", 43 /* xt_iclass_bst8 */,
18063 - XTENSA_OPCODE_IS_BRANCH,
18064 - Opcode_bltu_encode_fns, 0, 0 },
18065 - { "bany", 43 /* xt_iclass_bst8 */,
18066 - XTENSA_OPCODE_IS_BRANCH,
18067 - Opcode_bany_encode_fns, 0, 0 },
18068 - { "bnone", 43 /* xt_iclass_bst8 */,
18069 - XTENSA_OPCODE_IS_BRANCH,
18070 - Opcode_bnone_encode_fns, 0, 0 },
18071 - { "ball", 43 /* xt_iclass_bst8 */,
18072 - XTENSA_OPCODE_IS_BRANCH,
18073 - Opcode_ball_encode_fns, 0, 0 },
18074 - { "bnall", 43 /* xt_iclass_bst8 */,
18075 - XTENSA_OPCODE_IS_BRANCH,
18076 - Opcode_bnall_encode_fns, 0, 0 },
18077 - { "bbc", 43 /* xt_iclass_bst8 */,
18078 - XTENSA_OPCODE_IS_BRANCH,
18079 - Opcode_bbc_encode_fns, 0, 0 },
18080 - { "bbs", 43 /* xt_iclass_bst8 */,
18081 - XTENSA_OPCODE_IS_BRANCH,
18082 - Opcode_bbs_encode_fns, 0, 0 },
18083 - { "beqz", 44 /* xt_iclass_bsz12 */,
18084 - XTENSA_OPCODE_IS_BRANCH,
18085 - Opcode_beqz_encode_fns, 0, 0 },
18086 - { "bnez", 44 /* xt_iclass_bsz12 */,
18087 - XTENSA_OPCODE_IS_BRANCH,
18088 - Opcode_bnez_encode_fns, 0, 0 },
18089 - { "bgez", 44 /* xt_iclass_bsz12 */,
18090 - XTENSA_OPCODE_IS_BRANCH,
18091 - Opcode_bgez_encode_fns, 0, 0 },
18092 - { "bltz", 44 /* xt_iclass_bsz12 */,
18093 - XTENSA_OPCODE_IS_BRANCH,
18094 - Opcode_bltz_encode_fns, 0, 0 },
18095 - { "call0", 45 /* xt_iclass_call0 */,
18096 - XTENSA_OPCODE_IS_CALL,
18097 - Opcode_call0_encode_fns, 0, 0 },
18098 - { "callx0", 46 /* xt_iclass_callx0 */,
18099 - XTENSA_OPCODE_IS_CALL,
18100 - Opcode_callx0_encode_fns, 0, 0 },
18101 - { "extui", 47 /* xt_iclass_exti */,
18103 - Opcode_extui_encode_fns, 0, 0 },
18104 - { "ill", 48 /* xt_iclass_ill */,
18106 - Opcode_ill_encode_fns, 0, 0 },
18107 - { "j", 49 /* xt_iclass_jump */,
18108 - XTENSA_OPCODE_IS_JUMP,
18109 - Opcode_j_encode_fns, 0, 0 },
18110 - { "jx", 50 /* xt_iclass_jumpx */,
18111 - XTENSA_OPCODE_IS_JUMP,
18112 - Opcode_jx_encode_fns, 0, 0 },
18113 - { "l16ui", 51 /* xt_iclass_l16ui */,
18115 - Opcode_l16ui_encode_fns, 0, 0 },
18116 - { "l16si", 52 /* xt_iclass_l16si */,
18118 - Opcode_l16si_encode_fns, 0, 0 },
18119 - { "l32i", 53 /* xt_iclass_l32i */,
18121 - Opcode_l32i_encode_fns, 0, 0 },
18122 - { "l32r", 54 /* xt_iclass_l32r */,
18124 - Opcode_l32r_encode_fns, 0, 0 },
18125 - { "l8ui", 55 /* xt_iclass_l8i */,
18127 - Opcode_l8ui_encode_fns, 0, 0 },
18128 - { "loop", 56 /* xt_iclass_loop */,
18129 - XTENSA_OPCODE_IS_LOOP,
18130 - Opcode_loop_encode_fns, 0, 0 },
18131 - { "loopnez", 57 /* xt_iclass_loopz */,
18132 - XTENSA_OPCODE_IS_LOOP,
18133 - Opcode_loopnez_encode_fns, 0, 0 },
18134 - { "loopgtz", 57 /* xt_iclass_loopz */,
18135 - XTENSA_OPCODE_IS_LOOP,
18136 - Opcode_loopgtz_encode_fns, 0, 0 },
18137 - { "movi", 58 /* xt_iclass_movi */,
18139 - Opcode_movi_encode_fns, 0, 0 },
18140 - { "moveqz", 59 /* xt_iclass_movz */,
18142 - Opcode_moveqz_encode_fns, 0, 0 },
18143 - { "movnez", 59 /* xt_iclass_movz */,
18145 - Opcode_movnez_encode_fns, 0, 0 },
18146 - { "movltz", 59 /* xt_iclass_movz */,
18148 - Opcode_movltz_encode_fns, 0, 0 },
18149 - { "movgez", 59 /* xt_iclass_movz */,
18151 - Opcode_movgez_encode_fns, 0, 0 },
18152 - { "neg", 60 /* xt_iclass_neg */,
18154 - Opcode_neg_encode_fns, 0, 0 },
18155 - { "abs", 60 /* xt_iclass_neg */,
18157 - Opcode_abs_encode_fns, 0, 0 },
18158 - { "nop", 61 /* xt_iclass_nop */,
18160 - Opcode_nop_encode_fns, 0, 0 },
18161 - { "ret", 62 /* xt_iclass_return */,
18162 - XTENSA_OPCODE_IS_JUMP,
18163 - Opcode_ret_encode_fns, 0, 0 },
18164 - { "s16i", 63 /* xt_iclass_s16i */,
18166 - Opcode_s16i_encode_fns, 0, 0 },
18167 - { "s32i", 64 /* xt_iclass_s32i */,
18169 - Opcode_s32i_encode_fns, 0, 0 },
18170 - { "s8i", 65 /* xt_iclass_s8i */,
18172 - Opcode_s8i_encode_fns, 0, 0 },
18173 - { "ssr", 66 /* xt_iclass_sar */,
18175 - Opcode_ssr_encode_fns, 0, 0 },
18176 - { "ssl", 66 /* xt_iclass_sar */,
18178 - Opcode_ssl_encode_fns, 0, 0 },
18179 - { "ssa8l", 66 /* xt_iclass_sar */,
18181 - Opcode_ssa8l_encode_fns, 0, 0 },
18182 - { "ssa8b", 66 /* xt_iclass_sar */,
18184 - Opcode_ssa8b_encode_fns, 0, 0 },
18185 - { "ssai", 67 /* xt_iclass_sari */,
18187 - Opcode_ssai_encode_fns, 0, 0 },
18188 - { "sll", 68 /* xt_iclass_shifts */,
18190 - Opcode_sll_encode_fns, 0, 0 },
18191 - { "src", 69 /* xt_iclass_shiftst */,
18193 - Opcode_src_encode_fns, 0, 0 },
18194 - { "srl", 70 /* xt_iclass_shiftt */,
18196 - Opcode_srl_encode_fns, 0, 0 },
18197 - { "sra", 70 /* xt_iclass_shiftt */,
18199 - Opcode_sra_encode_fns, 0, 0 },
18200 - { "slli", 71 /* xt_iclass_slli */,
18202 - Opcode_slli_encode_fns, 0, 0 },
18203 - { "srai", 72 /* xt_iclass_srai */,
18205 - Opcode_srai_encode_fns, 0, 0 },
18206 - { "srli", 73 /* xt_iclass_srli */,
18208 - Opcode_srli_encode_fns, 0, 0 },
18209 - { "memw", 74 /* xt_iclass_memw */,
18211 - Opcode_memw_encode_fns, 0, 0 },
18212 - { "extw", 75 /* xt_iclass_extw */,
18214 - Opcode_extw_encode_fns, 0, 0 },
18215 - { "isync", 76 /* xt_iclass_isync */,
18217 - Opcode_isync_encode_fns, 0, 0 },
18218 - { "rsync", 77 /* xt_iclass_sync */,
18220 - Opcode_rsync_encode_fns, 0, 0 },
18221 - { "esync", 77 /* xt_iclass_sync */,
18223 - Opcode_esync_encode_fns, 0, 0 },
18224 - { "dsync", 77 /* xt_iclass_sync */,
18226 - Opcode_dsync_encode_fns, 0, 0 },
18227 - { "rsil", 78 /* xt_iclass_rsil */,
18229 - Opcode_rsil_encode_fns, 0, 0 },
18230 - { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
18232 - Opcode_rsr_lend_encode_fns, 0, 0 },
18233 - { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
18235 - Opcode_wsr_lend_encode_fns, 0, 0 },
18236 - { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
18238 - Opcode_xsr_lend_encode_fns, 0, 0 },
18239 - { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
18241 - Opcode_rsr_lcount_encode_fns, 0, 0 },
18242 - { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
18244 - Opcode_wsr_lcount_encode_fns, 0, 0 },
18245 - { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
18247 - Opcode_xsr_lcount_encode_fns, 0, 0 },
18248 - { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
18250 - Opcode_rsr_lbeg_encode_fns, 0, 0 },
18251 - { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
18253 - Opcode_wsr_lbeg_encode_fns, 0, 0 },
18254 - { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
18256 - Opcode_xsr_lbeg_encode_fns, 0, 0 },
18257 - { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
18259 - Opcode_rsr_sar_encode_fns, 0, 0 },
18260 - { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
18262 - Opcode_wsr_sar_encode_fns, 0, 0 },
18263 - { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
18265 - Opcode_xsr_sar_encode_fns, 0, 0 },
18266 - { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
18268 - Opcode_rsr_litbase_encode_fns, 0, 0 },
18269 - { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
18271 - Opcode_wsr_litbase_encode_fns, 0, 0 },
18272 - { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
18274 - Opcode_xsr_litbase_encode_fns, 0, 0 },
18275 - { "rsr.176", 94 /* xt_iclass_rsr.176 */,
18277 - Opcode_rsr_176_encode_fns, 0, 0 },
18278 - { "rsr.208", 95 /* xt_iclass_rsr.208 */,
18280 - Opcode_rsr_208_encode_fns, 0, 0 },
18281 - { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
18283 - Opcode_rsr_ps_encode_fns, 0, 0 },
18284 - { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
18286 - Opcode_wsr_ps_encode_fns, 0, 0 },
18287 - { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
18289 - Opcode_xsr_ps_encode_fns, 0, 0 },
18290 - { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
18292 - Opcode_rsr_epc1_encode_fns, 0, 0 },
18293 - { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
18295 - Opcode_wsr_epc1_encode_fns, 0, 0 },
18296 - { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
18298 - Opcode_xsr_epc1_encode_fns, 0, 0 },
18299 - { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
18301 - Opcode_rsr_excsave1_encode_fns, 0, 0 },
18302 - { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
18304 - Opcode_wsr_excsave1_encode_fns, 0, 0 },
18305 - { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
18307 - Opcode_xsr_excsave1_encode_fns, 0, 0 },
18308 - { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
18310 - Opcode_rsr_epc2_encode_fns, 0, 0 },
18311 - { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
18313 - Opcode_wsr_epc2_encode_fns, 0, 0 },
18314 - { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
18316 - Opcode_xsr_epc2_encode_fns, 0, 0 },
18317 - { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
18319 - Opcode_rsr_excsave2_encode_fns, 0, 0 },
18320 - { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
18322 - Opcode_wsr_excsave2_encode_fns, 0, 0 },
18323 - { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
18325 - Opcode_xsr_excsave2_encode_fns, 0, 0 },
18326 - { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
18328 - Opcode_rsr_epc3_encode_fns, 0, 0 },
18329 - { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
18331 - Opcode_wsr_epc3_encode_fns, 0, 0 },
18332 - { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
18334 - Opcode_xsr_epc3_encode_fns, 0, 0 },
18335 - { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
18337 - Opcode_rsr_excsave3_encode_fns, 0, 0 },
18338 - { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
18340 - Opcode_wsr_excsave3_encode_fns, 0, 0 },
18341 - { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
18343 - Opcode_xsr_excsave3_encode_fns, 0, 0 },
18344 - { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
18346 - Opcode_rsr_epc4_encode_fns, 0, 0 },
18347 - { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
18349 - Opcode_wsr_epc4_encode_fns, 0, 0 },
18350 - { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
18352 - Opcode_xsr_epc4_encode_fns, 0, 0 },
18353 - { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
18355 - Opcode_rsr_excsave4_encode_fns, 0, 0 },
18356 - { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
18358 - Opcode_wsr_excsave4_encode_fns, 0, 0 },
18359 - { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
18361 - Opcode_xsr_excsave4_encode_fns, 0, 0 },
18362 - { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
18364 - Opcode_rsr_epc5_encode_fns, 0, 0 },
18365 - { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
18367 - Opcode_wsr_epc5_encode_fns, 0, 0 },
18368 - { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
18370 - Opcode_xsr_epc5_encode_fns, 0, 0 },
18371 - { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
18373 - Opcode_rsr_excsave5_encode_fns, 0, 0 },
18374 - { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
18376 - Opcode_wsr_excsave5_encode_fns, 0, 0 },
18377 - { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
18379 - Opcode_xsr_excsave5_encode_fns, 0, 0 },
18380 - { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
18382 - Opcode_rsr_epc6_encode_fns, 0, 0 },
18383 - { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
18385 - Opcode_wsr_epc6_encode_fns, 0, 0 },
18386 - { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
18388 - Opcode_xsr_epc6_encode_fns, 0, 0 },
18389 - { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
18391 - Opcode_rsr_excsave6_encode_fns, 0, 0 },
18392 - { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
18394 - Opcode_wsr_excsave6_encode_fns, 0, 0 },
18395 - { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
18397 - Opcode_xsr_excsave6_encode_fns, 0, 0 },
18398 - { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
18400 - Opcode_rsr_epc7_encode_fns, 0, 0 },
18401 - { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
18403 - Opcode_wsr_epc7_encode_fns, 0, 0 },
18404 - { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
18406 - Opcode_xsr_epc7_encode_fns, 0, 0 },
18407 - { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
18409 - Opcode_rsr_excsave7_encode_fns, 0, 0 },
18410 - { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
18412 - Opcode_wsr_excsave7_encode_fns, 0, 0 },
18413 - { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
18415 - Opcode_xsr_excsave7_encode_fns, 0, 0 },
18416 - { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
18418 - Opcode_rsr_eps2_encode_fns, 0, 0 },
18419 - { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
18421 - Opcode_wsr_eps2_encode_fns, 0, 0 },
18422 - { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
18424 - Opcode_xsr_eps2_encode_fns, 0, 0 },
18425 - { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
18427 - Opcode_rsr_eps3_encode_fns, 0, 0 },
18428 - { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
18430 - Opcode_wsr_eps3_encode_fns, 0, 0 },
18431 - { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
18433 - Opcode_xsr_eps3_encode_fns, 0, 0 },
18434 - { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
18436 - Opcode_rsr_eps4_encode_fns, 0, 0 },
18437 - { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
18439 - Opcode_wsr_eps4_encode_fns, 0, 0 },
18440 - { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
18442 - Opcode_xsr_eps4_encode_fns, 0, 0 },
18443 - { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
18445 - Opcode_rsr_eps5_encode_fns, 0, 0 },
18446 - { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
18448 - Opcode_wsr_eps5_encode_fns, 0, 0 },
18449 - { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
18451 - Opcode_xsr_eps5_encode_fns, 0, 0 },
18452 - { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
18454 - Opcode_rsr_eps6_encode_fns, 0, 0 },
18455 - { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
18457 - Opcode_wsr_eps6_encode_fns, 0, 0 },
18458 - { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
18460 - Opcode_xsr_eps6_encode_fns, 0, 0 },
18461 - { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
18463 - Opcode_rsr_eps7_encode_fns, 0, 0 },
18464 - { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
18466 - Opcode_wsr_eps7_encode_fns, 0, 0 },
18467 - { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
18469 - Opcode_xsr_eps7_encode_fns, 0, 0 },
18470 - { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
18472 - Opcode_rsr_excvaddr_encode_fns, 0, 0 },
18473 - { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
18475 - Opcode_wsr_excvaddr_encode_fns, 0, 0 },
18476 - { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
18478 - Opcode_xsr_excvaddr_encode_fns, 0, 0 },
18479 - { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
18481 - Opcode_rsr_depc_encode_fns, 0, 0 },
18482 - { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
18484 - Opcode_wsr_depc_encode_fns, 0, 0 },
18485 - { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
18487 - Opcode_xsr_depc_encode_fns, 0, 0 },
18488 - { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
18490 - Opcode_rsr_exccause_encode_fns, 0, 0 },
18491 - { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
18493 - Opcode_wsr_exccause_encode_fns, 0, 0 },
18494 - { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
18496 - Opcode_xsr_exccause_encode_fns, 0, 0 },
18497 - { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
18499 - Opcode_rsr_misc0_encode_fns, 0, 0 },
18500 - { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
18502 - Opcode_wsr_misc0_encode_fns, 0, 0 },
18503 - { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
18505 - Opcode_xsr_misc0_encode_fns, 0, 0 },
18506 - { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
18508 - Opcode_rsr_misc1_encode_fns, 0, 0 },
18509 - { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
18511 - Opcode_wsr_misc1_encode_fns, 0, 0 },
18512 - { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
18514 - Opcode_xsr_misc1_encode_fns, 0, 0 },
18515 - { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
18517 - Opcode_rsr_misc2_encode_fns, 0, 0 },
18518 - { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
18520 - Opcode_wsr_misc2_encode_fns, 0, 0 },
18521 - { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
18523 - Opcode_xsr_misc2_encode_fns, 0, 0 },
18524 - { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
18526 - Opcode_rsr_misc3_encode_fns, 0, 0 },
18527 - { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
18529 - Opcode_wsr_misc3_encode_fns, 0, 0 },
18530 - { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
18532 - Opcode_xsr_misc3_encode_fns, 0, 0 },
18533 - { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
18535 - Opcode_rsr_prid_encode_fns, 0, 0 },
18536 - { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
18538 - Opcode_rsr_vecbase_encode_fns, 0, 0 },
18539 - { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
18541 - Opcode_wsr_vecbase_encode_fns, 0, 0 },
18542 - { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
18544 - Opcode_xsr_vecbase_encode_fns, 0, 0 },
18545 - { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18547 - Opcode_mul_aa_ll_encode_fns, 0, 0 },
18548 - { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18550 - Opcode_mul_aa_hl_encode_fns, 0, 0 },
18551 - { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18553 - Opcode_mul_aa_lh_encode_fns, 0, 0 },
18554 - { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18556 - Opcode_mul_aa_hh_encode_fns, 0, 0 },
18557 - { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18559 - Opcode_umul_aa_ll_encode_fns, 0, 0 },
18560 - { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18562 - Opcode_umul_aa_hl_encode_fns, 0, 0 },
18563 - { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18565 - Opcode_umul_aa_lh_encode_fns, 0, 0 },
18566 - { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18568 - Opcode_umul_aa_hh_encode_fns, 0, 0 },
18569 - { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
18571 - Opcode_mul_ad_ll_encode_fns, 0, 0 },
18572 - { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
18574 - Opcode_mul_ad_hl_encode_fns, 0, 0 },
18575 - { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
18577 - Opcode_mul_ad_lh_encode_fns, 0, 0 },
18578 - { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
18580 - Opcode_mul_ad_hh_encode_fns, 0, 0 },
18581 - { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
18583 - Opcode_mul_da_ll_encode_fns, 0, 0 },
18584 - { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
18586 - Opcode_mul_da_hl_encode_fns, 0, 0 },
18587 - { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
18589 - Opcode_mul_da_lh_encode_fns, 0, 0 },
18590 - { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
18592 - Opcode_mul_da_hh_encode_fns, 0, 0 },
18593 - { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
18595 - Opcode_mul_dd_ll_encode_fns, 0, 0 },
18596 - { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
18598 - Opcode_mul_dd_hl_encode_fns, 0, 0 },
18599 - { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
18601 - Opcode_mul_dd_lh_encode_fns, 0, 0 },
18602 - { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
18604 - Opcode_mul_dd_hh_encode_fns, 0, 0 },
18605 - { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18607 - Opcode_mula_aa_ll_encode_fns, 0, 0 },
18608 - { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18610 - Opcode_mula_aa_hl_encode_fns, 0, 0 },
18611 - { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18613 - Opcode_mula_aa_lh_encode_fns, 0, 0 },
18614 - { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18616 - Opcode_mula_aa_hh_encode_fns, 0, 0 },
18617 - { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18619 - Opcode_muls_aa_ll_encode_fns, 0, 0 },
18620 - { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18622 - Opcode_muls_aa_hl_encode_fns, 0, 0 },
18623 - { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18625 - Opcode_muls_aa_lh_encode_fns, 0, 0 },
18626 - { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18628 - Opcode_muls_aa_hh_encode_fns, 0, 0 },
18629 - { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18631 - Opcode_mula_ad_ll_encode_fns, 0, 0 },
18632 - { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18634 - Opcode_mula_ad_hl_encode_fns, 0, 0 },
18635 - { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18637 - Opcode_mula_ad_lh_encode_fns, 0, 0 },
18638 - { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18640 - Opcode_mula_ad_hh_encode_fns, 0, 0 },
18641 - { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18643 - Opcode_muls_ad_ll_encode_fns, 0, 0 },
18644 - { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18646 - Opcode_muls_ad_hl_encode_fns, 0, 0 },
18647 - { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18649 - Opcode_muls_ad_lh_encode_fns, 0, 0 },
18650 - { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18652 - Opcode_muls_ad_hh_encode_fns, 0, 0 },
18653 - { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
18655 - Opcode_mula_da_ll_encode_fns, 0, 0 },
18656 - { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
18658 - Opcode_mula_da_hl_encode_fns, 0, 0 },
18659 - { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
18661 - Opcode_mula_da_lh_encode_fns, 0, 0 },
18662 - { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
18664 - Opcode_mula_da_hh_encode_fns, 0, 0 },
18665 - { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
18667 - Opcode_muls_da_ll_encode_fns, 0, 0 },
18668 - { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
18670 - Opcode_muls_da_hl_encode_fns, 0, 0 },
18671 - { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
18673 - Opcode_muls_da_lh_encode_fns, 0, 0 },
18674 - { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
18676 - Opcode_muls_da_hh_encode_fns, 0, 0 },
18677 - { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18679 - Opcode_mula_dd_ll_encode_fns, 0, 0 },
18680 - { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18682 - Opcode_mula_dd_hl_encode_fns, 0, 0 },
18683 - { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18685 - Opcode_mula_dd_lh_encode_fns, 0, 0 },
18686 - { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18688 - Opcode_mula_dd_hh_encode_fns, 0, 0 },
18689 - { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18691 - Opcode_muls_dd_ll_encode_fns, 0, 0 },
18692 - { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18694 - Opcode_muls_dd_hl_encode_fns, 0, 0 },
18695 - { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18697 - Opcode_muls_dd_lh_encode_fns, 0, 0 },
18698 - { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18700 - Opcode_muls_dd_hh_encode_fns, 0, 0 },
18701 - { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
18703 - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
18704 - { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
18706 - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
18707 - { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
18709 - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
18710 - { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
18712 - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
18713 - { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
18715 - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
18716 - { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
18718 - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
18719 - { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
18721 - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
18722 - { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
18724 - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
18725 - { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
18727 - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
18728 - { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
18730 - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
18731 - { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
18733 - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
18734 - { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
18736 - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
18737 - { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
18739 - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
18740 - { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18742 - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
18743 - { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
18745 - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
18746 - { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18748 - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
18749 - { "lddec", 194 /* xt_iclass_mac16_l */,
18751 - Opcode_lddec_encode_fns, 0, 0 },
18752 - { "ldinc", 194 /* xt_iclass_mac16_l */,
18754 - Opcode_ldinc_encode_fns, 0, 0 },
18755 - { "mul16u", 195 /* xt_iclass_mul16 */,
18757 - Opcode_mul16u_encode_fns, 0, 0 },
18758 - { "mul16s", 195 /* xt_iclass_mul16 */,
18760 - Opcode_mul16s_encode_fns, 0, 0 },
18761 - { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
18763 - Opcode_rsr_m0_encode_fns, 0, 0 },
18764 - { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
18766 - Opcode_wsr_m0_encode_fns, 0, 0 },
18767 - { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
18769 - Opcode_xsr_m0_encode_fns, 0, 0 },
18770 - { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
18772 - Opcode_rsr_m1_encode_fns, 0, 0 },
18773 - { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
18775 - Opcode_wsr_m1_encode_fns, 0, 0 },
18776 - { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
18778 - Opcode_xsr_m1_encode_fns, 0, 0 },
18779 - { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
18781 - Opcode_rsr_m2_encode_fns, 0, 0 },
18782 - { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
18784 - Opcode_wsr_m2_encode_fns, 0, 0 },
18785 - { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
18787 - Opcode_xsr_m2_encode_fns, 0, 0 },
18788 - { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
18790 - Opcode_rsr_m3_encode_fns, 0, 0 },
18791 - { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
18793 - Opcode_wsr_m3_encode_fns, 0, 0 },
18794 - { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
18796 - Opcode_xsr_m3_encode_fns, 0, 0 },
18797 - { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
18799 - Opcode_rsr_acclo_encode_fns, 0, 0 },
18800 - { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
18802 - Opcode_wsr_acclo_encode_fns, 0, 0 },
18803 - { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
18805 - Opcode_xsr_acclo_encode_fns, 0, 0 },
18806 - { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
18808 - Opcode_rsr_acchi_encode_fns, 0, 0 },
18809 - { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
18811 - Opcode_wsr_acchi_encode_fns, 0, 0 },
18812 - { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
18814 - Opcode_xsr_acchi_encode_fns, 0, 0 },
18815 - { "rfi", 214 /* xt_iclass_rfi */,
18816 - XTENSA_OPCODE_IS_JUMP,
18817 - Opcode_rfi_encode_fns, 0, 0 },
18818 - { "waiti", 215 /* xt_iclass_wait */,
18820 - Opcode_waiti_encode_fns, 0, 0 },
18821 - { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
18823 - Opcode_rsr_interrupt_encode_fns, 0, 0 },
18824 - { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
18826 - Opcode_wsr_intset_encode_fns, 0, 0 },
18827 - { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
18829 - Opcode_wsr_intclear_encode_fns, 0, 0 },
18830 - { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
18832 - Opcode_rsr_intenable_encode_fns, 0, 0 },
18833 - { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
18835 - Opcode_wsr_intenable_encode_fns, 0, 0 },
18836 - { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
18838 - Opcode_xsr_intenable_encode_fns, 0, 0 },
18839 - { "break", 222 /* xt_iclass_break */,
18841 - Opcode_break_encode_fns, 0, 0 },
18842 - { "break.n", 223 /* xt_iclass_break.n */,
18844 - Opcode_break_n_encode_fns, 0, 0 },
18845 - { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
18847 - Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
18848 - { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
18850 - Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
18851 - { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
18853 - Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
18854 - { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
18856 - Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
18857 - { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
18859 - Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
18860 - { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
18862 - Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
18863 - { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
18865 - Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
18866 - { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
18868 - Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
18869 - { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
18871 - Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
18872 - { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
18874 - Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
18875 - { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
18877 - Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
18878 - { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
18880 - Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
18881 - { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
18883 - Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
18884 - { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
18886 - Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
18887 - { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
18889 - Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
18890 - { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
18892 - Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
18893 - { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
18895 - Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
18896 - { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
18898 - Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
18899 - { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
18901 - Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
18902 - { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
18904 - Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
18905 - { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
18907 - Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
18908 - { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
18910 - Opcode_rsr_debugcause_encode_fns, 0, 0 },
18911 - { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
18913 - Opcode_wsr_debugcause_encode_fns, 0, 0 },
18914 - { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
18916 - Opcode_xsr_debugcause_encode_fns, 0, 0 },
18917 - { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
18919 - Opcode_rsr_icount_encode_fns, 0, 0 },
18920 - { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
18922 - Opcode_wsr_icount_encode_fns, 0, 0 },
18923 - { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
18925 - Opcode_xsr_icount_encode_fns, 0, 0 },
18926 - { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
18928 - Opcode_rsr_icountlevel_encode_fns, 0, 0 },
18929 - { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
18931 - Opcode_wsr_icountlevel_encode_fns, 0, 0 },
18932 - { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
18934 - Opcode_xsr_icountlevel_encode_fns, 0, 0 },
18935 - { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
18937 - Opcode_rsr_ddr_encode_fns, 0, 0 },
18938 - { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
18940 - Opcode_wsr_ddr_encode_fns, 0, 0 },
18941 - { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
18943 - Opcode_xsr_ddr_encode_fns, 0, 0 },
18944 - { "rfdo", 257 /* xt_iclass_rfdo */,
18945 - XTENSA_OPCODE_IS_JUMP,
18946 - Opcode_rfdo_encode_fns, 0, 0 },
18947 - { "rfdd", 258 /* xt_iclass_rfdd */,
18948 - XTENSA_OPCODE_IS_JUMP,
18949 - Opcode_rfdd_encode_fns, 0, 0 },
18950 - { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
18952 - Opcode_wsr_mmid_encode_fns, 0, 0 },
18953 - { "andb", 260 /* xt_iclass_bbool1 */,
18955 - Opcode_andb_encode_fns, 0, 0 },
18956 - { "andbc", 260 /* xt_iclass_bbool1 */,
18958 - Opcode_andbc_encode_fns, 0, 0 },
18959 - { "orb", 260 /* xt_iclass_bbool1 */,
18961 - Opcode_orb_encode_fns, 0, 0 },
18962 - { "orbc", 260 /* xt_iclass_bbool1 */,
18964 - Opcode_orbc_encode_fns, 0, 0 },
18965 - { "xorb", 260 /* xt_iclass_bbool1 */,
18967 - Opcode_xorb_encode_fns, 0, 0 },
18968 - { "any4", 261 /* xt_iclass_bbool4 */,
18970 - Opcode_any4_encode_fns, 0, 0 },
18971 - { "all4", 261 /* xt_iclass_bbool4 */,
18973 - Opcode_all4_encode_fns, 0, 0 },
18974 - { "any8", 262 /* xt_iclass_bbool8 */,
18976 - Opcode_any8_encode_fns, 0, 0 },
18977 - { "all8", 262 /* xt_iclass_bbool8 */,
18979 - Opcode_all8_encode_fns, 0, 0 },
18980 - { "bf", 263 /* xt_iclass_bbranch */,
18981 - XTENSA_OPCODE_IS_BRANCH,
18982 - Opcode_bf_encode_fns, 0, 0 },
18983 - { "bt", 263 /* xt_iclass_bbranch */,
18984 - XTENSA_OPCODE_IS_BRANCH,
18985 - Opcode_bt_encode_fns, 0, 0 },
18986 - { "movf", 264 /* xt_iclass_bmove */,
18988 - Opcode_movf_encode_fns, 0, 0 },
18989 - { "movt", 264 /* xt_iclass_bmove */,
18991 - Opcode_movt_encode_fns, 0, 0 },
18992 - { "rsr.br", 265 /* xt_iclass_RSR.BR */,
18994 - Opcode_rsr_br_encode_fns, 0, 0 },
18995 - { "wsr.br", 266 /* xt_iclass_WSR.BR */,
18997 - Opcode_wsr_br_encode_fns, 0, 0 },
18998 - { "xsr.br", 267 /* xt_iclass_XSR.BR */,
19000 - Opcode_xsr_br_encode_fns, 0, 0 },
19001 - { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
19003 - Opcode_rsr_ccount_encode_fns, 0, 0 },
19004 - { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
19006 - Opcode_wsr_ccount_encode_fns, 0, 0 },
19007 - { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
19009 - Opcode_xsr_ccount_encode_fns, 0, 0 },
19010 - { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
19012 - Opcode_rsr_ccompare0_encode_fns, 0, 0 },
19013 - { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
19015 - Opcode_wsr_ccompare0_encode_fns, 0, 0 },
19016 - { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
19018 - Opcode_xsr_ccompare0_encode_fns, 0, 0 },
19019 - { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
19021 - Opcode_rsr_ccompare1_encode_fns, 0, 0 },
19022 - { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
19024 - Opcode_wsr_ccompare1_encode_fns, 0, 0 },
19025 - { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
19027 - Opcode_xsr_ccompare1_encode_fns, 0, 0 },
19028 - { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
19030 - Opcode_rsr_ccompare2_encode_fns, 0, 0 },
19031 - { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
19033 - Opcode_wsr_ccompare2_encode_fns, 0, 0 },
19034 - { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
19036 - Opcode_xsr_ccompare2_encode_fns, 0, 0 },
19037 - { "ipf", 280 /* xt_iclass_icache */,
19039 - Opcode_ipf_encode_fns, 0, 0 },
19040 - { "ihi", 280 /* xt_iclass_icache */,
19042 - Opcode_ihi_encode_fns, 0, 0 },
19043 - { "ipfl", 281 /* xt_iclass_icache_lock */,
19045 - Opcode_ipfl_encode_fns, 0, 0 },
19046 - { "ihu", 281 /* xt_iclass_icache_lock */,
19048 - Opcode_ihu_encode_fns, 0, 0 },
19049 - { "iiu", 281 /* xt_iclass_icache_lock */,
19051 - Opcode_iiu_encode_fns, 0, 0 },
19052 - { "iii", 282 /* xt_iclass_icache_inv */,
19054 - Opcode_iii_encode_fns, 0, 0 },
19055 - { "lict", 283 /* xt_iclass_licx */,
19057 - Opcode_lict_encode_fns, 0, 0 },
19058 - { "licw", 283 /* xt_iclass_licx */,
19060 - Opcode_licw_encode_fns, 0, 0 },
19061 - { "sict", 284 /* xt_iclass_sicx */,
19063 - Opcode_sict_encode_fns, 0, 0 },
19064 - { "sicw", 284 /* xt_iclass_sicx */,
19066 - Opcode_sicw_encode_fns, 0, 0 },
19067 - { "dhwb", 285 /* xt_iclass_dcache */,
19069 - Opcode_dhwb_encode_fns, 0, 0 },
19070 - { "dhwbi", 285 /* xt_iclass_dcache */,
19072 - Opcode_dhwbi_encode_fns, 0, 0 },
19073 - { "diwb", 286 /* xt_iclass_dcache_ind */,
19075 - Opcode_diwb_encode_fns, 0, 0 },
19076 - { "diwbi", 286 /* xt_iclass_dcache_ind */,
19078 - Opcode_diwbi_encode_fns, 0, 0 },
19079 - { "dhi", 287 /* xt_iclass_dcache_inv */,
19081 - Opcode_dhi_encode_fns, 0, 0 },
19082 - { "dii", 287 /* xt_iclass_dcache_inv */,
19084 - Opcode_dii_encode_fns, 0, 0 },
19085 - { "dpfr", 288 /* xt_iclass_dpf */,
19087 - Opcode_dpfr_encode_fns, 0, 0 },
19088 - { "dpfw", 288 /* xt_iclass_dpf */,
19090 - Opcode_dpfw_encode_fns, 0, 0 },
19091 - { "dpfro", 288 /* xt_iclass_dpf */,
19093 - Opcode_dpfro_encode_fns, 0, 0 },
19094 - { "dpfwo", 288 /* xt_iclass_dpf */,
19096 - Opcode_dpfwo_encode_fns, 0, 0 },
19097 - { "dpfl", 289 /* xt_iclass_dcache_lock */,
19099 - Opcode_dpfl_encode_fns, 0, 0 },
19100 - { "dhu", 289 /* xt_iclass_dcache_lock */,
19102 - Opcode_dhu_encode_fns, 0, 0 },
19103 - { "diu", 289 /* xt_iclass_dcache_lock */,
19105 - Opcode_diu_encode_fns, 0, 0 },
19106 - { "sdct", 290 /* xt_iclass_sdct */,
19108 - Opcode_sdct_encode_fns, 0, 0 },
19109 - { "ldct", 291 /* xt_iclass_ldct */,
19111 - Opcode_ldct_encode_fns, 0, 0 },
19112 - { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
19114 - Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
19115 - { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
19117 - Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
19118 - { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
19120 - Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
19121 - { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
19123 - Opcode_rsr_rasid_encode_fns, 0, 0 },
19124 - { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
19126 - Opcode_wsr_rasid_encode_fns, 0, 0 },
19127 - { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
19129 - Opcode_xsr_rasid_encode_fns, 0, 0 },
19130 - { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
19132 - Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
19133 - { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
19135 - Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
19136 - { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
19138 - Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
19139 - { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
19141 - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
19142 - { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
19144 - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
19145 - { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
19147 - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
19148 - { "idtlb", 304 /* xt_iclass_idtlb */,
19150 - Opcode_idtlb_encode_fns, 0, 0 },
19151 - { "pdtlb", 305 /* xt_iclass_rdtlb */,
19153 - Opcode_pdtlb_encode_fns, 0, 0 },
19154 - { "rdtlb0", 305 /* xt_iclass_rdtlb */,
19156 - Opcode_rdtlb0_encode_fns, 0, 0 },
19157 - { "rdtlb1", 305 /* xt_iclass_rdtlb */,
19159 - Opcode_rdtlb1_encode_fns, 0, 0 },
19160 - { "wdtlb", 306 /* xt_iclass_wdtlb */,
19162 - Opcode_wdtlb_encode_fns, 0, 0 },
19163 - { "iitlb", 307 /* xt_iclass_iitlb */,
19165 - Opcode_iitlb_encode_fns, 0, 0 },
19166 - { "pitlb", 308 /* xt_iclass_ritlb */,
19168 - Opcode_pitlb_encode_fns, 0, 0 },
19169 - { "ritlb0", 308 /* xt_iclass_ritlb */,
19171 - Opcode_ritlb0_encode_fns, 0, 0 },
19172 - { "ritlb1", 308 /* xt_iclass_ritlb */,
19174 - Opcode_ritlb1_encode_fns, 0, 0 },
19175 - { "witlb", 309 /* xt_iclass_witlb */,
19177 - Opcode_witlb_encode_fns, 0, 0 },
19178 - { "ldpte", 310 /* xt_iclass_ldpte */,
19180 - Opcode_ldpte_encode_fns, 0, 0 },
19181 - { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
19182 - XTENSA_OPCODE_IS_BRANCH,
19183 - Opcode_hwwitlba_encode_fns, 0, 0 },
19184 - { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
19186 - Opcode_hwwdtlba_encode_fns, 0, 0 },
19187 - { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
19189 - Opcode_rsr_cpenable_encode_fns, 0, 0 },
19190 - { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
19192 - Opcode_wsr_cpenable_encode_fns, 0, 0 },
19193 - { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
19195 - Opcode_xsr_cpenable_encode_fns, 0, 0 },
19196 - { "clamps", 316 /* xt_iclass_clamp */,
19198 - Opcode_clamps_encode_fns, 0, 0 },
19199 - { "min", 317 /* xt_iclass_minmax */,
19201 - Opcode_min_encode_fns, 0, 0 },
19202 - { "max", 317 /* xt_iclass_minmax */,
19204 - Opcode_max_encode_fns, 0, 0 },
19205 - { "minu", 317 /* xt_iclass_minmax */,
19207 - Opcode_minu_encode_fns, 0, 0 },
19208 - { "maxu", 317 /* xt_iclass_minmax */,
19210 - Opcode_maxu_encode_fns, 0, 0 },
19211 - { "nsa", 318 /* xt_iclass_nsa */,
19213 - Opcode_nsa_encode_fns, 0, 0 },
19214 - { "nsau", 318 /* xt_iclass_nsa */,
19216 - Opcode_nsau_encode_fns, 0, 0 },
19217 - { "sext", 319 /* xt_iclass_sx */,
19219 - Opcode_sext_encode_fns, 0, 0 },
19220 - { "l32ai", 320 /* xt_iclass_l32ai */,
19222 - Opcode_l32ai_encode_fns, 0, 0 },
19223 - { "s32ri", 321 /* xt_iclass_s32ri */,
19225 - Opcode_s32ri_encode_fns, 0, 0 },
19226 - { "s32c1i", 322 /* xt_iclass_s32c1i */,
19228 - Opcode_s32c1i_encode_fns, 0, 0 },
19229 - { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
19231 - Opcode_rsr_scompare1_encode_fns, 0, 0 },
19232 - { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
19234 - Opcode_wsr_scompare1_encode_fns, 0, 0 },
19235 - { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
19237 - Opcode_xsr_scompare1_encode_fns, 0, 0 },
19238 - { "quou", 326 /* xt_iclass_div */,
19240 - Opcode_quou_encode_fns, 0, 0 },
19241 - { "quos", 326 /* xt_iclass_div */,
19243 - Opcode_quos_encode_fns, 0, 0 },
19244 - { "remu", 326 /* xt_iclass_div */,
19246 - Opcode_remu_encode_fns, 0, 0 },
19247 - { "rems", 326 /* xt_iclass_div */,
19249 - Opcode_rems_encode_fns, 0, 0 },
19250 - { "mull", 327 /* xt_mul32 */,
19252 - Opcode_mull_encode_fns, 0, 0 },
19253 - { "muluh", 327 /* xt_mul32 */,
19255 - Opcode_muluh_encode_fns, 0, 0 },
19256 - { "mulsh", 327 /* xt_mul32 */,
19258 - Opcode_mulsh_encode_fns, 0, 0 },
19259 - { "rur.fcr", 328 /* rur_fcr */,
19261 - Opcode_rur_fcr_encode_fns, 0, 0 },
19262 - { "wur.fcr", 329 /* wur_fcr */,
19264 - Opcode_wur_fcr_encode_fns, 0, 0 },
19265 - { "rur.fsr", 330 /* rur_fsr */,
19267 - Opcode_rur_fsr_encode_fns, 0, 0 },
19268 - { "wur.fsr", 331 /* wur_fsr */,
19270 - Opcode_wur_fsr_encode_fns, 0, 0 },
19271 - { "add.s", 332 /* fp */,
19273 - Opcode_add_s_encode_fns, 0, 0 },
19274 - { "sub.s", 332 /* fp */,
19276 - Opcode_sub_s_encode_fns, 0, 0 },
19277 - { "mul.s", 332 /* fp */,
19279 - Opcode_mul_s_encode_fns, 0, 0 },
19280 - { "madd.s", 333 /* fp_mac */,
19282 - Opcode_madd_s_encode_fns, 0, 0 },
19283 - { "msub.s", 333 /* fp_mac */,
19285 - Opcode_msub_s_encode_fns, 0, 0 },
19286 - { "movf.s", 334 /* fp_cmov */,
19288 - Opcode_movf_s_encode_fns, 0, 0 },
19289 - { "movt.s", 334 /* fp_cmov */,
19291 - Opcode_movt_s_encode_fns, 0, 0 },
19292 - { "moveqz.s", 335 /* fp_mov */,
19294 - Opcode_moveqz_s_encode_fns, 0, 0 },
19295 - { "movnez.s", 335 /* fp_mov */,
19297 - Opcode_movnez_s_encode_fns, 0, 0 },
19298 - { "movltz.s", 335 /* fp_mov */,
19300 - Opcode_movltz_s_encode_fns, 0, 0 },
19301 - { "movgez.s", 335 /* fp_mov */,
19303 - Opcode_movgez_s_encode_fns, 0, 0 },
19304 - { "abs.s", 336 /* fp_mov2 */,
19306 - Opcode_abs_s_encode_fns, 0, 0 },
19307 - { "mov.s", 336 /* fp_mov2 */,
19309 - Opcode_mov_s_encode_fns, 0, 0 },
19310 - { "neg.s", 336 /* fp_mov2 */,
19312 - Opcode_neg_s_encode_fns, 0, 0 },
19313 - { "un.s", 337 /* fp_cmp */,
19315 - Opcode_un_s_encode_fns, 0, 0 },
19316 - { "oeq.s", 337 /* fp_cmp */,
19318 - Opcode_oeq_s_encode_fns, 0, 0 },
19319 - { "ueq.s", 337 /* fp_cmp */,
19321 - Opcode_ueq_s_encode_fns, 0, 0 },
19322 - { "olt.s", 337 /* fp_cmp */,
19324 - Opcode_olt_s_encode_fns, 0, 0 },
19325 - { "ult.s", 337 /* fp_cmp */,
19327 - Opcode_ult_s_encode_fns, 0, 0 },
19328 - { "ole.s", 337 /* fp_cmp */,
19330 - Opcode_ole_s_encode_fns, 0, 0 },
19331 - { "ule.s", 337 /* fp_cmp */,
19333 - Opcode_ule_s_encode_fns, 0, 0 },
19334 - { "float.s", 338 /* fp_float */,
19336 - Opcode_float_s_encode_fns, 0, 0 },
19337 - { "ufloat.s", 338 /* fp_float */,
19339 - Opcode_ufloat_s_encode_fns, 0, 0 },
19340 - { "round.s", 339 /* fp_int */,
19342 - Opcode_round_s_encode_fns, 0, 0 },
19343 - { "ceil.s", 339 /* fp_int */,
19345 - Opcode_ceil_s_encode_fns, 0, 0 },
19346 - { "floor.s", 339 /* fp_int */,
19348 - Opcode_floor_s_encode_fns, 0, 0 },
19349 - { "trunc.s", 339 /* fp_int */,
19351 - Opcode_trunc_s_encode_fns, 0, 0 },
19352 - { "utrunc.s", 339 /* fp_int */,
19354 - Opcode_utrunc_s_encode_fns, 0, 0 },
19355 - { "rfr", 340 /* fp_rfr */,
19357 - Opcode_rfr_encode_fns, 0, 0 },
19358 - { "wfr", 341 /* fp_wfr */,
19360 - Opcode_wfr_encode_fns, 0, 0 },
19361 - { "lsi", 342 /* fp_lsi */,
19363 - Opcode_lsi_encode_fns, 0, 0 },
19364 - { "lsiu", 343 /* fp_lsiu */,
19366 - Opcode_lsiu_encode_fns, 0, 0 },
19367 - { "lsx", 344 /* fp_lsx */,
19369 - Opcode_lsx_encode_fns, 0, 0 },
19370 - { "lsxu", 345 /* fp_lsxu */,
19372 - Opcode_lsxu_encode_fns, 0, 0 },
19373 - { "ssi", 346 /* fp_ssi */,
19375 - Opcode_ssi_encode_fns, 0, 0 },
19376 - { "ssiu", 347 /* fp_ssiu */,
19378 - Opcode_ssiu_encode_fns, 0, 0 },
19379 - { "ssx", 348 /* fp_ssx */,
19381 - Opcode_ssx_encode_fns, 0, 0 },
19382 - { "ssxu", 349 /* fp_ssxu */,
19384 - Opcode_ssxu_encode_fns, 0, 0 },
19385 - { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
19386 - XTENSA_OPCODE_IS_BRANCH,
19387 - Opcode_beqz_w18_encode_fns, 0, 0 },
19388 - { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
19389 - XTENSA_OPCODE_IS_BRANCH,
19390 - Opcode_bnez_w18_encode_fns, 0, 0 },
19391 - { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
19392 - XTENSA_OPCODE_IS_BRANCH,
19393 - Opcode_bgez_w18_encode_fns, 0, 0 },
19394 - { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
19395 - XTENSA_OPCODE_IS_BRANCH,
19396 - Opcode_bltz_w18_encode_fns, 0, 0 },
19397 - { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
19398 - XTENSA_OPCODE_IS_BRANCH,
19399 - Opcode_beqi_w18_encode_fns, 0, 0 },
19400 - { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
19401 - XTENSA_OPCODE_IS_BRANCH,
19402 - Opcode_bnei_w18_encode_fns, 0, 0 },
19403 - { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
19404 - XTENSA_OPCODE_IS_BRANCH,
19405 - Opcode_bgei_w18_encode_fns, 0, 0 },
19406 - { "blti.w18", 351 /* xt_iclass_wb18_1 */,
19407 - XTENSA_OPCODE_IS_BRANCH,
19408 - Opcode_blti_w18_encode_fns, 0, 0 },
19409 - { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
19410 - XTENSA_OPCODE_IS_BRANCH,
19411 - Opcode_bgeui_w18_encode_fns, 0, 0 },
19412 - { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
19413 - XTENSA_OPCODE_IS_BRANCH,
19414 - Opcode_bltui_w18_encode_fns, 0, 0 },
19415 - { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
19416 - XTENSA_OPCODE_IS_BRANCH,
19417 - Opcode_bbci_w18_encode_fns, 0, 0 },
19418 - { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
19419 - XTENSA_OPCODE_IS_BRANCH,
19420 - Opcode_bbsi_w18_encode_fns, 0, 0 },
19421 - { "beq.w18", 354 /* xt_iclass_wb18_4 */,
19422 - XTENSA_OPCODE_IS_BRANCH,
19423 - Opcode_beq_w18_encode_fns, 0, 0 },
19424 - { "bne.w18", 354 /* xt_iclass_wb18_4 */,
19425 - XTENSA_OPCODE_IS_BRANCH,
19426 - Opcode_bne_w18_encode_fns, 0, 0 },
19427 - { "bge.w18", 354 /* xt_iclass_wb18_4 */,
19428 - XTENSA_OPCODE_IS_BRANCH,
19429 - Opcode_bge_w18_encode_fns, 0, 0 },
19430 - { "blt.w18", 354 /* xt_iclass_wb18_4 */,
19431 - XTENSA_OPCODE_IS_BRANCH,
19432 - Opcode_blt_w18_encode_fns, 0, 0 },
19433 - { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
19434 - XTENSA_OPCODE_IS_BRANCH,
19435 - Opcode_bgeu_w18_encode_fns, 0, 0 },
19436 - { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
19437 - XTENSA_OPCODE_IS_BRANCH,
19438 - Opcode_bltu_w18_encode_fns, 0, 0 },
19439 - { "bany.w18", 354 /* xt_iclass_wb18_4 */,
19440 - XTENSA_OPCODE_IS_BRANCH,
19441 - Opcode_bany_w18_encode_fns, 0, 0 },
19442 - { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
19443 - XTENSA_OPCODE_IS_BRANCH,
19444 - Opcode_bnone_w18_encode_fns, 0, 0 },
19445 - { "ball.w18", 354 /* xt_iclass_wb18_4 */,
19446 - XTENSA_OPCODE_IS_BRANCH,
19447 - Opcode_ball_w18_encode_fns, 0, 0 },
19448 - { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
19449 - XTENSA_OPCODE_IS_BRANCH,
19450 - Opcode_bnall_w18_encode_fns, 0, 0 },
19451 - { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
19452 - XTENSA_OPCODE_IS_BRANCH,
19453 - Opcode_bbc_w18_encode_fns, 0, 0 },
19454 - { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
19455 - XTENSA_OPCODE_IS_BRANCH,
19456 - Opcode_bbs_w18_encode_fns, 0, 0 }
19460 -/* Slot-specific opcode decode functions. */
19463 -Slot_inst_decode (const xtensa_insnbuf insn)
19465 - switch (Field_op0_Slot_inst_get (insn))
19468 - switch (Field_op1_Slot_inst_get (insn))
19471 - switch (Field_op2_Slot_inst_get (insn))
19474 - switch (Field_r_Slot_inst_get (insn))
19477 - switch (Field_m_Slot_inst_get (insn))
19480 - if (Field_s_Slot_inst_get (insn) == 0 &&
19481 - Field_n_Slot_inst_get (insn) == 0)
19482 - return 79; /* ill */
19485 - switch (Field_n_Slot_inst_get (insn))
19488 - return 98; /* ret */
19490 - return 14; /* retw */
19492 - return 81; /* jx */
19496 - switch (Field_n_Slot_inst_get (insn))
19499 - return 77; /* callx0 */
19501 - return 10; /* callx4 */
19503 - return 9; /* callx8 */
19505 - return 8; /* callx12 */
19511 - return 12; /* movsp */
19513 - if (Field_s_Slot_inst_get (insn) == 0)
19515 - switch (Field_t_Slot_inst_get (insn))
19518 - return 116; /* isync */
19520 - return 117; /* rsync */
19522 - return 118; /* esync */
19524 - return 119; /* dsync */
19526 - return 0; /* excw */
19528 - return 114; /* memw */
19530 - return 115; /* extw */
19532 - return 97; /* nop */
19537 - switch (Field_t_Slot_inst_get (insn))
19540 - switch (Field_s_Slot_inst_get (insn))
19543 - return 1; /* rfe */
19545 - return 2; /* rfde */
19547 - return 16; /* rfwo */
19549 - return 17; /* rfwu */
19553 - return 316; /* rfi */
19557 - return 324; /* break */
19559 - switch (Field_s_Slot_inst_get (insn))
19562 - if (Field_t_Slot_inst_get (insn) == 0)
19563 - return 3; /* syscall */
19566 - if (Field_t_Slot_inst_get (insn) == 0)
19567 - return 4; /* simcall */
19572 - return 120; /* rsil */
19574 - if (Field_t_Slot_inst_get (insn) == 0)
19575 - return 317; /* waiti */
19578 - return 367; /* any4 */
19580 - return 368; /* all4 */
19582 - return 369; /* any8 */
19584 - return 370; /* all8 */
19588 - return 49; /* and */
19590 - return 50; /* or */
19592 - return 51; /* xor */
19594 - switch (Field_r_Slot_inst_get (insn))
19597 - if (Field_t_Slot_inst_get (insn) == 0)
19598 - return 102; /* ssr */
19601 - if (Field_t_Slot_inst_get (insn) == 0)
19602 - return 103; /* ssl */
19605 - if (Field_t_Slot_inst_get (insn) == 0)
19606 - return 104; /* ssa8l */
19609 - if (Field_t_Slot_inst_get (insn) == 0)
19610 - return 105; /* ssa8b */
19613 - if (Field_thi3_Slot_inst_get (insn) == 0)
19614 - return 106; /* ssai */
19617 - if (Field_s_Slot_inst_get (insn) == 0)
19618 - return 13; /* rotw */
19621 - return 448; /* nsa */
19623 - return 449; /* nsau */
19627 - switch (Field_r_Slot_inst_get (insn))
19630 - return 438; /* hwwitlba */
19632 - return 434; /* ritlb0 */
19634 - if (Field_t_Slot_inst_get (insn) == 0)
19635 - return 432; /* iitlb */
19638 - return 433; /* pitlb */
19640 - return 436; /* witlb */
19642 - return 435; /* ritlb1 */
19644 - return 439; /* hwwdtlba */
19646 - return 429; /* rdtlb0 */
19648 - if (Field_t_Slot_inst_get (insn) == 0)
19649 - return 427; /* idtlb */
19652 - return 428; /* pdtlb */
19654 - return 431; /* wdtlb */
19656 - return 430; /* rdtlb1 */
19660 - switch (Field_s_Slot_inst_get (insn))
19663 - return 95; /* neg */
19665 - return 96; /* abs */
19669 - return 41; /* add */
19671 - return 43; /* addx2 */
19673 - return 44; /* addx4 */
19675 - return 45; /* addx8 */
19677 - return 42; /* sub */
19679 - return 46; /* subx2 */
19681 - return 47; /* subx4 */
19683 - return 48; /* subx8 */
19687 - switch (Field_op2_Slot_inst_get (insn))
19691 - return 111; /* slli */
19694 - return 112; /* srai */
19696 - return 113; /* srli */
19698 - switch (Field_sr_Slot_inst_get (insn))
19701 - return 129; /* xsr.lbeg */
19703 - return 123; /* xsr.lend */
19705 - return 126; /* xsr.lcount */
19707 - return 132; /* xsr.sar */
19709 - return 377; /* xsr.br */
19711 - return 135; /* xsr.litbase */
19713 - return 456; /* xsr.scompare1 */
19715 - return 312; /* xsr.acclo */
19717 - return 315; /* xsr.acchi */
19719 - return 300; /* xsr.m0 */
19721 - return 303; /* xsr.m1 */
19723 - return 306; /* xsr.m2 */
19725 - return 309; /* xsr.m3 */
19727 - return 22; /* xsr.windowbase */
19729 - return 25; /* xsr.windowstart */
19731 - return 417; /* xsr.ptevaddr */
19733 - return 420; /* xsr.rasid */
19735 - return 423; /* xsr.itlbcfg */
19737 - return 426; /* xsr.dtlbcfg */
19739 - return 346; /* xsr.ibreakenable */
19741 - return 358; /* xsr.ddr */
19743 - return 340; /* xsr.ibreaka0 */
19745 - return 343; /* xsr.ibreaka1 */
19747 - return 328; /* xsr.dbreaka0 */
19749 - return 334; /* xsr.dbreaka1 */
19751 - return 331; /* xsr.dbreakc0 */
19753 - return 337; /* xsr.dbreakc1 */
19755 - return 143; /* xsr.epc1 */
19757 - return 149; /* xsr.epc2 */
19759 - return 155; /* xsr.epc3 */
19761 - return 161; /* xsr.epc4 */
19763 - return 167; /* xsr.epc5 */
19765 - return 173; /* xsr.epc6 */
19767 - return 179; /* xsr.epc7 */
19769 - return 206; /* xsr.depc */
19771 - return 185; /* xsr.eps2 */
19773 - return 188; /* xsr.eps3 */
19775 - return 191; /* xsr.eps4 */
19777 - return 194; /* xsr.eps5 */
19779 - return 197; /* xsr.eps6 */
19781 - return 200; /* xsr.eps7 */
19783 - return 146; /* xsr.excsave1 */
19785 - return 152; /* xsr.excsave2 */
19787 - return 158; /* xsr.excsave3 */
19789 - return 164; /* xsr.excsave4 */
19791 - return 170; /* xsr.excsave5 */
19793 - return 176; /* xsr.excsave6 */
19795 - return 182; /* xsr.excsave7 */
19797 - return 442; /* xsr.cpenable */
19799 - return 323; /* xsr.intenable */
19801 - return 140; /* xsr.ps */
19803 - return 225; /* xsr.vecbase */
19805 - return 209; /* xsr.exccause */
19807 - return 349; /* xsr.debugcause */
19809 - return 380; /* xsr.ccount */
19811 - return 352; /* xsr.icount */
19813 - return 355; /* xsr.icountlevel */
19815 - return 203; /* xsr.excvaddr */
19817 - return 383; /* xsr.ccompare0 */
19819 - return 386; /* xsr.ccompare1 */
19821 - return 389; /* xsr.ccompare2 */
19823 - return 212; /* xsr.misc0 */
19825 - return 215; /* xsr.misc1 */
19827 - return 218; /* xsr.misc2 */
19829 - return 221; /* xsr.misc3 */
19833 - return 108; /* src */
19835 - if (Field_s_Slot_inst_get (insn) == 0)
19836 - return 109; /* srl */
19839 - if (Field_t_Slot_inst_get (insn) == 0)
19840 - return 107; /* sll */
19843 - if (Field_s_Slot_inst_get (insn) == 0)
19844 - return 110; /* sra */
19847 - return 296; /* mul16u */
19849 - return 297; /* mul16s */
19851 - switch (Field_r_Slot_inst_get (insn))
19854 - return 396; /* lict */
19856 - return 398; /* sict */
19858 - return 397; /* licw */
19860 - return 399; /* sicw */
19862 - return 414; /* ldct */
19864 - return 413; /* sdct */
19866 - if (Field_t_Slot_inst_get (insn) == 0)
19867 - return 359; /* rfdo */
19868 - if (Field_t_Slot_inst_get (insn) == 1)
19869 - return 360; /* rfdd */
19872 - return 437; /* ldpte */
19878 - switch (Field_op2_Slot_inst_get (insn))
19881 - return 362; /* andb */
19883 - return 363; /* andbc */
19885 - return 364; /* orb */
19887 - return 365; /* orbc */
19889 - return 366; /* xorb */
19891 - return 461; /* mull */
19893 - return 462; /* muluh */
19895 - return 463; /* mulsh */
19897 - return 457; /* quou */
19899 - return 458; /* quos */
19901 - return 459; /* remu */
19903 - return 460; /* rems */
19907 - switch (Field_op2_Slot_inst_get (insn))
19910 - switch (Field_sr_Slot_inst_get (insn))
19913 - return 127; /* rsr.lbeg */
19915 - return 121; /* rsr.lend */
19917 - return 124; /* rsr.lcount */
19919 - return 130; /* rsr.sar */
19921 - return 375; /* rsr.br */
19923 - return 133; /* rsr.litbase */
19925 - return 454; /* rsr.scompare1 */
19927 - return 310; /* rsr.acclo */
19929 - return 313; /* rsr.acchi */
19931 - return 298; /* rsr.m0 */
19933 - return 301; /* rsr.m1 */
19935 - return 304; /* rsr.m2 */
19937 - return 307; /* rsr.m3 */
19939 - return 20; /* rsr.windowbase */
19941 - return 23; /* rsr.windowstart */
19943 - return 416; /* rsr.ptevaddr */
19945 - return 418; /* rsr.rasid */
19947 - return 421; /* rsr.itlbcfg */
19949 - return 424; /* rsr.dtlbcfg */
19951 - return 344; /* rsr.ibreakenable */
19953 - return 356; /* rsr.ddr */
19955 - return 338; /* rsr.ibreaka0 */
19957 - return 341; /* rsr.ibreaka1 */
19959 - return 326; /* rsr.dbreaka0 */
19961 - return 332; /* rsr.dbreaka1 */
19963 - return 329; /* rsr.dbreakc0 */
19965 - return 335; /* rsr.dbreakc1 */
19967 - return 136; /* rsr.176 */
19969 - return 141; /* rsr.epc1 */
19971 - return 147; /* rsr.epc2 */
19973 - return 153; /* rsr.epc3 */
19975 - return 159; /* rsr.epc4 */
19977 - return 165; /* rsr.epc5 */
19979 - return 171; /* rsr.epc6 */
19981 - return 177; /* rsr.epc7 */
19983 - return 204; /* rsr.depc */
19985 - return 183; /* rsr.eps2 */
19987 - return 186; /* rsr.eps3 */
19989 - return 189; /* rsr.eps4 */
19991 - return 192; /* rsr.eps5 */
19993 - return 195; /* rsr.eps6 */
19995 - return 198; /* rsr.eps7 */
19997 - return 137; /* rsr.208 */
19999 - return 144; /* rsr.excsave1 */
20001 - return 150; /* rsr.excsave2 */
20003 - return 156; /* rsr.excsave3 */
20005 - return 162; /* rsr.excsave4 */
20007 - return 168; /* rsr.excsave5 */
20009 - return 174; /* rsr.excsave6 */
20011 - return 180; /* rsr.excsave7 */
20013 - return 440; /* rsr.cpenable */
20015 - return 318; /* rsr.interrupt */
20017 - return 321; /* rsr.intenable */
20019 - return 138; /* rsr.ps */
20021 - return 223; /* rsr.vecbase */
20023 - return 207; /* rsr.exccause */
20025 - return 347; /* rsr.debugcause */
20027 - return 378; /* rsr.ccount */
20029 - return 222; /* rsr.prid */
20031 - return 350; /* rsr.icount */
20033 - return 353; /* rsr.icountlevel */
20035 - return 201; /* rsr.excvaddr */
20037 - return 381; /* rsr.ccompare0 */
20039 - return 384; /* rsr.ccompare1 */
20041 - return 387; /* rsr.ccompare2 */
20043 - return 210; /* rsr.misc0 */
20045 - return 213; /* rsr.misc1 */
20047 - return 216; /* rsr.misc2 */
20049 - return 219; /* rsr.misc3 */
20053 - switch (Field_sr_Slot_inst_get (insn))
20056 - return 128; /* wsr.lbeg */
20058 - return 122; /* wsr.lend */
20060 - return 125; /* wsr.lcount */
20062 - return 131; /* wsr.sar */
20064 - return 376; /* wsr.br */
20066 - return 134; /* wsr.litbase */
20068 - return 455; /* wsr.scompare1 */
20070 - return 311; /* wsr.acclo */
20072 - return 314; /* wsr.acchi */
20074 - return 299; /* wsr.m0 */
20076 - return 302; /* wsr.m1 */
20078 - return 305; /* wsr.m2 */
20080 - return 308; /* wsr.m3 */
20082 - return 21; /* wsr.windowbase */
20084 - return 24; /* wsr.windowstart */
20086 - return 415; /* wsr.ptevaddr */
20088 - return 361; /* wsr.mmid */
20090 - return 419; /* wsr.rasid */
20092 - return 422; /* wsr.itlbcfg */
20094 - return 425; /* wsr.dtlbcfg */
20096 - return 345; /* wsr.ibreakenable */
20098 - return 357; /* wsr.ddr */
20100 - return 339; /* wsr.ibreaka0 */
20102 - return 342; /* wsr.ibreaka1 */
20104 - return 327; /* wsr.dbreaka0 */
20106 - return 333; /* wsr.dbreaka1 */
20108 - return 330; /* wsr.dbreakc0 */
20110 - return 336; /* wsr.dbreakc1 */
20112 - return 142; /* wsr.epc1 */
20114 - return 148; /* wsr.epc2 */
20116 - return 154; /* wsr.epc3 */
20118 - return 160; /* wsr.epc4 */
20120 - return 166; /* wsr.epc5 */
20122 - return 172; /* wsr.epc6 */
20124 - return 178; /* wsr.epc7 */
20126 - return 205; /* wsr.depc */
20128 - return 184; /* wsr.eps2 */
20130 - return 187; /* wsr.eps3 */
20132 - return 190; /* wsr.eps4 */
20134 - return 193; /* wsr.eps5 */
20136 - return 196; /* wsr.eps6 */
20138 - return 199; /* wsr.eps7 */
20140 - return 145; /* wsr.excsave1 */
20142 - return 151; /* wsr.excsave2 */
20144 - return 157; /* wsr.excsave3 */
20146 - return 163; /* wsr.excsave4 */
20148 - return 169; /* wsr.excsave5 */
20150 - return 175; /* wsr.excsave6 */
20152 - return 181; /* wsr.excsave7 */
20154 - return 441; /* wsr.cpenable */
20156 - return 319; /* wsr.intset */
20158 - return 320; /* wsr.intclear */
20160 - return 322; /* wsr.intenable */
20162 - return 139; /* wsr.ps */
20164 - return 224; /* wsr.vecbase */
20166 - return 208; /* wsr.exccause */
20168 - return 348; /* wsr.debugcause */
20170 - return 379; /* wsr.ccount */
20172 - return 351; /* wsr.icount */
20174 - return 354; /* wsr.icountlevel */
20176 - return 202; /* wsr.excvaddr */
20178 - return 382; /* wsr.ccompare0 */
20180 - return 385; /* wsr.ccompare1 */
20182 - return 388; /* wsr.ccompare2 */
20184 - return 211; /* wsr.misc0 */
20186 - return 214; /* wsr.misc1 */
20188 - return 217; /* wsr.misc2 */
20190 - return 220; /* wsr.misc3 */
20194 - return 450; /* sext */
20196 - return 443; /* clamps */
20198 - return 444; /* min */
20200 - return 445; /* max */
20202 - return 446; /* minu */
20204 - return 447; /* maxu */
20206 - return 91; /* moveqz */
20208 - return 92; /* movnez */
20210 - return 93; /* movltz */
20212 - return 94; /* movgez */
20214 - return 373; /* movf */
20216 - return 374; /* movt */
20218 - switch (Field_st_Slot_inst_get (insn))
20221 - return 37; /* rur.threadptr */
20223 - return 464; /* rur.fcr */
20225 - return 466; /* rur.fsr */
20229 - switch (Field_sr_Slot_inst_get (insn))
20232 - return 38; /* wur.threadptr */
20234 - return 465; /* wur.fcr */
20236 - return 467; /* wur.fsr */
20243 - return 78; /* extui */
20245 - switch (Field_op2_Slot_inst_get (insn))
20248 - return 500; /* lsx */
20250 - return 501; /* lsxu */
20252 - return 504; /* ssx */
20254 - return 505; /* ssxu */
20258 - switch (Field_op2_Slot_inst_get (insn))
20261 - return 18; /* l32e */
20263 - return 19; /* s32e */
20267 - switch (Field_op2_Slot_inst_get (insn))
20270 - return 468; /* add.s */
20272 - return 469; /* sub.s */
20274 - return 470; /* mul.s */
20276 - return 471; /* madd.s */
20278 - return 472; /* msub.s */
20280 - return 491; /* round.s */
20282 - return 494; /* trunc.s */
20284 - return 493; /* floor.s */
20286 - return 492; /* ceil.s */
20288 - return 489; /* float.s */
20290 - return 490; /* ufloat.s */
20292 - return 495; /* utrunc.s */
20294 - switch (Field_t_Slot_inst_get (insn))
20297 - return 480; /* mov.s */
20299 - return 479; /* abs.s */
20301 - return 496; /* rfr */
20303 - return 497; /* wfr */
20305 - return 481; /* neg.s */
20311 - switch (Field_op2_Slot_inst_get (insn))
20314 - return 482; /* un.s */
20316 - return 483; /* oeq.s */
20318 - return 484; /* ueq.s */
20320 - return 485; /* olt.s */
20322 - return 486; /* ult.s */
20324 - return 487; /* ole.s */
20326 - return 488; /* ule.s */
20328 - return 475; /* moveqz.s */
20330 - return 476; /* movnez.s */
20332 - return 477; /* movltz.s */
20334 - return 478; /* movgez.s */
20336 - return 473; /* movf.s */
20338 - return 474; /* movt.s */
20344 - return 85; /* l32r */
20346 - switch (Field_r_Slot_inst_get (insn))
20349 - return 86; /* l8ui */
20351 - return 82; /* l16ui */
20353 - return 84; /* l32i */
20355 - return 101; /* s8i */
20357 - return 99; /* s16i */
20359 - return 100; /* s32i */
20361 - switch (Field_t_Slot_inst_get (insn))
20364 - return 406; /* dpfr */
20366 - return 407; /* dpfw */
20368 - return 408; /* dpfro */
20370 - return 409; /* dpfwo */
20372 - return 400; /* dhwb */
20374 - return 401; /* dhwbi */
20376 - return 404; /* dhi */
20378 - return 405; /* dii */
20380 - switch (Field_op1_Slot_inst_get (insn))
20383 - return 410; /* dpfl */
20385 - return 411; /* dhu */
20387 - return 412; /* diu */
20389 - return 402; /* diwb */
20391 - return 403; /* diwbi */
20395 - return 390; /* ipf */
20397 - switch (Field_op1_Slot_inst_get (insn))
20400 - return 392; /* ipfl */
20402 - return 393; /* ihu */
20404 - return 394; /* iiu */
20408 - return 391; /* ihi */
20410 - return 395; /* iii */
20414 - return 83; /* l16si */
20416 - return 90; /* movi */
20418 - return 451; /* l32ai */
20420 - return 39; /* addi */
20422 - return 40; /* addmi */
20424 - return 453; /* s32c1i */
20426 - return 452; /* s32ri */
20430 - switch (Field_r_Slot_inst_get (insn))
20433 - return 498; /* lsi */
20435 - return 502; /* ssi */
20437 - return 499; /* lsiu */
20439 - return 503; /* ssiu */
20443 - switch (Field_op2_Slot_inst_get (insn))
20446 - switch (Field_op1_Slot_inst_get (insn))
20449 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20450 - Field_tlo_Slot_inst_get (insn) == 0 &&
20451 - Field_r3_Slot_inst_get (insn) == 0)
20452 - return 287; /* mula.dd.ll.ldinc */
20455 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20456 - Field_tlo_Slot_inst_get (insn) == 0 &&
20457 - Field_r3_Slot_inst_get (insn) == 0)
20458 - return 289; /* mula.dd.hl.ldinc */
20461 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20462 - Field_tlo_Slot_inst_get (insn) == 0 &&
20463 - Field_r3_Slot_inst_get (insn) == 0)
20464 - return 291; /* mula.dd.lh.ldinc */
20467 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20468 - Field_tlo_Slot_inst_get (insn) == 0 &&
20469 - Field_r3_Slot_inst_get (insn) == 0)
20470 - return 293; /* mula.dd.hh.ldinc */
20475 - switch (Field_op1_Slot_inst_get (insn))
20478 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20479 - Field_tlo_Slot_inst_get (insn) == 0 &&
20480 - Field_r3_Slot_inst_get (insn) == 0)
20481 - return 286; /* mula.dd.ll.lddec */
20484 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20485 - Field_tlo_Slot_inst_get (insn) == 0 &&
20486 - Field_r3_Slot_inst_get (insn) == 0)
20487 - return 288; /* mula.dd.hl.lddec */
20490 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20491 - Field_tlo_Slot_inst_get (insn) == 0 &&
20492 - Field_r3_Slot_inst_get (insn) == 0)
20493 - return 290; /* mula.dd.lh.lddec */
20496 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20497 - Field_tlo_Slot_inst_get (insn) == 0 &&
20498 - Field_r3_Slot_inst_get (insn) == 0)
20499 - return 292; /* mula.dd.hh.lddec */
20504 - switch (Field_op1_Slot_inst_get (insn))
20507 - if (Field_s_Slot_inst_get (insn) == 0 &&
20508 - Field_w_Slot_inst_get (insn) == 0 &&
20509 - Field_r3_Slot_inst_get (insn) == 0 &&
20510 - Field_t3_Slot_inst_get (insn) == 0 &&
20511 - Field_tlo_Slot_inst_get (insn) == 0)
20512 - return 242; /* mul.dd.ll */
20515 - if (Field_s_Slot_inst_get (insn) == 0 &&
20516 - Field_w_Slot_inst_get (insn) == 0 &&
20517 - Field_r3_Slot_inst_get (insn) == 0 &&
20518 - Field_t3_Slot_inst_get (insn) == 0 &&
20519 - Field_tlo_Slot_inst_get (insn) == 0)
20520 - return 243; /* mul.dd.hl */
20523 - if (Field_s_Slot_inst_get (insn) == 0 &&
20524 - Field_w_Slot_inst_get (insn) == 0 &&
20525 - Field_r3_Slot_inst_get (insn) == 0 &&
20526 - Field_t3_Slot_inst_get (insn) == 0 &&
20527 - Field_tlo_Slot_inst_get (insn) == 0)
20528 - return 244; /* mul.dd.lh */
20531 - if (Field_s_Slot_inst_get (insn) == 0 &&
20532 - Field_w_Slot_inst_get (insn) == 0 &&
20533 - Field_r3_Slot_inst_get (insn) == 0 &&
20534 - Field_t3_Slot_inst_get (insn) == 0 &&
20535 - Field_tlo_Slot_inst_get (insn) == 0)
20536 - return 245; /* mul.dd.hh */
20539 - if (Field_s_Slot_inst_get (insn) == 0 &&
20540 - Field_w_Slot_inst_get (insn) == 0 &&
20541 - Field_r3_Slot_inst_get (insn) == 0 &&
20542 - Field_t3_Slot_inst_get (insn) == 0 &&
20543 - Field_tlo_Slot_inst_get (insn) == 0)
20544 - return 270; /* mula.dd.ll */
20547 - if (Field_s_Slot_inst_get (insn) == 0 &&
20548 - Field_w_Slot_inst_get (insn) == 0 &&
20549 - Field_r3_Slot_inst_get (insn) == 0 &&
20550 - Field_t3_Slot_inst_get (insn) == 0 &&
20551 - Field_tlo_Slot_inst_get (insn) == 0)
20552 - return 271; /* mula.dd.hl */
20555 - if (Field_s_Slot_inst_get (insn) == 0 &&
20556 - Field_w_Slot_inst_get (insn) == 0 &&
20557 - Field_r3_Slot_inst_get (insn) == 0 &&
20558 - Field_t3_Slot_inst_get (insn) == 0 &&
20559 - Field_tlo_Slot_inst_get (insn) == 0)
20560 - return 272; /* mula.dd.lh */
20563 - if (Field_s_Slot_inst_get (insn) == 0 &&
20564 - Field_w_Slot_inst_get (insn) == 0 &&
20565 - Field_r3_Slot_inst_get (insn) == 0 &&
20566 - Field_t3_Slot_inst_get (insn) == 0 &&
20567 - Field_tlo_Slot_inst_get (insn) == 0)
20568 - return 273; /* mula.dd.hh */
20571 - if (Field_s_Slot_inst_get (insn) == 0 &&
20572 - Field_w_Slot_inst_get (insn) == 0 &&
20573 - Field_r3_Slot_inst_get (insn) == 0 &&
20574 - Field_t3_Slot_inst_get (insn) == 0 &&
20575 - Field_tlo_Slot_inst_get (insn) == 0)
20576 - return 274; /* muls.dd.ll */
20579 - if (Field_s_Slot_inst_get (insn) == 0 &&
20580 - Field_w_Slot_inst_get (insn) == 0 &&
20581 - Field_r3_Slot_inst_get (insn) == 0 &&
20582 - Field_t3_Slot_inst_get (insn) == 0 &&
20583 - Field_tlo_Slot_inst_get (insn) == 0)
20584 - return 275; /* muls.dd.hl */
20587 - if (Field_s_Slot_inst_get (insn) == 0 &&
20588 - Field_w_Slot_inst_get (insn) == 0 &&
20589 - Field_r3_Slot_inst_get (insn) == 0 &&
20590 - Field_t3_Slot_inst_get (insn) == 0 &&
20591 - Field_tlo_Slot_inst_get (insn) == 0)
20592 - return 276; /* muls.dd.lh */
20595 - if (Field_s_Slot_inst_get (insn) == 0 &&
20596 - Field_w_Slot_inst_get (insn) == 0 &&
20597 - Field_r3_Slot_inst_get (insn) == 0 &&
20598 - Field_t3_Slot_inst_get (insn) == 0 &&
20599 - Field_tlo_Slot_inst_get (insn) == 0)
20600 - return 277; /* muls.dd.hh */
20605 - switch (Field_op1_Slot_inst_get (insn))
20608 - if (Field_r_Slot_inst_get (insn) == 0 &&
20609 - Field_t3_Slot_inst_get (insn) == 0 &&
20610 - Field_tlo_Slot_inst_get (insn) == 0)
20611 - return 234; /* mul.ad.ll */
20614 - if (Field_r_Slot_inst_get (insn) == 0 &&
20615 - Field_t3_Slot_inst_get (insn) == 0 &&
20616 - Field_tlo_Slot_inst_get (insn) == 0)
20617 - return 235; /* mul.ad.hl */
20620 - if (Field_r_Slot_inst_get (insn) == 0 &&
20621 - Field_t3_Slot_inst_get (insn) == 0 &&
20622 - Field_tlo_Slot_inst_get (insn) == 0)
20623 - return 236; /* mul.ad.lh */
20626 - if (Field_r_Slot_inst_get (insn) == 0 &&
20627 - Field_t3_Slot_inst_get (insn) == 0 &&
20628 - Field_tlo_Slot_inst_get (insn) == 0)
20629 - return 237; /* mul.ad.hh */
20632 - if (Field_r_Slot_inst_get (insn) == 0 &&
20633 - Field_t3_Slot_inst_get (insn) == 0 &&
20634 - Field_tlo_Slot_inst_get (insn) == 0)
20635 - return 254; /* mula.ad.ll */
20638 - if (Field_r_Slot_inst_get (insn) == 0 &&
20639 - Field_t3_Slot_inst_get (insn) == 0 &&
20640 - Field_tlo_Slot_inst_get (insn) == 0)
20641 - return 255; /* mula.ad.hl */
20644 - if (Field_r_Slot_inst_get (insn) == 0 &&
20645 - Field_t3_Slot_inst_get (insn) == 0 &&
20646 - Field_tlo_Slot_inst_get (insn) == 0)
20647 - return 256; /* mula.ad.lh */
20650 - if (Field_r_Slot_inst_get (insn) == 0 &&
20651 - Field_t3_Slot_inst_get (insn) == 0 &&
20652 - Field_tlo_Slot_inst_get (insn) == 0)
20653 - return 257; /* mula.ad.hh */
20656 - if (Field_r_Slot_inst_get (insn) == 0 &&
20657 - Field_t3_Slot_inst_get (insn) == 0 &&
20658 - Field_tlo_Slot_inst_get (insn) == 0)
20659 - return 258; /* muls.ad.ll */
20662 - if (Field_r_Slot_inst_get (insn) == 0 &&
20663 - Field_t3_Slot_inst_get (insn) == 0 &&
20664 - Field_tlo_Slot_inst_get (insn) == 0)
20665 - return 259; /* muls.ad.hl */
20668 - if (Field_r_Slot_inst_get (insn) == 0 &&
20669 - Field_t3_Slot_inst_get (insn) == 0 &&
20670 - Field_tlo_Slot_inst_get (insn) == 0)
20671 - return 260; /* muls.ad.lh */
20674 - if (Field_r_Slot_inst_get (insn) == 0 &&
20675 - Field_t3_Slot_inst_get (insn) == 0 &&
20676 - Field_tlo_Slot_inst_get (insn) == 0)
20677 - return 261; /* muls.ad.hh */
20682 - switch (Field_op1_Slot_inst_get (insn))
20685 - if (Field_r3_Slot_inst_get (insn) == 0)
20686 - return 279; /* mula.da.ll.ldinc */
20689 - if (Field_r3_Slot_inst_get (insn) == 0)
20690 - return 281; /* mula.da.hl.ldinc */
20693 - if (Field_r3_Slot_inst_get (insn) == 0)
20694 - return 283; /* mula.da.lh.ldinc */
20697 - if (Field_r3_Slot_inst_get (insn) == 0)
20698 - return 285; /* mula.da.hh.ldinc */
20703 - switch (Field_op1_Slot_inst_get (insn))
20706 - if (Field_r3_Slot_inst_get (insn) == 0)
20707 - return 278; /* mula.da.ll.lddec */
20710 - if (Field_r3_Slot_inst_get (insn) == 0)
20711 - return 280; /* mula.da.hl.lddec */
20714 - if (Field_r3_Slot_inst_get (insn) == 0)
20715 - return 282; /* mula.da.lh.lddec */
20718 - if (Field_r3_Slot_inst_get (insn) == 0)
20719 - return 284; /* mula.da.hh.lddec */
20724 - switch (Field_op1_Slot_inst_get (insn))
20727 - if (Field_s_Slot_inst_get (insn) == 0 &&
20728 - Field_w_Slot_inst_get (insn) == 0 &&
20729 - Field_r3_Slot_inst_get (insn) == 0)
20730 - return 238; /* mul.da.ll */
20733 - if (Field_s_Slot_inst_get (insn) == 0 &&
20734 - Field_w_Slot_inst_get (insn) == 0 &&
20735 - Field_r3_Slot_inst_get (insn) == 0)
20736 - return 239; /* mul.da.hl */
20739 - if (Field_s_Slot_inst_get (insn) == 0 &&
20740 - Field_w_Slot_inst_get (insn) == 0 &&
20741 - Field_r3_Slot_inst_get (insn) == 0)
20742 - return 240; /* mul.da.lh */
20745 - if (Field_s_Slot_inst_get (insn) == 0 &&
20746 - Field_w_Slot_inst_get (insn) == 0 &&
20747 - Field_r3_Slot_inst_get (insn) == 0)
20748 - return 241; /* mul.da.hh */
20751 - if (Field_s_Slot_inst_get (insn) == 0 &&
20752 - Field_w_Slot_inst_get (insn) == 0 &&
20753 - Field_r3_Slot_inst_get (insn) == 0)
20754 - return 262; /* mula.da.ll */
20757 - if (Field_s_Slot_inst_get (insn) == 0 &&
20758 - Field_w_Slot_inst_get (insn) == 0 &&
20759 - Field_r3_Slot_inst_get (insn) == 0)
20760 - return 263; /* mula.da.hl */
20763 - if (Field_s_Slot_inst_get (insn) == 0 &&
20764 - Field_w_Slot_inst_get (insn) == 0 &&
20765 - Field_r3_Slot_inst_get (insn) == 0)
20766 - return 264; /* mula.da.lh */
20769 - if (Field_s_Slot_inst_get (insn) == 0 &&
20770 - Field_w_Slot_inst_get (insn) == 0 &&
20771 - Field_r3_Slot_inst_get (insn) == 0)
20772 - return 265; /* mula.da.hh */
20775 - if (Field_s_Slot_inst_get (insn) == 0 &&
20776 - Field_w_Slot_inst_get (insn) == 0 &&
20777 - Field_r3_Slot_inst_get (insn) == 0)
20778 - return 266; /* muls.da.ll */
20781 - if (Field_s_Slot_inst_get (insn) == 0 &&
20782 - Field_w_Slot_inst_get (insn) == 0 &&
20783 - Field_r3_Slot_inst_get (insn) == 0)
20784 - return 267; /* muls.da.hl */
20787 - if (Field_s_Slot_inst_get (insn) == 0 &&
20788 - Field_w_Slot_inst_get (insn) == 0 &&
20789 - Field_r3_Slot_inst_get (insn) == 0)
20790 - return 268; /* muls.da.lh */
20793 - if (Field_s_Slot_inst_get (insn) == 0 &&
20794 - Field_w_Slot_inst_get (insn) == 0 &&
20795 - Field_r3_Slot_inst_get (insn) == 0)
20796 - return 269; /* muls.da.hh */
20801 - switch (Field_op1_Slot_inst_get (insn))
20804 - if (Field_r_Slot_inst_get (insn) == 0)
20805 - return 230; /* umul.aa.ll */
20808 - if (Field_r_Slot_inst_get (insn) == 0)
20809 - return 231; /* umul.aa.hl */
20812 - if (Field_r_Slot_inst_get (insn) == 0)
20813 - return 232; /* umul.aa.lh */
20816 - if (Field_r_Slot_inst_get (insn) == 0)
20817 - return 233; /* umul.aa.hh */
20820 - if (Field_r_Slot_inst_get (insn) == 0)
20821 - return 226; /* mul.aa.ll */
20824 - if (Field_r_Slot_inst_get (insn) == 0)
20825 - return 227; /* mul.aa.hl */
20828 - if (Field_r_Slot_inst_get (insn) == 0)
20829 - return 228; /* mul.aa.lh */
20832 - if (Field_r_Slot_inst_get (insn) == 0)
20833 - return 229; /* mul.aa.hh */
20836 - if (Field_r_Slot_inst_get (insn) == 0)
20837 - return 246; /* mula.aa.ll */
20840 - if (Field_r_Slot_inst_get (insn) == 0)
20841 - return 247; /* mula.aa.hl */
20844 - if (Field_r_Slot_inst_get (insn) == 0)
20845 - return 248; /* mula.aa.lh */
20848 - if (Field_r_Slot_inst_get (insn) == 0)
20849 - return 249; /* mula.aa.hh */
20852 - if (Field_r_Slot_inst_get (insn) == 0)
20853 - return 250; /* muls.aa.ll */
20856 - if (Field_r_Slot_inst_get (insn) == 0)
20857 - return 251; /* muls.aa.hl */
20860 - if (Field_r_Slot_inst_get (insn) == 0)
20861 - return 252; /* muls.aa.lh */
20864 - if (Field_r_Slot_inst_get (insn) == 0)
20865 - return 253; /* muls.aa.hh */
20870 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20871 - Field_t_Slot_inst_get (insn) == 0 &&
20872 - Field_rhi_Slot_inst_get (insn) == 0)
20873 - return 295; /* ldinc */
20876 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20877 - Field_t_Slot_inst_get (insn) == 0 &&
20878 - Field_rhi_Slot_inst_get (insn) == 0)
20879 - return 294; /* lddec */
20884 - switch (Field_n_Slot_inst_get (insn))
20887 - return 76; /* call0 */
20889 - return 7; /* call4 */
20891 - return 6; /* call8 */
20893 - return 5; /* call12 */
20897 - switch (Field_n_Slot_inst_get (insn))
20900 - return 80; /* j */
20902 - switch (Field_m_Slot_inst_get (insn))
20905 - return 72; /* beqz */
20907 - return 73; /* bnez */
20909 - return 75; /* bltz */
20911 - return 74; /* bgez */
20915 - switch (Field_m_Slot_inst_get (insn))
20918 - return 52; /* beqi */
20920 - return 53; /* bnei */
20922 - return 55; /* blti */
20924 - return 54; /* bgei */
20928 - switch (Field_m_Slot_inst_get (insn))
20931 - return 11; /* entry */
20933 - switch (Field_r_Slot_inst_get (insn))
20936 - return 371; /* bf */
20938 - return 372; /* bt */
20940 - return 87; /* loop */
20942 - return 88; /* loopnez */
20944 - return 89; /* loopgtz */
20948 - return 59; /* bltui */
20950 - return 58; /* bgeui */
20956 - switch (Field_r_Slot_inst_get (insn))
20959 - return 67; /* bnone */
20961 - return 60; /* beq */
20963 - return 63; /* blt */
20965 - return 65; /* bltu */
20967 - return 68; /* ball */
20969 - return 70; /* bbc */
20972 - return 56; /* bbci */
20974 - return 66; /* bany */
20976 - return 61; /* bne */
20978 - return 62; /* bge */
20980 - return 64; /* bgeu */
20982 - return 69; /* bnall */
20984 - return 71; /* bbs */
20987 - return 57; /* bbsi */
20992 +static xtensa_iclass_internal iclasses[] = {
20993 + { 0, 0 /* xt_iclass_excw */,
20995 + { 0, 0 /* xt_iclass_rfe */,
20996 + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
20997 + { 0, 0 /* xt_iclass_rfde */,
20998 + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
20999 + { 0, 0 /* xt_iclass_syscall */,
21001 + { 0, 0 /* xt_iclass_simcall */,
21003 + { 2, Iclass_xt_iclass_call12_args,
21004 + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
21005 + { 2, Iclass_xt_iclass_call8_args,
21006 + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
21007 + { 2, Iclass_xt_iclass_call4_args,
21008 + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
21009 + { 2, Iclass_xt_iclass_callx12_args,
21010 + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
21011 + { 2, Iclass_xt_iclass_callx8_args,
21012 + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
21013 + { 2, Iclass_xt_iclass_callx4_args,
21014 + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
21015 + { 3, Iclass_xt_iclass_entry_args,
21016 + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
21017 + { 2, Iclass_xt_iclass_movsp_args,
21018 + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
21019 + { 1, Iclass_xt_iclass_rotw_args,
21020 + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
21021 + { 1, Iclass_xt_iclass_retw_args,
21022 + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
21023 + { 0, 0 /* xt_iclass_rfwou */,
21024 + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
21025 + { 3, Iclass_xt_iclass_l32e_args,
21027 + { 3, Iclass_xt_iclass_s32e_args,
21029 + { 1, Iclass_xt_iclass_rsr_windowbase_args,
21030 + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
21031 + { 1, Iclass_xt_iclass_wsr_windowbase_args,
21032 + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
21033 + { 1, Iclass_xt_iclass_xsr_windowbase_args,
21034 + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
21035 + { 1, Iclass_xt_iclass_rsr_windowstart_args,
21036 + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
21037 + { 1, Iclass_xt_iclass_wsr_windowstart_args,
21038 + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
21039 + { 1, Iclass_xt_iclass_xsr_windowstart_args,
21040 + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
21041 + { 3, Iclass_xt_iclass_add_n_args,
21043 + { 3, Iclass_xt_iclass_addi_n_args,
21045 + { 2, Iclass_xt_iclass_bz6_args,
21047 + { 0, 0 /* xt_iclass_ill_n */,
21049 + { 3, Iclass_xt_iclass_loadi4_args,
21051 + { 2, Iclass_xt_iclass_mov_n_args,
21053 + { 2, Iclass_xt_iclass_movi_n_args,
21055 + { 0, 0 /* xt_iclass_nopn */,
21057 + { 1, Iclass_xt_iclass_retn_args,
21059 + { 3, Iclass_xt_iclass_storei4_args,
21061 + { 1, Iclass_rur_threadptr_args,
21062 + 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
21063 + { 1, Iclass_wur_threadptr_args,
21064 + 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
21065 + { 3, Iclass_xt_iclass_addi_args,
21067 + { 3, Iclass_xt_iclass_addmi_args,
21069 + { 3, Iclass_xt_iclass_addsub_args,
21071 + { 3, Iclass_xt_iclass_bit_args,
21073 + { 3, Iclass_xt_iclass_bsi8_args,
21075 + { 3, Iclass_xt_iclass_bsi8b_args,
21077 + { 3, Iclass_xt_iclass_bsi8u_args,
21079 + { 3, Iclass_xt_iclass_bst8_args,
21081 + { 2, Iclass_xt_iclass_bsz12_args,
21083 + { 2, Iclass_xt_iclass_call0_args,
21085 + { 2, Iclass_xt_iclass_callx0_args,
21087 + { 4, Iclass_xt_iclass_exti_args,
21089 + { 0, 0 /* xt_iclass_ill */,
21091 + { 1, Iclass_xt_iclass_jump_args,
21093 + { 1, Iclass_xt_iclass_jumpx_args,
21095 + { 3, Iclass_xt_iclass_l16ui_args,
21097 + { 3, Iclass_xt_iclass_l16si_args,
21099 + { 3, Iclass_xt_iclass_l32i_args,
21101 + { 2, Iclass_xt_iclass_l32r_args,
21102 + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
21103 + { 3, Iclass_xt_iclass_l8i_args,
21105 + { 2, Iclass_xt_iclass_loop_args,
21106 + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
21107 + { 2, Iclass_xt_iclass_loopz_args,
21108 + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
21109 + { 2, Iclass_xt_iclass_movi_args,
21111 + { 3, Iclass_xt_iclass_movz_args,
21113 + { 2, Iclass_xt_iclass_neg_args,
21115 + { 0, 0 /* xt_iclass_nop */,
21117 + { 1, Iclass_xt_iclass_return_args,
21119 + { 3, Iclass_xt_iclass_s16i_args,
21121 + { 3, Iclass_xt_iclass_s32i_args,
21123 + { 3, Iclass_xt_iclass_s8i_args,
21125 + { 1, Iclass_xt_iclass_sar_args,
21126 + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
21127 + { 1, Iclass_xt_iclass_sari_args,
21128 + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
21129 + { 2, Iclass_xt_iclass_shifts_args,
21130 + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
21131 + { 3, Iclass_xt_iclass_shiftst_args,
21132 + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
21133 + { 2, Iclass_xt_iclass_shiftt_args,
21134 + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
21135 + { 3, Iclass_xt_iclass_slli_args,
21137 + { 3, Iclass_xt_iclass_srai_args,
21139 + { 3, Iclass_xt_iclass_srli_args,
21141 + { 0, 0 /* xt_iclass_memw */,
21143 + { 0, 0 /* xt_iclass_extw */,
21145 + { 0, 0 /* xt_iclass_isync */,
21147 + { 0, 0 /* xt_iclass_sync */,
21148 + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
21149 + { 2, Iclass_xt_iclass_rsil_args,
21150 + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
21151 + { 1, Iclass_xt_iclass_rsr_lend_args,
21152 + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
21153 + { 1, Iclass_xt_iclass_wsr_lend_args,
21154 + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
21155 + { 1, Iclass_xt_iclass_xsr_lend_args,
21156 + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
21157 + { 1, Iclass_xt_iclass_rsr_lcount_args,
21158 + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
21159 + { 1, Iclass_xt_iclass_wsr_lcount_args,
21160 + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
21161 + { 1, Iclass_xt_iclass_xsr_lcount_args,
21162 + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
21163 + { 1, Iclass_xt_iclass_rsr_lbeg_args,
21164 + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
21165 + { 1, Iclass_xt_iclass_wsr_lbeg_args,
21166 + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
21167 + { 1, Iclass_xt_iclass_xsr_lbeg_args,
21168 + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
21169 + { 1, Iclass_xt_iclass_rsr_sar_args,
21170 + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
21171 + { 1, Iclass_xt_iclass_wsr_sar_args,
21172 + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
21173 + { 1, Iclass_xt_iclass_xsr_sar_args,
21174 + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
21175 + { 1, Iclass_xt_iclass_rsr_litbase_args,
21176 + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
21177 + { 1, Iclass_xt_iclass_wsr_litbase_args,
21178 + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
21179 + { 1, Iclass_xt_iclass_xsr_litbase_args,
21180 + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
21181 + { 1, Iclass_xt_iclass_rsr_176_args,
21183 + { 1, Iclass_xt_iclass_rsr_208_args,
21185 + { 1, Iclass_xt_iclass_rsr_ps_args,
21186 + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
21187 + { 1, Iclass_xt_iclass_wsr_ps_args,
21188 + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
21189 + { 1, Iclass_xt_iclass_xsr_ps_args,
21190 + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
21191 + { 1, Iclass_xt_iclass_rsr_epc1_args,
21192 + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
21193 + { 1, Iclass_xt_iclass_wsr_epc1_args,
21194 + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
21195 + { 1, Iclass_xt_iclass_xsr_epc1_args,
21196 + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
21197 + { 1, Iclass_xt_iclass_rsr_excsave1_args,
21198 + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
21199 + { 1, Iclass_xt_iclass_wsr_excsave1_args,
21200 + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
21201 + { 1, Iclass_xt_iclass_xsr_excsave1_args,
21202 + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
21203 + { 1, Iclass_xt_iclass_rsr_epc2_args,
21204 + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
21205 + { 1, Iclass_xt_iclass_wsr_epc2_args,
21206 + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
21207 + { 1, Iclass_xt_iclass_xsr_epc2_args,
21208 + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
21209 + { 1, Iclass_xt_iclass_rsr_excsave2_args,
21210 + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
21211 + { 1, Iclass_xt_iclass_wsr_excsave2_args,
21212 + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
21213 + { 1, Iclass_xt_iclass_xsr_excsave2_args,
21214 + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
21215 + { 1, Iclass_xt_iclass_rsr_epc3_args,
21216 + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
21217 + { 1, Iclass_xt_iclass_wsr_epc3_args,
21218 + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
21219 + { 1, Iclass_xt_iclass_xsr_epc3_args,
21220 + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
21221 + { 1, Iclass_xt_iclass_rsr_excsave3_args,
21222 + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
21223 + { 1, Iclass_xt_iclass_wsr_excsave3_args,
21224 + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
21225 + { 1, Iclass_xt_iclass_xsr_excsave3_args,
21226 + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
21227 + { 1, Iclass_xt_iclass_rsr_epc4_args,
21228 + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
21229 + { 1, Iclass_xt_iclass_wsr_epc4_args,
21230 + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
21231 + { 1, Iclass_xt_iclass_xsr_epc4_args,
21232 + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
21233 + { 1, Iclass_xt_iclass_rsr_excsave4_args,
21234 + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
21235 + { 1, Iclass_xt_iclass_wsr_excsave4_args,
21236 + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
21237 + { 1, Iclass_xt_iclass_xsr_excsave4_args,
21238 + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
21239 + { 1, Iclass_xt_iclass_rsr_epc5_args,
21240 + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
21241 + { 1, Iclass_xt_iclass_wsr_epc5_args,
21242 + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
21243 + { 1, Iclass_xt_iclass_xsr_epc5_args,
21244 + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
21245 + { 1, Iclass_xt_iclass_rsr_excsave5_args,
21246 + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
21247 + { 1, Iclass_xt_iclass_wsr_excsave5_args,
21248 + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
21249 + { 1, Iclass_xt_iclass_xsr_excsave5_args,
21250 + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
21251 + { 1, Iclass_xt_iclass_rsr_eps2_args,
21252 + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
21253 + { 1, Iclass_xt_iclass_wsr_eps2_args,
21254 + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
21255 + { 1, Iclass_xt_iclass_xsr_eps2_args,
21256 + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
21257 + { 1, Iclass_xt_iclass_rsr_eps3_args,
21258 + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
21259 + { 1, Iclass_xt_iclass_wsr_eps3_args,
21260 + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
21261 + { 1, Iclass_xt_iclass_xsr_eps3_args,
21262 + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
21263 + { 1, Iclass_xt_iclass_rsr_eps4_args,
21264 + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
21265 + { 1, Iclass_xt_iclass_wsr_eps4_args,
21266 + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
21267 + { 1, Iclass_xt_iclass_xsr_eps4_args,
21268 + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
21269 + { 1, Iclass_xt_iclass_rsr_eps5_args,
21270 + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
21271 + { 1, Iclass_xt_iclass_wsr_eps5_args,
21272 + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
21273 + { 1, Iclass_xt_iclass_xsr_eps5_args,
21274 + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
21275 + { 1, Iclass_xt_iclass_rsr_excvaddr_args,
21276 + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
21277 + { 1, Iclass_xt_iclass_wsr_excvaddr_args,
21278 + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
21279 + { 1, Iclass_xt_iclass_xsr_excvaddr_args,
21280 + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
21281 + { 1, Iclass_xt_iclass_rsr_depc_args,
21282 + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
21283 + { 1, Iclass_xt_iclass_wsr_depc_args,
21284 + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
21285 + { 1, Iclass_xt_iclass_xsr_depc_args,
21286 + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
21287 + { 1, Iclass_xt_iclass_rsr_exccause_args,
21288 + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
21289 + { 1, Iclass_xt_iclass_wsr_exccause_args,
21290 + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
21291 + { 1, Iclass_xt_iclass_xsr_exccause_args,
21292 + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
21293 + { 1, Iclass_xt_iclass_rsr_misc0_args,
21294 + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
21295 + { 1, Iclass_xt_iclass_wsr_misc0_args,
21296 + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
21297 + { 1, Iclass_xt_iclass_xsr_misc0_args,
21298 + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
21299 + { 1, Iclass_xt_iclass_rsr_misc1_args,
21300 + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
21301 + { 1, Iclass_xt_iclass_wsr_misc1_args,
21302 + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
21303 + { 1, Iclass_xt_iclass_xsr_misc1_args,
21304 + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
21305 + { 1, Iclass_xt_iclass_rsr_prid_args,
21307 + { 1, Iclass_xt_iclass_rsr_vecbase_args,
21308 + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
21309 + { 1, Iclass_xt_iclass_wsr_vecbase_args,
21310 + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
21311 + { 1, Iclass_xt_iclass_xsr_vecbase_args,
21312 + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
21313 + { 1, Iclass_xt_iclass_rfi_args,
21314 + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
21315 + { 1, Iclass_xt_iclass_wait_args,
21316 + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
21317 + { 1, Iclass_xt_iclass_rsr_interrupt_args,
21318 + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
21319 + { 1, Iclass_xt_iclass_wsr_intset_args,
21320 + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
21321 + { 1, Iclass_xt_iclass_wsr_intclear_args,
21322 + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
21323 + { 1, Iclass_xt_iclass_rsr_intenable_args,
21324 + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
21325 + { 1, Iclass_xt_iclass_wsr_intenable_args,
21326 + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
21327 + { 1, Iclass_xt_iclass_xsr_intenable_args,
21328 + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
21329 + { 2, Iclass_xt_iclass_break_args,
21330 + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
21331 + { 1, Iclass_xt_iclass_break_n_args,
21332 + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
21333 + { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
21334 + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
21335 + { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
21336 + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
21337 + { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
21338 + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
21339 + { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
21340 + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
21341 + { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
21342 + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
21343 + { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
21344 + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
21345 + { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
21346 + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
21347 + { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
21348 + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
21349 + { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
21350 + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
21351 + { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
21352 + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
21353 + { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
21354 + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
21355 + { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
21356 + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
21357 + { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
21358 + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
21359 + { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
21360 + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
21361 + { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
21362 + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
21363 + { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
21364 + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
21365 + { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
21366 + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
21367 + { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
21368 + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
21369 + { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
21370 + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
21371 + { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
21372 + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
21373 + { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
21374 + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
21375 + { 1, Iclass_xt_iclass_rsr_debugcause_args,
21376 + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
21377 + { 1, Iclass_xt_iclass_wsr_debugcause_args,
21378 + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
21379 + { 1, Iclass_xt_iclass_xsr_debugcause_args,
21380 + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
21381 + { 1, Iclass_xt_iclass_rsr_icount_args,
21382 + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
21383 + { 1, Iclass_xt_iclass_wsr_icount_args,
21384 + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
21385 + { 1, Iclass_xt_iclass_xsr_icount_args,
21386 + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
21387 + { 1, Iclass_xt_iclass_rsr_icountlevel_args,
21388 + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
21389 + { 1, Iclass_xt_iclass_wsr_icountlevel_args,
21390 + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
21391 + { 1, Iclass_xt_iclass_xsr_icountlevel_args,
21392 + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
21393 + { 1, Iclass_xt_iclass_rsr_ddr_args,
21394 + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
21395 + { 1, Iclass_xt_iclass_wsr_ddr_args,
21396 + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
21397 + { 1, Iclass_xt_iclass_xsr_ddr_args,
21398 + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
21399 + { 1, Iclass_xt_iclass_rfdo_args,
21400 + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
21401 + { 0, 0 /* xt_iclass_rfdd */,
21402 + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
21403 + { 1, Iclass_xt_iclass_wsr_mmid_args,
21404 + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
21405 + { 1, Iclass_xt_iclass_rsr_ccount_args,
21406 + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
21407 + { 1, Iclass_xt_iclass_wsr_ccount_args,
21408 + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
21409 + { 1, Iclass_xt_iclass_xsr_ccount_args,
21410 + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
21411 + { 1, Iclass_xt_iclass_rsr_ccompare0_args,
21412 + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
21413 + { 1, Iclass_xt_iclass_wsr_ccompare0_args,
21414 + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
21415 + { 1, Iclass_xt_iclass_xsr_ccompare0_args,
21416 + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
21417 + { 1, Iclass_xt_iclass_idtlb_args,
21418 + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
21419 + { 2, Iclass_xt_iclass_rdtlb_args,
21421 + { 2, Iclass_xt_iclass_wdtlb_args,
21422 + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
21423 + { 1, Iclass_xt_iclass_iitlb_args,
21425 + { 2, Iclass_xt_iclass_ritlb_args,
21427 + { 2, Iclass_xt_iclass_witlb_args,
21429 + { 3, Iclass_xt_iclass_minmax_args,
21431 + { 2, Iclass_xt_iclass_nsa_args,
21433 + { 3, Iclass_xt_iclass_sx_args,
21435 + { 3, Iclass_xt_iclass_l32ai_args,
21437 + { 3, Iclass_xt_iclass_s32ri_args,
21439 + { 3, Iclass_xt_iclass_s32c1i_args,
21440 + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
21441 + { 1, Iclass_xt_iclass_rsr_scompare1_args,
21442 + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
21443 + { 1, Iclass_xt_iclass_wsr_scompare1_args,
21444 + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
21445 + { 1, Iclass_xt_iclass_xsr_scompare1_args,
21446 + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
21447 + { 3, Iclass_xt_mul32_args,
21452 +/* Opcode encodings. */
21455 +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21457 + slotbuf[0] = 0x80200;
21461 +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
21463 + slotbuf[0] = 0x300;
21467 +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
21469 + slotbuf[0] = 0x2300;
21473 +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21475 + slotbuf[0] = 0x500;
21479 +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21481 + slotbuf[0] = 0x1500;
21485 +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21487 + slotbuf[0] = 0x5c0000;
21491 +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21493 + slotbuf[0] = 0x580000;
21497 +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21499 + slotbuf[0] = 0x540000;
21503 +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21505 + slotbuf[0] = 0xf0000;
21509 +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21511 + slotbuf[0] = 0xb0000;
21515 +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21517 + slotbuf[0] = 0x70000;
21521 +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
21523 + slotbuf[0] = 0x6c0000;
21527 +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21529 + slotbuf[0] = 0x100;
21533 +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21535 + slotbuf[0] = 0x804;
21539 +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21541 + slotbuf[0] = 0x60000;
21545 +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21547 + slotbuf[0] = 0xd10f;
21551 +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
21553 + slotbuf[0] = 0x4300;
21557 +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21559 + slotbuf[0] = 0x5300;
21563 +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21565 + slotbuf[0] = 0x90;
21569 +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21571 + slotbuf[0] = 0x94;
21575 +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21577 + slotbuf[0] = 0x4830;
21581 +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21583 + slotbuf[0] = 0x4831;
21587 +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21589 + slotbuf[0] = 0x4816;
21593 +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21595 + slotbuf[0] = 0x4930;
21599 +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21601 + slotbuf[0] = 0x4931;
21605 +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21607 + slotbuf[0] = 0x4916;
21611 +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21613 + slotbuf[0] = 0xa000;
21617 +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21619 + slotbuf[0] = 0xb000;
21623 +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21625 + slotbuf[0] = 0xc800;
21629 +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21631 + slotbuf[0] = 0xcc00;
21635 +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21637 + slotbuf[0] = 0xd60f;
21641 +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21643 + slotbuf[0] = 0x8000;
21647 +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21649 + slotbuf[0] = 0xd000;
21653 +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21655 + slotbuf[0] = 0xc000;
21659 +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21661 + slotbuf[0] = 0xd30f;
21665 +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21667 + slotbuf[0] = 0xd00f;
21671 +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21673 + slotbuf[0] = 0x9000;
21677 +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21679 + slotbuf[0] = 0x7e03e;
21683 +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21685 + slotbuf[0] = 0xe73f;
21689 +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21691 + slotbuf[0] = 0x200c00;
21695 +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21697 + slotbuf[0] = 0x200d00;
21701 +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
21703 + slotbuf[0] = 0x8;
21707 +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
21709 + slotbuf[0] = 0xc;
21713 +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21715 + slotbuf[0] = 0x9;
21719 +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21721 + slotbuf[0] = 0xa;
21725 +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21727 + slotbuf[0] = 0xb;
21731 +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21733 + slotbuf[0] = 0xd;
21737 +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21739 + slotbuf[0] = 0xe;
21743 +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21745 + slotbuf[0] = 0xf;
21749 +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
21751 + slotbuf[0] = 0x1;
21755 +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
21757 + slotbuf[0] = 0x2;
21761 +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
21763 + slotbuf[0] = 0x3;
21767 +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21769 + slotbuf[0] = 0x680000;
21773 +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21775 + slotbuf[0] = 0x690000;
21779 +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21781 + slotbuf[0] = 0x6b0000;
21785 +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
21787 + slotbuf[0] = 0x6a0000;
21791 +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
21793 + slotbuf[0] = 0x700600;
21797 +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21799 + slotbuf[0] = 0x700e00;
21803 +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21805 + slotbuf[0] = 0x6f0000;
21809 +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21811 + slotbuf[0] = 0x6e0000;
21815 +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
21817 + slotbuf[0] = 0x700100;
21821 +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
21823 + slotbuf[0] = 0x700900;
21827 +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
21829 + slotbuf[0] = 0x700a00;
21833 +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
21835 + slotbuf[0] = 0x700200;
21839 +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21841 + slotbuf[0] = 0x700b00;
21845 +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21847 + slotbuf[0] = 0x700300;
21851 +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
21853 + slotbuf[0] = 0x700800;
21857 +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21859 + slotbuf[0] = 0x700000;
21863 +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
21865 + slotbuf[0] = 0x700400;
21869 +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21871 + slotbuf[0] = 0x700c00;
21875 +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
21877 + slotbuf[0] = 0x700500;
21881 +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
21883 + slotbuf[0] = 0x700d00;
21887 +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21889 + slotbuf[0] = 0x640000;
21893 +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21895 + slotbuf[0] = 0x650000;
21899 +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21901 + slotbuf[0] = 0x670000;
21905 +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21907 + slotbuf[0] = 0x660000;
21911 +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21913 + slotbuf[0] = 0x500000;
21917 +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21919 + slotbuf[0] = 0x30000;
21923 +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21925 + slotbuf[0] = 0x40;
21929 +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
21935 +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
21937 + slotbuf[0] = 0x600000;
21941 +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
21943 + slotbuf[0] = 0xa0000;
21947 +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21949 + slotbuf[0] = 0x200100;
21953 +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
21955 + slotbuf[0] = 0x200900;
21959 +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21961 + slotbuf[0] = 0x200200;
21965 +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
21967 + slotbuf[0] = 0x100000;
21971 +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21973 + slotbuf[0] = 0x200000;
21977 +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
21979 + slotbuf[0] = 0x6d0800;
21983 +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21985 + slotbuf[0] = 0x6d0900;
21989 +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21991 + slotbuf[0] = 0x6d0a00;
21995 +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21997 + slotbuf[0] = 0x200a00;
22001 +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22003 + slotbuf[0] = 0x38;
22007 +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22009 + slotbuf[0] = 0x39;
22013 +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22015 + slotbuf[0] = 0x3a;
22019 +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22021 + slotbuf[0] = 0x3b;
22025 +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22027 + slotbuf[0] = 0x6;
22031 +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
22033 + slotbuf[0] = 0x1006;
22037 +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
22039 + slotbuf[0] = 0xf0200;
22043 +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
22045 + slotbuf[0] = 0x20000;
22049 +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22051 + slotbuf[0] = 0x200500;
22055 +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22057 + slotbuf[0] = 0x200600;
22061 +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22063 + slotbuf[0] = 0x200400;
22067 +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22069 + slotbuf[0] = 0x4;
22073 +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22075 + slotbuf[0] = 0x104;
22079 +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22081 + slotbuf[0] = 0x204;
22085 +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
22087 + slotbuf[0] = 0x304;
22091 +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22093 + slotbuf[0] = 0x404;
22097 +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
22099 + slotbuf[0] = 0x1a;
22103 +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
22105 + slotbuf[0] = 0x18;
22109 +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22111 + slotbuf[0] = 0x19;
22115 +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
22117 + slotbuf[0] = 0x1b;
22121 +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22123 + slotbuf[0] = 0x10;
22127 +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22129 + slotbuf[0] = 0x12;
22133 +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22135 + slotbuf[0] = 0x14;
22139 +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22141 + slotbuf[0] = 0xc0200;
22145 +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22147 + slotbuf[0] = 0xd0200;
22151 +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22153 + slotbuf[0] = 0x200;
22157 +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22159 + slotbuf[0] = 0x10200;
22163 +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22165 + slotbuf[0] = 0x20200;
22169 +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22171 + slotbuf[0] = 0x30200;
22175 +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
22177 + slotbuf[0] = 0x600;
22181 +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22183 + slotbuf[0] = 0x130;
22187 +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22189 + slotbuf[0] = 0x131;
22193 +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22195 + slotbuf[0] = 0x116;
22199 +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22201 + slotbuf[0] = 0x230;
22205 +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22207 + slotbuf[0] = 0x231;
22211 +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22213 + slotbuf[0] = 0x216;
22217 +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22219 + slotbuf[0] = 0x30;
22223 +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22225 + slotbuf[0] = 0x31;
22229 +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22231 + slotbuf[0] = 0x16;
22235 +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22237 + slotbuf[0] = 0x330;
22241 +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22243 + slotbuf[0] = 0x331;
22247 +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22249 + slotbuf[0] = 0x316;
22253 +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22255 + slotbuf[0] = 0x530;
22259 +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22261 + slotbuf[0] = 0x531;
22265 +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22267 + slotbuf[0] = 0x516;
22271 +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
22273 + slotbuf[0] = 0xb030;
22277 +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
22279 + slotbuf[0] = 0xd030;
22283 +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22285 + slotbuf[0] = 0xe630;
22289 +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22291 + slotbuf[0] = 0xe631;
22295 +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22297 + slotbuf[0] = 0xe616;
22301 +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22303 + slotbuf[0] = 0xb130;
22307 +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22309 + slotbuf[0] = 0xb131;
22313 +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22315 + slotbuf[0] = 0xb116;
22319 +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22321 + slotbuf[0] = 0xd130;
22325 +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22327 + slotbuf[0] = 0xd131;
22331 +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22333 + slotbuf[0] = 0xd116;
22337 +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22339 + slotbuf[0] = 0xb230;
22343 +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22345 + slotbuf[0] = 0xb231;
22349 +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22351 + slotbuf[0] = 0xb216;
22355 +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22357 + slotbuf[0] = 0xd230;
22361 +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22363 + slotbuf[0] = 0xd231;
22367 +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22369 + slotbuf[0] = 0xd216;
22373 +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22375 + slotbuf[0] = 0xb330;
22379 +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22381 + slotbuf[0] = 0xb331;
22385 +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22387 + slotbuf[0] = 0xb316;
22391 +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22393 + slotbuf[0] = 0xd330;
22397 +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22399 + slotbuf[0] = 0xd331;
22403 +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22405 + slotbuf[0] = 0xd316;
22409 +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22411 + slotbuf[0] = 0xb430;
22415 +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22417 + slotbuf[0] = 0xb431;
22421 +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22423 + slotbuf[0] = 0xb416;
22427 +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22429 + slotbuf[0] = 0xd430;
22433 +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22435 + slotbuf[0] = 0xd431;
22439 +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22441 + slotbuf[0] = 0xd416;
22445 +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22447 + slotbuf[0] = 0xb530;
22451 +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22453 + slotbuf[0] = 0xb531;
22457 +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22459 + slotbuf[0] = 0xb516;
22463 +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22465 + slotbuf[0] = 0xd530;
22469 +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22471 + slotbuf[0] = 0xd531;
22475 +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22477 + slotbuf[0] = 0xd516;
22481 +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22483 + slotbuf[0] = 0xc230;
22487 +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22489 + slotbuf[0] = 0xc231;
22493 +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22495 + slotbuf[0] = 0xc216;
22499 +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22501 + slotbuf[0] = 0xc330;
22505 +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22507 + slotbuf[0] = 0xc331;
22511 +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22513 + slotbuf[0] = 0xc316;
22517 +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22519 + slotbuf[0] = 0xc430;
22523 +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22525 + slotbuf[0] = 0xc431;
22529 +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22531 + slotbuf[0] = 0xc416;
22535 +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22537 + slotbuf[0] = 0xc530;
22541 +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22543 + slotbuf[0] = 0xc531;
22547 +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22549 + slotbuf[0] = 0xc516;
22553 +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22555 + slotbuf[0] = 0xee30;
22559 +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22561 + slotbuf[0] = 0xee31;
22565 +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22567 + slotbuf[0] = 0xee16;
22571 +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22573 + slotbuf[0] = 0xc030;
22577 +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22579 + slotbuf[0] = 0xc031;
22583 +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22585 + slotbuf[0] = 0xc016;
22589 +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22591 + slotbuf[0] = 0xe830;
22595 +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22597 + slotbuf[0] = 0xe831;
22601 +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22603 + slotbuf[0] = 0xe816;
22607 +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22609 + slotbuf[0] = 0xf430;
22613 +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22615 + slotbuf[0] = 0xf431;
22619 +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22621 + slotbuf[0] = 0xf416;
22625 +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22627 + slotbuf[0] = 0xf530;
22631 +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22633 + slotbuf[0] = 0xf531;
22637 +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22639 + slotbuf[0] = 0xf516;
22643 +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22645 + slotbuf[0] = 0xeb30;
22649 +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22651 + slotbuf[0] = 0xe730;
22655 +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22657 + slotbuf[0] = 0xe731;
22661 +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22663 + slotbuf[0] = 0xe716;
22667 +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
22669 + slotbuf[0] = 0x10300;
22673 +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
22675 + slotbuf[0] = 0x700;
22679 +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
22681 + slotbuf[0] = 0xe230;
22685 +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
22687 + slotbuf[0] = 0xe231;
22691 +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
22693 + slotbuf[0] = 0xe331;
22697 +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22699 + slotbuf[0] = 0xe430;
22703 +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22705 + slotbuf[0] = 0xe431;
22709 +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22711 + slotbuf[0] = 0xe416;
22715 +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
22717 + slotbuf[0] = 0x400;
22721 +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
22723 + slotbuf[0] = 0xd20f;
22727 +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22729 + slotbuf[0] = 0x9030;
22733 +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22735 + slotbuf[0] = 0x9031;
22739 +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22741 + slotbuf[0] = 0x9016;
22745 +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22747 + slotbuf[0] = 0xa030;
22751 +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22753 + slotbuf[0] = 0xa031;
22757 +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22759 + slotbuf[0] = 0xa016;
22763 +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22765 + slotbuf[0] = 0x9130;
22769 +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22771 + slotbuf[0] = 0x9131;
22775 +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22777 + slotbuf[0] = 0x9116;
22781 +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22783 + slotbuf[0] = 0xa130;
22787 +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22789 + slotbuf[0] = 0xa131;
22793 +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22795 + slotbuf[0] = 0xa116;
22799 +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22801 + slotbuf[0] = 0x8030;
22805 +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22807 + slotbuf[0] = 0x8031;
22811 +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22813 + slotbuf[0] = 0x8016;
22817 +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22819 + slotbuf[0] = 0x8130;
22823 +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22825 + slotbuf[0] = 0x8131;
22829 +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22831 + slotbuf[0] = 0x8116;
22835 +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22837 + slotbuf[0] = 0x6030;
22841 +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22843 + slotbuf[0] = 0x6031;
22847 +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22849 + slotbuf[0] = 0x6016;
22853 +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22855 + slotbuf[0] = 0xe930;
22859 +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22861 + slotbuf[0] = 0xe931;
22865 +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22867 + slotbuf[0] = 0xe916;
22871 +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22873 + slotbuf[0] = 0xec30;
22877 +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22879 + slotbuf[0] = 0xec31;
22883 +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22885 + slotbuf[0] = 0xec16;
22889 +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22891 + slotbuf[0] = 0xed30;
22895 +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22897 + slotbuf[0] = 0xed31;
22901 +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22903 + slotbuf[0] = 0xed16;
22907 +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22909 + slotbuf[0] = 0x6830;
22913 +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22915 + slotbuf[0] = 0x6831;
22919 +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22921 + slotbuf[0] = 0x6816;
22925 +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
22927 + slotbuf[0] = 0xe1f;
22931 +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
22933 + slotbuf[0] = 0x10e1f;
22937 +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22939 + slotbuf[0] = 0x5931;
22943 +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22945 + slotbuf[0] = 0xea30;
22949 +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22951 + slotbuf[0] = 0xea31;
22955 +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22957 + slotbuf[0] = 0xea16;
22961 +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22963 + slotbuf[0] = 0xf030;
22967 +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22969 + slotbuf[0] = 0xf031;
22973 +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22975 + slotbuf[0] = 0xf016;
22979 +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22981 + slotbuf[0] = 0xc05;
22985 +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22987 + slotbuf[0] = 0xd05;
22991 +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22993 + slotbuf[0] = 0xb05;
22997 +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22999 + slotbuf[0] = 0xf05;
23003 +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23005 + slotbuf[0] = 0xe05;
23009 +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23011 + slotbuf[0] = 0x405;
23015 +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23017 + slotbuf[0] = 0x505;
23021 +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
23023 + slotbuf[0] = 0x305;
23027 +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23029 + slotbuf[0] = 0x705;
23033 +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23035 + slotbuf[0] = 0x605;
23039 +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
23041 + slotbuf[0] = 0x34;
23045 +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
23047 + slotbuf[0] = 0x35;
23051 +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23053 + slotbuf[0] = 0x36;
23057 +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23059 + slotbuf[0] = 0x37;
23063 +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
23065 + slotbuf[0] = 0xe04;
23069 +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
23071 + slotbuf[0] = 0xf04;
23075 +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
23077 + slotbuf[0] = 0x32;
23081 +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
23083 + slotbuf[0] = 0x200b00;
23087 +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
23089 + slotbuf[0] = 0x200f00;
23093 +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
23095 + slotbuf[0] = 0x200e00;
23099 +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23101 + slotbuf[0] = 0xc30;
23105 +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23107 + slotbuf[0] = 0xc31;
23111 +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23113 + slotbuf[0] = 0xc16;
23117 +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
23119 + slotbuf[0] = 0x28;
23123 +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23125 + slotbuf[0] = 0x2a;
23129 +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23131 + slotbuf[0] = 0x2b;
23135 +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
23137 + slotbuf[0] = 0x1c;
23141 +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
23143 + slotbuf[0] = 0x1d;
23147 -Slot_inst16b_decode (const xtensa_insnbuf insn)
23149 - switch (Field_op0_Slot_inst16b_get (insn))
23152 - switch (Field_i_Slot_inst16b_get (insn))
23155 - return 33; /* movi.n */
23157 - switch (Field_z_Slot_inst16b_get (insn))
23160 - return 28; /* beqz.n */
23162 - return 29; /* bnez.n */
23168 - switch (Field_r_Slot_inst16b_get (insn))
23171 - return 32; /* mov.n */
23173 - switch (Field_t_Slot_inst16b_get (insn))
23176 - return 35; /* ret.n */
23178 - return 15; /* retw.n */
23180 - return 325; /* break.n */
23182 - if (Field_s_Slot_inst16b_get (insn) == 0)
23183 - return 34; /* nop.n */
23186 - if (Field_s_Slot_inst16b_get (insn) == 0)
23187 - return 30; /* ill.n */
23196 +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
23197 + Opcode_excw_Slot_inst_encode, 0, 0
23200 +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
23201 + Opcode_rfe_Slot_inst_encode, 0, 0
23204 +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
23205 + Opcode_rfde_Slot_inst_encode, 0, 0
23208 +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
23209 + Opcode_syscall_Slot_inst_encode, 0, 0
23212 +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
23213 + Opcode_simcall_Slot_inst_encode, 0, 0
23216 +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
23217 + Opcode_call12_Slot_inst_encode, 0, 0
23220 +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
23221 + Opcode_call8_Slot_inst_encode, 0, 0
23224 +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
23225 + Opcode_call4_Slot_inst_encode, 0, 0
23228 +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
23229 + Opcode_callx12_Slot_inst_encode, 0, 0
23232 +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
23233 + Opcode_callx8_Slot_inst_encode, 0, 0
23236 +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
23237 + Opcode_callx4_Slot_inst_encode, 0, 0
23240 +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
23241 + Opcode_entry_Slot_inst_encode, 0, 0
23244 +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
23245 + Opcode_movsp_Slot_inst_encode, 0, 0
23248 +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
23249 + Opcode_rotw_Slot_inst_encode, 0, 0
23252 +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
23253 + Opcode_retw_Slot_inst_encode, 0, 0
23256 +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
23257 + 0, 0, Opcode_retw_n_Slot_inst16b_encode
23260 +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
23261 + Opcode_rfwo_Slot_inst_encode, 0, 0
23264 +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
23265 + Opcode_rfwu_Slot_inst_encode, 0, 0
23268 +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
23269 + Opcode_l32e_Slot_inst_encode, 0, 0
23272 +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
23273 + Opcode_s32e_Slot_inst_encode, 0, 0
23276 +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
23277 + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
23280 +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
23281 + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
23284 +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
23285 + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
23288 +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
23289 + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
23292 +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
23293 + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
23296 +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
23297 + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
23300 +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
23301 + 0, Opcode_add_n_Slot_inst16a_encode, 0
23304 +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
23305 + 0, Opcode_addi_n_Slot_inst16a_encode, 0
23308 +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
23309 + 0, 0, Opcode_beqz_n_Slot_inst16b_encode
23312 +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
23313 + 0, 0, Opcode_bnez_n_Slot_inst16b_encode
23316 +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
23317 + 0, 0, Opcode_ill_n_Slot_inst16b_encode
23320 +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
23321 + 0, Opcode_l32i_n_Slot_inst16a_encode, 0
23324 +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
23325 + 0, 0, Opcode_mov_n_Slot_inst16b_encode
23328 +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
23329 + 0, 0, Opcode_movi_n_Slot_inst16b_encode
23332 +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
23333 + 0, 0, Opcode_nop_n_Slot_inst16b_encode
23336 +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
23337 + 0, 0, Opcode_ret_n_Slot_inst16b_encode
23340 +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
23341 + 0, Opcode_s32i_n_Slot_inst16a_encode, 0
23344 +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
23345 + Opcode_rur_threadptr_Slot_inst_encode, 0, 0
23348 +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
23349 + Opcode_wur_threadptr_Slot_inst_encode, 0, 0
23352 +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
23353 + Opcode_addi_Slot_inst_encode, 0, 0
23356 +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
23357 + Opcode_addmi_Slot_inst_encode, 0, 0
23360 +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
23361 + Opcode_add_Slot_inst_encode, 0, 0
23364 +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
23365 + Opcode_sub_Slot_inst_encode, 0, 0
23368 +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
23369 + Opcode_addx2_Slot_inst_encode, 0, 0
23372 +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
23373 + Opcode_addx4_Slot_inst_encode, 0, 0
23376 +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
23377 + Opcode_addx8_Slot_inst_encode, 0, 0
23380 +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
23381 + Opcode_subx2_Slot_inst_encode, 0, 0
23384 +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
23385 + Opcode_subx4_Slot_inst_encode, 0, 0
23388 +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
23389 + Opcode_subx8_Slot_inst_encode, 0, 0
23392 +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
23393 + Opcode_and_Slot_inst_encode, 0, 0
23396 +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
23397 + Opcode_or_Slot_inst_encode, 0, 0
23400 +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
23401 + Opcode_xor_Slot_inst_encode, 0, 0
23404 +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
23405 + Opcode_beqi_Slot_inst_encode, 0, 0
23408 +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
23409 + Opcode_bnei_Slot_inst_encode, 0, 0
23412 +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
23413 + Opcode_bgei_Slot_inst_encode, 0, 0
23416 +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
23417 + Opcode_blti_Slot_inst_encode, 0, 0
23420 +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
23421 + Opcode_bbci_Slot_inst_encode, 0, 0
23424 +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
23425 + Opcode_bbsi_Slot_inst_encode, 0, 0
23428 +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
23429 + Opcode_bgeui_Slot_inst_encode, 0, 0
23432 +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
23433 + Opcode_bltui_Slot_inst_encode, 0, 0
23436 +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
23437 + Opcode_beq_Slot_inst_encode, 0, 0
23440 +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
23441 + Opcode_bne_Slot_inst_encode, 0, 0
23444 +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
23445 + Opcode_bge_Slot_inst_encode, 0, 0
23448 +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
23449 + Opcode_blt_Slot_inst_encode, 0, 0
23452 +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
23453 + Opcode_bgeu_Slot_inst_encode, 0, 0
23456 +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
23457 + Opcode_bltu_Slot_inst_encode, 0, 0
23460 +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
23461 + Opcode_bany_Slot_inst_encode, 0, 0
23464 +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
23465 + Opcode_bnone_Slot_inst_encode, 0, 0
23468 +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
23469 + Opcode_ball_Slot_inst_encode, 0, 0
23472 +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
23473 + Opcode_bnall_Slot_inst_encode, 0, 0
23476 +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
23477 + Opcode_bbc_Slot_inst_encode, 0, 0
23480 +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
23481 + Opcode_bbs_Slot_inst_encode, 0, 0
23484 +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
23485 + Opcode_beqz_Slot_inst_encode, 0, 0
23488 +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
23489 + Opcode_bnez_Slot_inst_encode, 0, 0
23492 +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
23493 + Opcode_bgez_Slot_inst_encode, 0, 0
23496 +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
23497 + Opcode_bltz_Slot_inst_encode, 0, 0
23500 +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
23501 + Opcode_call0_Slot_inst_encode, 0, 0
23504 +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
23505 + Opcode_callx0_Slot_inst_encode, 0, 0
23508 +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
23509 + Opcode_extui_Slot_inst_encode, 0, 0
23512 +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
23513 + Opcode_ill_Slot_inst_encode, 0, 0
23516 +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
23517 + Opcode_j_Slot_inst_encode, 0, 0
23520 +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
23521 + Opcode_jx_Slot_inst_encode, 0, 0
23524 +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
23525 + Opcode_l16ui_Slot_inst_encode, 0, 0
23528 +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
23529 + Opcode_l16si_Slot_inst_encode, 0, 0
23532 +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
23533 + Opcode_l32i_Slot_inst_encode, 0, 0
23536 +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
23537 + Opcode_l32r_Slot_inst_encode, 0, 0
23540 +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
23541 + Opcode_l8ui_Slot_inst_encode, 0, 0
23544 +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
23545 + Opcode_loop_Slot_inst_encode, 0, 0
23548 +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
23549 + Opcode_loopnez_Slot_inst_encode, 0, 0
23552 +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
23553 + Opcode_loopgtz_Slot_inst_encode, 0, 0
23556 +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
23557 + Opcode_movi_Slot_inst_encode, 0, 0
23560 +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
23561 + Opcode_moveqz_Slot_inst_encode, 0, 0
23564 +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
23565 + Opcode_movnez_Slot_inst_encode, 0, 0
23568 +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
23569 + Opcode_movltz_Slot_inst_encode, 0, 0
23572 +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
23573 + Opcode_movgez_Slot_inst_encode, 0, 0
23576 +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
23577 + Opcode_neg_Slot_inst_encode, 0, 0
23580 +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
23581 + Opcode_abs_Slot_inst_encode, 0, 0
23584 +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
23585 + Opcode_nop_Slot_inst_encode, 0, 0
23588 +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
23589 + Opcode_ret_Slot_inst_encode, 0, 0
23592 +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
23593 + Opcode_s16i_Slot_inst_encode, 0, 0
23596 +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
23597 + Opcode_s32i_Slot_inst_encode, 0, 0
23600 +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
23601 + Opcode_s8i_Slot_inst_encode, 0, 0
23604 +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
23605 + Opcode_ssr_Slot_inst_encode, 0, 0
23608 +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
23609 + Opcode_ssl_Slot_inst_encode, 0, 0
23612 +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
23613 + Opcode_ssa8l_Slot_inst_encode, 0, 0
23616 +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
23617 + Opcode_ssa8b_Slot_inst_encode, 0, 0
23620 +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
23621 + Opcode_ssai_Slot_inst_encode, 0, 0
23624 +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
23625 + Opcode_sll_Slot_inst_encode, 0, 0
23628 +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
23629 + Opcode_src_Slot_inst_encode, 0, 0
23632 +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
23633 + Opcode_srl_Slot_inst_encode, 0, 0
23636 +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
23637 + Opcode_sra_Slot_inst_encode, 0, 0
23640 +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
23641 + Opcode_slli_Slot_inst_encode, 0, 0
23644 +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
23645 + Opcode_srai_Slot_inst_encode, 0, 0
23648 +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
23649 + Opcode_srli_Slot_inst_encode, 0, 0
23652 +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
23653 + Opcode_memw_Slot_inst_encode, 0, 0
23656 +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
23657 + Opcode_extw_Slot_inst_encode, 0, 0
23660 +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
23661 + Opcode_isync_Slot_inst_encode, 0, 0
23664 +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
23665 + Opcode_rsync_Slot_inst_encode, 0, 0
23668 +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
23669 + Opcode_esync_Slot_inst_encode, 0, 0
23672 +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
23673 + Opcode_dsync_Slot_inst_encode, 0, 0
23676 +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
23677 + Opcode_rsil_Slot_inst_encode, 0, 0
23680 +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
23681 + Opcode_rsr_lend_Slot_inst_encode, 0, 0
23684 +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
23685 + Opcode_wsr_lend_Slot_inst_encode, 0, 0
23688 +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
23689 + Opcode_xsr_lend_Slot_inst_encode, 0, 0
23692 +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
23693 + Opcode_rsr_lcount_Slot_inst_encode, 0, 0
23696 +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
23697 + Opcode_wsr_lcount_Slot_inst_encode, 0, 0
23700 +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
23701 + Opcode_xsr_lcount_Slot_inst_encode, 0, 0
23704 +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
23705 + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
23708 +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
23709 + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
23712 +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
23713 + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
23716 +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
23717 + Opcode_rsr_sar_Slot_inst_encode, 0, 0
23720 +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
23721 + Opcode_wsr_sar_Slot_inst_encode, 0, 0
23724 +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
23725 + Opcode_xsr_sar_Slot_inst_encode, 0, 0
23728 +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
23729 + Opcode_rsr_litbase_Slot_inst_encode, 0, 0
23732 +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
23733 + Opcode_wsr_litbase_Slot_inst_encode, 0, 0
23736 +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
23737 + Opcode_xsr_litbase_Slot_inst_encode, 0, 0
23740 +xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
23741 + Opcode_rsr_176_Slot_inst_encode, 0, 0
23744 +xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
23745 + Opcode_rsr_208_Slot_inst_encode, 0, 0
23748 +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
23749 + Opcode_rsr_ps_Slot_inst_encode, 0, 0
23752 +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
23753 + Opcode_wsr_ps_Slot_inst_encode, 0, 0
23756 +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
23757 + Opcode_xsr_ps_Slot_inst_encode, 0, 0
23760 +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
23761 + Opcode_rsr_epc1_Slot_inst_encode, 0, 0
23764 +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
23765 + Opcode_wsr_epc1_Slot_inst_encode, 0, 0
23768 +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
23769 + Opcode_xsr_epc1_Slot_inst_encode, 0, 0
23772 +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
23773 + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
23776 +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
23777 + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
23780 +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
23781 + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
23784 +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
23785 + Opcode_rsr_epc2_Slot_inst_encode, 0, 0
23788 +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
23789 + Opcode_wsr_epc2_Slot_inst_encode, 0, 0
23792 +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
23793 + Opcode_xsr_epc2_Slot_inst_encode, 0, 0
23796 +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
23797 + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
23800 +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
23801 + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
23804 +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
23805 + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
23808 +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
23809 + Opcode_rsr_epc3_Slot_inst_encode, 0, 0
23812 +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
23813 + Opcode_wsr_epc3_Slot_inst_encode, 0, 0
23816 +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
23817 + Opcode_xsr_epc3_Slot_inst_encode, 0, 0
23820 +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
23821 + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
23824 +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
23825 + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
23828 +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
23829 + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
23832 +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
23833 + Opcode_rsr_epc4_Slot_inst_encode, 0, 0
23836 +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
23837 + Opcode_wsr_epc4_Slot_inst_encode, 0, 0
23840 +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
23841 + Opcode_xsr_epc4_Slot_inst_encode, 0, 0
23844 +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
23845 + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
23848 +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
23849 + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
23852 +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
23853 + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
23856 +xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
23857 + Opcode_rsr_epc5_Slot_inst_encode, 0, 0
23860 +xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
23861 + Opcode_wsr_epc5_Slot_inst_encode, 0, 0
23864 +xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
23865 + Opcode_xsr_epc5_Slot_inst_encode, 0, 0
23868 +xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
23869 + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
23872 +xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
23873 + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
23876 +xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
23877 + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
23880 +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
23881 + Opcode_rsr_eps2_Slot_inst_encode, 0, 0
23884 +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
23885 + Opcode_wsr_eps2_Slot_inst_encode, 0, 0
23888 +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
23889 + Opcode_xsr_eps2_Slot_inst_encode, 0, 0
23892 +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
23893 + Opcode_rsr_eps3_Slot_inst_encode, 0, 0
23896 +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
23897 + Opcode_wsr_eps3_Slot_inst_encode, 0, 0
23900 +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
23901 + Opcode_xsr_eps3_Slot_inst_encode, 0, 0
23904 +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
23905 + Opcode_rsr_eps4_Slot_inst_encode, 0, 0
23908 +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
23909 + Opcode_wsr_eps4_Slot_inst_encode, 0, 0
23912 +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
23913 + Opcode_xsr_eps4_Slot_inst_encode, 0, 0
23916 +xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
23917 + Opcode_rsr_eps5_Slot_inst_encode, 0, 0
23920 +xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
23921 + Opcode_wsr_eps5_Slot_inst_encode, 0, 0
23924 +xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
23925 + Opcode_xsr_eps5_Slot_inst_encode, 0, 0
23928 +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
23929 + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
23932 +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
23933 + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
23936 +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
23937 + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
23940 +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
23941 + Opcode_rsr_depc_Slot_inst_encode, 0, 0
23944 +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
23945 + Opcode_wsr_depc_Slot_inst_encode, 0, 0
23948 +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
23949 + Opcode_xsr_depc_Slot_inst_encode, 0, 0
23952 +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
23953 + Opcode_rsr_exccause_Slot_inst_encode, 0, 0
23956 +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
23957 + Opcode_wsr_exccause_Slot_inst_encode, 0, 0
23960 +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
23961 + Opcode_xsr_exccause_Slot_inst_encode, 0, 0
23964 +xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
23965 + Opcode_rsr_misc0_Slot_inst_encode, 0, 0
23968 +xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
23969 + Opcode_wsr_misc0_Slot_inst_encode, 0, 0
23972 +xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
23973 + Opcode_xsr_misc0_Slot_inst_encode, 0, 0
23976 +xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
23977 + Opcode_rsr_misc1_Slot_inst_encode, 0, 0
23980 +xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
23981 + Opcode_wsr_misc1_Slot_inst_encode, 0, 0
23984 +xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
23985 + Opcode_xsr_misc1_Slot_inst_encode, 0, 0
23988 +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
23989 + Opcode_rsr_prid_Slot_inst_encode, 0, 0
23992 +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
23993 + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
23996 +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
23997 + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
24000 +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
24001 + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
24004 +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
24005 + Opcode_rfi_Slot_inst_encode, 0, 0
24008 +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
24009 + Opcode_waiti_Slot_inst_encode, 0, 0
24012 +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
24013 + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
24016 +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
24017 + Opcode_wsr_intset_Slot_inst_encode, 0, 0
24020 +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
24021 + Opcode_wsr_intclear_Slot_inst_encode, 0, 0
24024 +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
24025 + Opcode_rsr_intenable_Slot_inst_encode, 0, 0
24028 +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
24029 + Opcode_wsr_intenable_Slot_inst_encode, 0, 0
24032 +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
24033 + Opcode_xsr_intenable_Slot_inst_encode, 0, 0
24036 +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
24037 + Opcode_break_Slot_inst_encode, 0, 0
24040 +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
24041 + 0, 0, Opcode_break_n_Slot_inst16b_encode
24044 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
24045 + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
24048 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
24049 + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
24052 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
24053 + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
24056 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
24057 + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
24060 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
24061 + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
24064 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
24065 + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
24068 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
24069 + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
24073 -Slot_inst16a_decode (const xtensa_insnbuf insn)
24075 - switch (Field_op0_Slot_inst16a_get (insn))
24078 - return 31; /* l32i.n */
24080 - return 36; /* s32i.n */
24082 - return 26; /* add.n */
24084 - return 27; /* addi.n */
24088 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
24089 + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
24093 -Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
24095 - switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
24098 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24099 - return 41; /* add */
24100 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24101 - return 42; /* sub */
24102 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24103 - return 43; /* addx2 */
24104 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24105 - return 49; /* and */
24106 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24107 - return 450; /* sext */
24110 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24111 - return 27; /* addi.n */
24112 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24113 - return 44; /* addx4 */
24114 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24115 - return 50; /* or */
24116 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24117 - return 51; /* xor */
24118 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24119 - return 113; /* srli */
24122 - if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
24123 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
24124 - return 33; /* movi.n */
24125 - if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
24126 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24127 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24128 - return 32; /* mov.n */
24129 - if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24130 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24131 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24132 - return 97; /* nop */
24133 - if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
24134 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24135 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24136 - return 96; /* abs */
24137 - if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
24138 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24139 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24140 - return 95; /* neg */
24141 - if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
24142 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24143 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24144 - return 110; /* sra */
24145 - if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24146 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24147 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24148 - return 109; /* srl */
24149 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
24150 - return 112; /* srai */
24153 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
24154 + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
24158 -Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
24160 - switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
24163 - if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
24164 - return 78; /* extui */
24165 - switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
24168 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24171 - if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
24173 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24175 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
24176 - return 97; /* nop */
24181 - return 49; /* and */
24183 - return 50; /* or */
24185 - return 51; /* xor */
24187 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24190 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24191 - return 102; /* ssr */
24194 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24195 - return 103; /* ssl */
24198 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24199 - return 104; /* ssa8l */
24202 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24203 - return 105; /* ssa8b */
24206 - if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
24207 - return 106; /* ssai */
24210 - return 448; /* nsa */
24212 - return 449; /* nsau */
24216 - switch (Field_s_Slot_xt_flix64_slot0_get (insn))
24219 - return 95; /* neg */
24221 - return 96; /* abs */
24225 - return 41; /* add */
24227 - return 43; /* addx2 */
24229 - return 44; /* addx4 */
24231 - return 45; /* addx8 */
24233 - return 42; /* sub */
24235 - return 46; /* subx2 */
24237 - return 47; /* subx4 */
24239 - return 48; /* subx8 */
24243 - if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
24244 - return 112; /* srai */
24245 - if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
24246 - return 111; /* slli */
24247 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24250 - return 113; /* srli */
24252 - return 108; /* src */
24254 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24255 - return 109; /* srl */
24258 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24259 - return 107; /* sll */
24262 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24263 - return 110; /* sra */
24266 - return 296; /* mul16u */
24268 - return 297; /* mul16s */
24272 - if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
24273 - return 461; /* mull */
24276 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24279 - return 450; /* sext */
24281 - return 443; /* clamps */
24283 - return 444; /* min */
24285 - return 445; /* max */
24287 - return 446; /* minu */
24289 - return 447; /* maxu */
24291 - return 91; /* moveqz */
24293 - return 92; /* movnez */
24295 - return 93; /* movltz */
24297 - return 94; /* movgez */
24303 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24306 - return 86; /* l8ui */
24308 - return 82; /* l16ui */
24310 - return 84; /* l32i */
24312 - return 101; /* s8i */
24314 - return 99; /* s16i */
24316 - return 100; /* s32i */
24318 - return 83; /* l16si */
24320 - return 90; /* movi */
24322 - return 39; /* addi */
24324 - return 40; /* addmi */
24328 - if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
24329 - return 85; /* l32r */
24330 - if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
24331 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
24332 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
24333 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
24334 - return 32; /* mov.n */
24337 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
24338 + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
24342 -Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
24344 - if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
24345 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24346 - return 78; /* extui */
24347 - switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24350 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24351 - return 90; /* movi */
24354 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24355 - return 39; /* addi */
24358 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24359 - return 40; /* addmi */
24360 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24361 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
24362 - return 51; /* xor */
24365 - switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24368 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24369 - return 111; /* slli */
24372 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24373 - return 112; /* srai */
24376 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24377 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24378 - return 107; /* sll */
24381 - switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24384 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24385 - return 41; /* add */
24388 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24389 - return 45; /* addx8 */
24392 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24393 - return 43; /* addx2 */
24396 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24397 - return 49; /* and */
24400 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24401 - return 91; /* moveqz */
24404 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24405 - return 94; /* movgez */
24408 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24409 - return 44; /* addx4 */
24412 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24413 - return 93; /* movltz */
24416 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24417 - return 92; /* movnez */
24420 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24421 - return 296; /* mul16u */
24424 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24425 - return 297; /* mul16s */
24428 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24429 - return 461; /* mull */
24432 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24433 - return 50; /* or */
24436 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24437 - return 450; /* sext */
24440 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24441 - return 108; /* src */
24444 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24445 - return 113; /* srli */
24448 - if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
24449 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24450 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24451 - return 32; /* mov.n */
24452 - if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
24453 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24454 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24455 - return 81; /* jx */
24456 - if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
24457 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24458 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24459 - return 103; /* ssl */
24460 - if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
24461 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24462 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24463 - return 97; /* nop */
24464 - if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
24465 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24466 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24467 - return 95; /* neg */
24468 - if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
24469 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24470 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24471 - return 110; /* sra */
24472 - if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
24473 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24474 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24475 - return 109; /* srl */
24476 - if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
24477 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24478 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24479 - return 42; /* sub */
24480 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
24481 - return 80; /* j */
24484 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
24485 + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
24488 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
24489 + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
24493 -Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
24495 - switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
24498 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24499 - return 516; /* bbci.w18 */
24502 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24503 - return 517; /* bbsi.w18 */
24506 - if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24507 - return 526; /* ball.w18 */
24510 - if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24511 - return 524; /* bany.w18 */
24514 - if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24515 - return 528; /* bbc.w18 */
24518 - if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24519 - return 529; /* bbs.w18 */
24522 - if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24523 - return 518; /* beq.w18 */
24526 - if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24527 - return 510; /* beqi.w18 */
24530 - if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24531 - return 520; /* bge.w18 */
24534 - if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24535 - return 512; /* bgei.w18 */
24538 - if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24539 - return 522; /* bgeu.w18 */
24542 - if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24543 - return 514; /* bgeui.w18 */
24546 - if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24547 - return 521; /* blt.w18 */
24550 - if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24551 - return 513; /* blti.w18 */
24554 - if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24555 - return 523; /* bltu.w18 */
24558 - if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24559 - return 515; /* bltui.w18 */
24562 - if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24563 - return 527; /* bnall.w18 */
24566 - if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24567 - return 519; /* bne.w18 */
24570 - if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24571 - return 511; /* bnei.w18 */
24574 - if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24575 - return 525; /* bnone.w18 */
24578 - if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24579 - return 506; /* beqz.w18 */
24582 - if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24583 - return 508; /* bgez.w18 */
24586 - if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24587 - return 509; /* bltz.w18 */
24590 - if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24591 - return 507; /* bnez.w18 */
24594 - if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24595 - return 97; /* nop */
24600 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
24601 + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
24605 -/* Instruction slots. */
24606 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
24607 + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
24611 -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
24612 - xtensa_insnbuf slotbuf)
24615 - slotbuf[0] = (insn[0] & 0xffffff);
24617 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
24618 + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
24622 -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
24623 - const xtensa_insnbuf slotbuf)
24625 - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
24627 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
24628 + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
24632 -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
24633 - xtensa_insnbuf slotbuf)
24636 - slotbuf[0] = (insn[0] & 0xffff);
24638 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
24639 + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
24643 -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
24644 - const xtensa_insnbuf slotbuf)
24646 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24648 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
24649 + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
24653 -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
24654 - xtensa_insnbuf slotbuf)
24657 - slotbuf[0] = (insn[0] & 0xffff);
24659 +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
24660 + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
24664 -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
24665 - const xtensa_insnbuf slotbuf)
24667 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24669 +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
24670 + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
24674 -Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24675 - xtensa_insnbuf slotbuf)
24678 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24680 +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
24681 + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
24685 -Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24686 - const xtensa_insnbuf slotbuf)
24688 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24690 +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
24691 + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
24695 -Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24696 - xtensa_insnbuf slotbuf)
24699 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24701 +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
24702 + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
24706 -Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24707 - const xtensa_insnbuf slotbuf)
24709 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24711 +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
24712 + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
24716 -Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
24717 - xtensa_insnbuf slotbuf)
24720 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24721 - slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
24723 +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
24724 + Opcode_rsr_icount_Slot_inst_encode, 0, 0
24728 -Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
24729 - const xtensa_insnbuf slotbuf)
24731 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24732 - insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
24734 +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
24735 + Opcode_wsr_icount_Slot_inst_encode, 0, 0
24739 -Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
24740 - xtensa_insnbuf slotbuf)
24743 - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
24745 +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
24746 + Opcode_xsr_icount_Slot_inst_encode, 0, 0
24750 -Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
24751 - const xtensa_insnbuf slotbuf)
24753 - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
24755 +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
24756 + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
24760 -Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
24761 - xtensa_insnbuf slotbuf)
24763 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24764 - slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
24765 - slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
24767 +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
24768 + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
24772 -Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
24773 - const xtensa_insnbuf slotbuf)
24775 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24776 - insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
24777 - insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
24779 +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
24780 + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
24783 -static xtensa_get_field_fn
24784 -Slot_inst_get_field_fns[] = {
24785 - Field_t_Slot_inst_get,
24786 - Field_bbi4_Slot_inst_get,
24787 - Field_bbi_Slot_inst_get,
24788 - Field_imm12_Slot_inst_get,
24789 - Field_imm8_Slot_inst_get,
24790 - Field_s_Slot_inst_get,
24791 - Field_imm12b_Slot_inst_get,
24792 - Field_imm16_Slot_inst_get,
24793 - Field_m_Slot_inst_get,
24794 - Field_n_Slot_inst_get,
24795 - Field_offset_Slot_inst_get,
24796 - Field_op0_Slot_inst_get,
24797 - Field_op1_Slot_inst_get,
24798 - Field_op2_Slot_inst_get,
24799 - Field_r_Slot_inst_get,
24800 - Field_sa4_Slot_inst_get,
24801 - Field_sae4_Slot_inst_get,
24802 - Field_sae_Slot_inst_get,
24803 - Field_sal_Slot_inst_get,
24804 - Field_sargt_Slot_inst_get,
24805 - Field_sas4_Slot_inst_get,
24806 - Field_sas_Slot_inst_get,
24807 - Field_sr_Slot_inst_get,
24808 - Field_st_Slot_inst_get,
24809 - Field_thi3_Slot_inst_get,
24810 - Field_imm4_Slot_inst_get,
24811 - Field_mn_Slot_inst_get,
24820 - Field_r3_Slot_inst_get,
24821 - Field_rbit2_Slot_inst_get,
24822 - Field_rhi_Slot_inst_get,
24823 - Field_t3_Slot_inst_get,
24824 - Field_tbit2_Slot_inst_get,
24825 - Field_tlo_Slot_inst_get,
24826 - Field_w_Slot_inst_get,
24827 - Field_y_Slot_inst_get,
24828 - Field_x_Slot_inst_get,
24829 - Field_t2_Slot_inst_get,
24830 - Field_s2_Slot_inst_get,
24831 - Field_r2_Slot_inst_get,
24832 - Field_t4_Slot_inst_get,
24833 - Field_s4_Slot_inst_get,
24834 - Field_r4_Slot_inst_get,
24835 - Field_t8_Slot_inst_get,
24836 - Field_s8_Slot_inst_get,
24837 - Field_r8_Slot_inst_get,
24838 - Field_xt_wbr15_imm_Slot_inst_get,
24839 - Field_xt_wbr18_imm_Slot_inst_get,
24908 - Implicit_Field_ar0_get,
24909 - Implicit_Field_ar4_get,
24910 - Implicit_Field_ar8_get,
24911 - Implicit_Field_ar12_get,
24912 - Implicit_Field_mr0_get,
24913 - Implicit_Field_mr1_get,
24914 - Implicit_Field_mr2_get,
24915 - Implicit_Field_mr3_get,
24916 - Implicit_Field_bt16_get,
24917 - Implicit_Field_bs16_get,
24918 - Implicit_Field_br16_get,
24919 - Implicit_Field_brall_get
24920 +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
24921 + Opcode_rsr_ddr_Slot_inst_encode, 0, 0
24924 +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
24925 + Opcode_wsr_ddr_Slot_inst_encode, 0, 0
24928 -static xtensa_set_field_fn
24929 -Slot_inst_set_field_fns[] = {
24930 - Field_t_Slot_inst_set,
24931 - Field_bbi4_Slot_inst_set,
24932 - Field_bbi_Slot_inst_set,
24933 - Field_imm12_Slot_inst_set,
24934 - Field_imm8_Slot_inst_set,
24935 - Field_s_Slot_inst_set,
24936 - Field_imm12b_Slot_inst_set,
24937 - Field_imm16_Slot_inst_set,
24938 - Field_m_Slot_inst_set,
24939 - Field_n_Slot_inst_set,
24940 - Field_offset_Slot_inst_set,
24941 - Field_op0_Slot_inst_set,
24942 - Field_op1_Slot_inst_set,
24943 - Field_op2_Slot_inst_set,
24944 - Field_r_Slot_inst_set,
24945 - Field_sa4_Slot_inst_set,
24946 - Field_sae4_Slot_inst_set,
24947 - Field_sae_Slot_inst_set,
24948 - Field_sal_Slot_inst_set,
24949 - Field_sargt_Slot_inst_set,
24950 - Field_sas4_Slot_inst_set,
24951 - Field_sas_Slot_inst_set,
24952 - Field_sr_Slot_inst_set,
24953 - Field_st_Slot_inst_set,
24954 - Field_thi3_Slot_inst_set,
24955 - Field_imm4_Slot_inst_set,
24956 - Field_mn_Slot_inst_set,
24965 - Field_r3_Slot_inst_set,
24966 - Field_rbit2_Slot_inst_set,
24967 - Field_rhi_Slot_inst_set,
24968 - Field_t3_Slot_inst_set,
24969 - Field_tbit2_Slot_inst_set,
24970 - Field_tlo_Slot_inst_set,
24971 - Field_w_Slot_inst_set,
24972 - Field_y_Slot_inst_set,
24973 - Field_x_Slot_inst_set,
24974 - Field_t2_Slot_inst_set,
24975 - Field_s2_Slot_inst_set,
24976 - Field_r2_Slot_inst_set,
24977 - Field_t4_Slot_inst_set,
24978 - Field_s4_Slot_inst_set,
24979 - Field_r4_Slot_inst_set,
24980 - Field_t8_Slot_inst_set,
24981 - Field_s8_Slot_inst_set,
24982 - Field_r8_Slot_inst_set,
24983 - Field_xt_wbr15_imm_Slot_inst_set,
24984 - Field_xt_wbr18_imm_Slot_inst_set,
25053 - Implicit_Field_set,
25054 - Implicit_Field_set,
25055 - Implicit_Field_set,
25056 - Implicit_Field_set,
25057 - Implicit_Field_set,
25058 - Implicit_Field_set,
25059 - Implicit_Field_set,
25060 - Implicit_Field_set,
25061 - Implicit_Field_set,
25062 - Implicit_Field_set,
25063 - Implicit_Field_set,
25064 - Implicit_Field_set
25065 +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
25066 + Opcode_xsr_ddr_Slot_inst_encode, 0, 0
25069 -static xtensa_get_field_fn
25070 -Slot_inst16a_get_field_fns[] = {
25071 - Field_t_Slot_inst16a_get,
25076 - Field_s_Slot_inst16a_get,
25082 - Field_op0_Slot_inst16a_get,
25085 - Field_r_Slot_inst16a_get,
25093 - Field_sr_Slot_inst16a_get,
25094 - Field_st_Slot_inst16a_get,
25096 - Field_imm4_Slot_inst16a_get,
25098 - Field_i_Slot_inst16a_get,
25099 - Field_imm6lo_Slot_inst16a_get,
25100 - Field_imm6hi_Slot_inst16a_get,
25101 - Field_imm7lo_Slot_inst16a_get,
25102 - Field_imm7hi_Slot_inst16a_get,
25103 - Field_z_Slot_inst16a_get,
25104 - Field_imm6_Slot_inst16a_get,
25105 - Field_imm7_Slot_inst16a_get,
25115 - Field_t2_Slot_inst16a_get,
25116 - Field_s2_Slot_inst16a_get,
25117 - Field_r2_Slot_inst16a_get,
25118 - Field_t4_Slot_inst16a_get,
25119 - Field_s4_Slot_inst16a_get,
25120 - Field_r4_Slot_inst16a_get,
25121 - Field_t8_Slot_inst16a_get,
25122 - Field_s8_Slot_inst16a_get,
25123 - Field_r8_Slot_inst16a_get,
25194 - Implicit_Field_ar0_get,
25195 - Implicit_Field_ar4_get,
25196 - Implicit_Field_ar8_get,
25197 - Implicit_Field_ar12_get,
25198 - Implicit_Field_mr0_get,
25199 - Implicit_Field_mr1_get,
25200 - Implicit_Field_mr2_get,
25201 - Implicit_Field_mr3_get,
25202 - Implicit_Field_bt16_get,
25203 - Implicit_Field_bs16_get,
25204 - Implicit_Field_br16_get,
25205 - Implicit_Field_brall_get
25206 +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
25207 + Opcode_rfdo_Slot_inst_encode, 0, 0
25210 +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
25211 + Opcode_rfdd_Slot_inst_encode, 0, 0
25214 +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
25215 + Opcode_wsr_mmid_Slot_inst_encode, 0, 0
25218 +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
25219 + Opcode_rsr_ccount_Slot_inst_encode, 0, 0
25222 +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
25223 + Opcode_wsr_ccount_Slot_inst_encode, 0, 0
25226 +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
25227 + Opcode_xsr_ccount_Slot_inst_encode, 0, 0
25230 -static xtensa_set_field_fn
25231 -Slot_inst16a_set_field_fns[] = {
25232 - Field_t_Slot_inst16a_set,
25237 - Field_s_Slot_inst16a_set,
25243 - Field_op0_Slot_inst16a_set,
25246 - Field_r_Slot_inst16a_set,
25254 - Field_sr_Slot_inst16a_set,
25255 - Field_st_Slot_inst16a_set,
25257 - Field_imm4_Slot_inst16a_set,
25259 - Field_i_Slot_inst16a_set,
25260 - Field_imm6lo_Slot_inst16a_set,
25261 - Field_imm6hi_Slot_inst16a_set,
25262 - Field_imm7lo_Slot_inst16a_set,
25263 - Field_imm7hi_Slot_inst16a_set,
25264 - Field_z_Slot_inst16a_set,
25265 - Field_imm6_Slot_inst16a_set,
25266 - Field_imm7_Slot_inst16a_set,
25276 - Field_t2_Slot_inst16a_set,
25277 - Field_s2_Slot_inst16a_set,
25278 - Field_r2_Slot_inst16a_set,
25279 - Field_t4_Slot_inst16a_set,
25280 - Field_s4_Slot_inst16a_set,
25281 - Field_r4_Slot_inst16a_set,
25282 - Field_t8_Slot_inst16a_set,
25283 - Field_s8_Slot_inst16a_set,
25284 - Field_r8_Slot_inst16a_set,
25355 - Implicit_Field_set,
25356 - Implicit_Field_set,
25357 - Implicit_Field_set,
25358 - Implicit_Field_set,
25359 - Implicit_Field_set,
25360 - Implicit_Field_set,
25361 - Implicit_Field_set,
25362 - Implicit_Field_set,
25363 - Implicit_Field_set,
25364 - Implicit_Field_set,
25365 - Implicit_Field_set,
25366 - Implicit_Field_set
25367 +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
25368 + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
25371 -static xtensa_get_field_fn
25372 -Slot_inst16b_get_field_fns[] = {
25373 - Field_t_Slot_inst16b_get,
25378 - Field_s_Slot_inst16b_get,
25384 - Field_op0_Slot_inst16b_get,
25387 - Field_r_Slot_inst16b_get,
25395 - Field_sr_Slot_inst16b_get,
25396 - Field_st_Slot_inst16b_get,
25398 - Field_imm4_Slot_inst16b_get,
25400 - Field_i_Slot_inst16b_get,
25401 - Field_imm6lo_Slot_inst16b_get,
25402 - Field_imm6hi_Slot_inst16b_get,
25403 - Field_imm7lo_Slot_inst16b_get,
25404 - Field_imm7hi_Slot_inst16b_get,
25405 - Field_z_Slot_inst16b_get,
25406 - Field_imm6_Slot_inst16b_get,
25407 - Field_imm7_Slot_inst16b_get,
25417 - Field_t2_Slot_inst16b_get,
25418 - Field_s2_Slot_inst16b_get,
25419 - Field_r2_Slot_inst16b_get,
25420 - Field_t4_Slot_inst16b_get,
25421 - Field_s4_Slot_inst16b_get,
25422 - Field_r4_Slot_inst16b_get,
25423 - Field_t8_Slot_inst16b_get,
25424 - Field_s8_Slot_inst16b_get,
25425 - Field_r8_Slot_inst16b_get,
25496 - Implicit_Field_ar0_get,
25497 - Implicit_Field_ar4_get,
25498 - Implicit_Field_ar8_get,
25499 - Implicit_Field_ar12_get,
25500 - Implicit_Field_mr0_get,
25501 - Implicit_Field_mr1_get,
25502 - Implicit_Field_mr2_get,
25503 - Implicit_Field_mr3_get,
25504 - Implicit_Field_bt16_get,
25505 - Implicit_Field_bs16_get,
25506 - Implicit_Field_br16_get,
25507 - Implicit_Field_brall_get
25508 +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
25509 + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
25512 +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
25513 + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
25516 +xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
25517 + Opcode_idtlb_Slot_inst_encode, 0, 0
25520 -static xtensa_set_field_fn
25521 -Slot_inst16b_set_field_fns[] = {
25522 - Field_t_Slot_inst16b_set,
25527 - Field_s_Slot_inst16b_set,
25533 - Field_op0_Slot_inst16b_set,
25536 - Field_r_Slot_inst16b_set,
25544 - Field_sr_Slot_inst16b_set,
25545 - Field_st_Slot_inst16b_set,
25547 - Field_imm4_Slot_inst16b_set,
25549 - Field_i_Slot_inst16b_set,
25550 - Field_imm6lo_Slot_inst16b_set,
25551 - Field_imm6hi_Slot_inst16b_set,
25552 - Field_imm7lo_Slot_inst16b_set,
25553 - Field_imm7hi_Slot_inst16b_set,
25554 - Field_z_Slot_inst16b_set,
25555 - Field_imm6_Slot_inst16b_set,
25556 - Field_imm7_Slot_inst16b_set,
25566 - Field_t2_Slot_inst16b_set,
25567 - Field_s2_Slot_inst16b_set,
25568 - Field_r2_Slot_inst16b_set,
25569 - Field_t4_Slot_inst16b_set,
25570 - Field_s4_Slot_inst16b_set,
25571 - Field_r4_Slot_inst16b_set,
25572 - Field_t8_Slot_inst16b_set,
25573 - Field_s8_Slot_inst16b_set,
25574 - Field_r8_Slot_inst16b_set,
25645 - Implicit_Field_set,
25646 - Implicit_Field_set,
25647 - Implicit_Field_set,
25648 - Implicit_Field_set,
25649 - Implicit_Field_set,
25650 - Implicit_Field_set,
25651 - Implicit_Field_set,
25652 - Implicit_Field_set,
25653 - Implicit_Field_set,
25654 - Implicit_Field_set,
25655 - Implicit_Field_set,
25656 - Implicit_Field_set
25657 +xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
25658 + Opcode_pdtlb_Slot_inst_encode, 0, 0
25661 -static xtensa_get_field_fn
25662 -Slot_xt_flix64_slot0_get_field_fns[] = {
25663 - Field_t_Slot_xt_flix64_slot0_get,
25667 - Field_imm8_Slot_xt_flix64_slot0_get,
25668 - Field_s_Slot_xt_flix64_slot0_get,
25669 - Field_imm12b_Slot_xt_flix64_slot0_get,
25670 - Field_imm16_Slot_xt_flix64_slot0_get,
25671 - Field_m_Slot_xt_flix64_slot0_get,
25672 - Field_n_Slot_xt_flix64_slot0_get,
25675 - Field_op1_Slot_xt_flix64_slot0_get,
25676 - Field_op2_Slot_xt_flix64_slot0_get,
25677 - Field_r_Slot_xt_flix64_slot0_get,
25679 - Field_sae4_Slot_xt_flix64_slot0_get,
25680 - Field_sae_Slot_xt_flix64_slot0_get,
25681 - Field_sal_Slot_xt_flix64_slot0_get,
25682 - Field_sargt_Slot_xt_flix64_slot0_get,
25684 - Field_sas_Slot_xt_flix64_slot0_get,
25687 - Field_thi3_Slot_xt_flix64_slot0_get,
25718 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
25719 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
25720 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
25721 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
25722 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
25723 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25785 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25786 - Implicit_Field_ar0_get,
25787 - Implicit_Field_ar4_get,
25788 - Implicit_Field_ar8_get,
25789 - Implicit_Field_ar12_get,
25790 - Implicit_Field_mr0_get,
25791 - Implicit_Field_mr1_get,
25792 - Implicit_Field_mr2_get,
25793 - Implicit_Field_mr3_get,
25794 - Implicit_Field_bt16_get,
25795 - Implicit_Field_bs16_get,
25796 - Implicit_Field_br16_get,
25797 - Implicit_Field_brall_get
25798 +xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
25799 + Opcode_rdtlb0_Slot_inst_encode, 0, 0
25802 +xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
25803 + Opcode_rdtlb1_Slot_inst_encode, 0, 0
25806 +xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
25807 + Opcode_wdtlb_Slot_inst_encode, 0, 0
25810 +xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
25811 + Opcode_iitlb_Slot_inst_encode, 0, 0
25814 +xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
25815 + Opcode_pitlb_Slot_inst_encode, 0, 0
25818 +xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
25819 + Opcode_ritlb0_Slot_inst_encode, 0, 0
25822 +xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
25823 + Opcode_ritlb1_Slot_inst_encode, 0, 0
25826 +xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
25827 + Opcode_witlb_Slot_inst_encode, 0, 0
25830 +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
25831 + Opcode_min_Slot_inst_encode, 0, 0
25834 +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
25835 + Opcode_max_Slot_inst_encode, 0, 0
25838 +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
25839 + Opcode_minu_Slot_inst_encode, 0, 0
25842 +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
25843 + Opcode_maxu_Slot_inst_encode, 0, 0
25846 +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
25847 + Opcode_nsa_Slot_inst_encode, 0, 0
25850 +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
25851 + Opcode_nsau_Slot_inst_encode, 0, 0
25854 +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
25855 + Opcode_sext_Slot_inst_encode, 0, 0
25858 +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
25859 + Opcode_l32ai_Slot_inst_encode, 0, 0
25862 +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
25863 + Opcode_s32ri_Slot_inst_encode, 0, 0
25866 +xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
25867 + Opcode_s32c1i_Slot_inst_encode, 0, 0
25870 +xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
25871 + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
25874 +xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
25875 + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
25878 +xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
25879 + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
25882 +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
25883 + Opcode_mull_Slot_inst_encode, 0, 0
25886 +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
25887 + Opcode_muluh_Slot_inst_encode, 0, 0
25890 +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
25891 + Opcode_mulsh_Slot_inst_encode, 0, 0
25894 +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
25895 + Opcode_mul16u_Slot_inst_encode, 0, 0
25898 +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
25899 + Opcode_mul16s_Slot_inst_encode, 0, 0
25903 +/* Opcode table. */
25905 +static xtensa_opcode_internal opcodes[] = {
25906 + { "excw", 0 /* xt_iclass_excw */,
25908 + Opcode_excw_encode_fns, 0, 0 },
25909 + { "rfe", 1 /* xt_iclass_rfe */,
25910 + XTENSA_OPCODE_IS_JUMP,
25911 + Opcode_rfe_encode_fns, 0, 0 },
25912 + { "rfde", 2 /* xt_iclass_rfde */,
25913 + XTENSA_OPCODE_IS_JUMP,
25914 + Opcode_rfde_encode_fns, 0, 0 },
25915 + { "syscall", 3 /* xt_iclass_syscall */,
25917 + Opcode_syscall_encode_fns, 0, 0 },
25918 + { "simcall", 4 /* xt_iclass_simcall */,
25920 + Opcode_simcall_encode_fns, 0, 0 },
25921 + { "call12", 5 /* xt_iclass_call12 */,
25922 + XTENSA_OPCODE_IS_CALL,
25923 + Opcode_call12_encode_fns, 0, 0 },
25924 + { "call8", 6 /* xt_iclass_call8 */,
25925 + XTENSA_OPCODE_IS_CALL,
25926 + Opcode_call8_encode_fns, 0, 0 },
25927 + { "call4", 7 /* xt_iclass_call4 */,
25928 + XTENSA_OPCODE_IS_CALL,
25929 + Opcode_call4_encode_fns, 0, 0 },
25930 + { "callx12", 8 /* xt_iclass_callx12 */,
25931 + XTENSA_OPCODE_IS_CALL,
25932 + Opcode_callx12_encode_fns, 0, 0 },
25933 + { "callx8", 9 /* xt_iclass_callx8 */,
25934 + XTENSA_OPCODE_IS_CALL,
25935 + Opcode_callx8_encode_fns, 0, 0 },
25936 + { "callx4", 10 /* xt_iclass_callx4 */,
25937 + XTENSA_OPCODE_IS_CALL,
25938 + Opcode_callx4_encode_fns, 0, 0 },
25939 + { "entry", 11 /* xt_iclass_entry */,
25941 + Opcode_entry_encode_fns, 0, 0 },
25942 + { "movsp", 12 /* xt_iclass_movsp */,
25944 + Opcode_movsp_encode_fns, 0, 0 },
25945 + { "rotw", 13 /* xt_iclass_rotw */,
25947 + Opcode_rotw_encode_fns, 0, 0 },
25948 + { "retw", 14 /* xt_iclass_retw */,
25949 + XTENSA_OPCODE_IS_JUMP,
25950 + Opcode_retw_encode_fns, 0, 0 },
25951 + { "retw.n", 14 /* xt_iclass_retw */,
25952 + XTENSA_OPCODE_IS_JUMP,
25953 + Opcode_retw_n_encode_fns, 0, 0 },
25954 + { "rfwo", 15 /* xt_iclass_rfwou */,
25955 + XTENSA_OPCODE_IS_JUMP,
25956 + Opcode_rfwo_encode_fns, 0, 0 },
25957 + { "rfwu", 15 /* xt_iclass_rfwou */,
25958 + XTENSA_OPCODE_IS_JUMP,
25959 + Opcode_rfwu_encode_fns, 0, 0 },
25960 + { "l32e", 16 /* xt_iclass_l32e */,
25962 + Opcode_l32e_encode_fns, 0, 0 },
25963 + { "s32e", 17 /* xt_iclass_s32e */,
25965 + Opcode_s32e_encode_fns, 0, 0 },
25966 + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
25968 + Opcode_rsr_windowbase_encode_fns, 0, 0 },
25969 + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
25971 + Opcode_wsr_windowbase_encode_fns, 0, 0 },
25972 + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
25974 + Opcode_xsr_windowbase_encode_fns, 0, 0 },
25975 + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
25977 + Opcode_rsr_windowstart_encode_fns, 0, 0 },
25978 + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
25980 + Opcode_wsr_windowstart_encode_fns, 0, 0 },
25981 + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
25983 + Opcode_xsr_windowstart_encode_fns, 0, 0 },
25984 + { "add.n", 24 /* xt_iclass_add.n */,
25986 + Opcode_add_n_encode_fns, 0, 0 },
25987 + { "addi.n", 25 /* xt_iclass_addi.n */,
25989 + Opcode_addi_n_encode_fns, 0, 0 },
25990 + { "beqz.n", 26 /* xt_iclass_bz6 */,
25991 + XTENSA_OPCODE_IS_BRANCH,
25992 + Opcode_beqz_n_encode_fns, 0, 0 },
25993 + { "bnez.n", 26 /* xt_iclass_bz6 */,
25994 + XTENSA_OPCODE_IS_BRANCH,
25995 + Opcode_bnez_n_encode_fns, 0, 0 },
25996 + { "ill.n", 27 /* xt_iclass_ill.n */,
25998 + Opcode_ill_n_encode_fns, 0, 0 },
25999 + { "l32i.n", 28 /* xt_iclass_loadi4 */,
26001 + Opcode_l32i_n_encode_fns, 0, 0 },
26002 + { "mov.n", 29 /* xt_iclass_mov.n */,
26004 + Opcode_mov_n_encode_fns, 0, 0 },
26005 + { "movi.n", 30 /* xt_iclass_movi.n */,
26007 + Opcode_movi_n_encode_fns, 0, 0 },
26008 + { "nop.n", 31 /* xt_iclass_nopn */,
26010 + Opcode_nop_n_encode_fns, 0, 0 },
26011 + { "ret.n", 32 /* xt_iclass_retn */,
26012 + XTENSA_OPCODE_IS_JUMP,
26013 + Opcode_ret_n_encode_fns, 0, 0 },
26014 + { "s32i.n", 33 /* xt_iclass_storei4 */,
26016 + Opcode_s32i_n_encode_fns, 0, 0 },
26017 + { "rur.threadptr", 34 /* rur_threadptr */,
26019 + Opcode_rur_threadptr_encode_fns, 0, 0 },
26020 + { "wur.threadptr", 35 /* wur_threadptr */,
26022 + Opcode_wur_threadptr_encode_fns, 0, 0 },
26023 + { "addi", 36 /* xt_iclass_addi */,
26025 + Opcode_addi_encode_fns, 0, 0 },
26026 + { "addmi", 37 /* xt_iclass_addmi */,
26028 + Opcode_addmi_encode_fns, 0, 0 },
26029 + { "add", 38 /* xt_iclass_addsub */,
26031 + Opcode_add_encode_fns, 0, 0 },
26032 + { "sub", 38 /* xt_iclass_addsub */,
26034 + Opcode_sub_encode_fns, 0, 0 },
26035 + { "addx2", 38 /* xt_iclass_addsub */,
26037 + Opcode_addx2_encode_fns, 0, 0 },
26038 + { "addx4", 38 /* xt_iclass_addsub */,
26040 + Opcode_addx4_encode_fns, 0, 0 },
26041 + { "addx8", 38 /* xt_iclass_addsub */,
26043 + Opcode_addx8_encode_fns, 0, 0 },
26044 + { "subx2", 38 /* xt_iclass_addsub */,
26046 + Opcode_subx2_encode_fns, 0, 0 },
26047 + { "subx4", 38 /* xt_iclass_addsub */,
26049 + Opcode_subx4_encode_fns, 0, 0 },
26050 + { "subx8", 38 /* xt_iclass_addsub */,
26052 + Opcode_subx8_encode_fns, 0, 0 },
26053 + { "and", 39 /* xt_iclass_bit */,
26055 + Opcode_and_encode_fns, 0, 0 },
26056 + { "or", 39 /* xt_iclass_bit */,
26058 + Opcode_or_encode_fns, 0, 0 },
26059 + { "xor", 39 /* xt_iclass_bit */,
26061 + Opcode_xor_encode_fns, 0, 0 },
26062 + { "beqi", 40 /* xt_iclass_bsi8 */,
26063 + XTENSA_OPCODE_IS_BRANCH,
26064 + Opcode_beqi_encode_fns, 0, 0 },
26065 + { "bnei", 40 /* xt_iclass_bsi8 */,
26066 + XTENSA_OPCODE_IS_BRANCH,
26067 + Opcode_bnei_encode_fns, 0, 0 },
26068 + { "bgei", 40 /* xt_iclass_bsi8 */,
26069 + XTENSA_OPCODE_IS_BRANCH,
26070 + Opcode_bgei_encode_fns, 0, 0 },
26071 + { "blti", 40 /* xt_iclass_bsi8 */,
26072 + XTENSA_OPCODE_IS_BRANCH,
26073 + Opcode_blti_encode_fns, 0, 0 },
26074 + { "bbci", 41 /* xt_iclass_bsi8b */,
26075 + XTENSA_OPCODE_IS_BRANCH,
26076 + Opcode_bbci_encode_fns, 0, 0 },
26077 + { "bbsi", 41 /* xt_iclass_bsi8b */,
26078 + XTENSA_OPCODE_IS_BRANCH,
26079 + Opcode_bbsi_encode_fns, 0, 0 },
26080 + { "bgeui", 42 /* xt_iclass_bsi8u */,
26081 + XTENSA_OPCODE_IS_BRANCH,
26082 + Opcode_bgeui_encode_fns, 0, 0 },
26083 + { "bltui", 42 /* xt_iclass_bsi8u */,
26084 + XTENSA_OPCODE_IS_BRANCH,
26085 + Opcode_bltui_encode_fns, 0, 0 },
26086 + { "beq", 43 /* xt_iclass_bst8 */,
26087 + XTENSA_OPCODE_IS_BRANCH,
26088 + Opcode_beq_encode_fns, 0, 0 },
26089 + { "bne", 43 /* xt_iclass_bst8 */,
26090 + XTENSA_OPCODE_IS_BRANCH,
26091 + Opcode_bne_encode_fns, 0, 0 },
26092 + { "bge", 43 /* xt_iclass_bst8 */,
26093 + XTENSA_OPCODE_IS_BRANCH,
26094 + Opcode_bge_encode_fns, 0, 0 },
26095 + { "blt", 43 /* xt_iclass_bst8 */,
26096 + XTENSA_OPCODE_IS_BRANCH,
26097 + Opcode_blt_encode_fns, 0, 0 },
26098 + { "bgeu", 43 /* xt_iclass_bst8 */,
26099 + XTENSA_OPCODE_IS_BRANCH,
26100 + Opcode_bgeu_encode_fns, 0, 0 },
26101 + { "bltu", 43 /* xt_iclass_bst8 */,
26102 + XTENSA_OPCODE_IS_BRANCH,
26103 + Opcode_bltu_encode_fns, 0, 0 },
26104 + { "bany", 43 /* xt_iclass_bst8 */,
26105 + XTENSA_OPCODE_IS_BRANCH,
26106 + Opcode_bany_encode_fns, 0, 0 },
26107 + { "bnone", 43 /* xt_iclass_bst8 */,
26108 + XTENSA_OPCODE_IS_BRANCH,
26109 + Opcode_bnone_encode_fns, 0, 0 },
26110 + { "ball", 43 /* xt_iclass_bst8 */,
26111 + XTENSA_OPCODE_IS_BRANCH,
26112 + Opcode_ball_encode_fns, 0, 0 },
26113 + { "bnall", 43 /* xt_iclass_bst8 */,
26114 + XTENSA_OPCODE_IS_BRANCH,
26115 + Opcode_bnall_encode_fns, 0, 0 },
26116 + { "bbc", 43 /* xt_iclass_bst8 */,
26117 + XTENSA_OPCODE_IS_BRANCH,
26118 + Opcode_bbc_encode_fns, 0, 0 },
26119 + { "bbs", 43 /* xt_iclass_bst8 */,
26120 + XTENSA_OPCODE_IS_BRANCH,
26121 + Opcode_bbs_encode_fns, 0, 0 },
26122 + { "beqz", 44 /* xt_iclass_bsz12 */,
26123 + XTENSA_OPCODE_IS_BRANCH,
26124 + Opcode_beqz_encode_fns, 0, 0 },
26125 + { "bnez", 44 /* xt_iclass_bsz12 */,
26126 + XTENSA_OPCODE_IS_BRANCH,
26127 + Opcode_bnez_encode_fns, 0, 0 },
26128 + { "bgez", 44 /* xt_iclass_bsz12 */,
26129 + XTENSA_OPCODE_IS_BRANCH,
26130 + Opcode_bgez_encode_fns, 0, 0 },
26131 + { "bltz", 44 /* xt_iclass_bsz12 */,
26132 + XTENSA_OPCODE_IS_BRANCH,
26133 + Opcode_bltz_encode_fns, 0, 0 },
26134 + { "call0", 45 /* xt_iclass_call0 */,
26135 + XTENSA_OPCODE_IS_CALL,
26136 + Opcode_call0_encode_fns, 0, 0 },
26137 + { "callx0", 46 /* xt_iclass_callx0 */,
26138 + XTENSA_OPCODE_IS_CALL,
26139 + Opcode_callx0_encode_fns, 0, 0 },
26140 + { "extui", 47 /* xt_iclass_exti */,
26142 + Opcode_extui_encode_fns, 0, 0 },
26143 + { "ill", 48 /* xt_iclass_ill */,
26145 + Opcode_ill_encode_fns, 0, 0 },
26146 + { "j", 49 /* xt_iclass_jump */,
26147 + XTENSA_OPCODE_IS_JUMP,
26148 + Opcode_j_encode_fns, 0, 0 },
26149 + { "jx", 50 /* xt_iclass_jumpx */,
26150 + XTENSA_OPCODE_IS_JUMP,
26151 + Opcode_jx_encode_fns, 0, 0 },
26152 + { "l16ui", 51 /* xt_iclass_l16ui */,
26154 + Opcode_l16ui_encode_fns, 0, 0 },
26155 + { "l16si", 52 /* xt_iclass_l16si */,
26157 + Opcode_l16si_encode_fns, 0, 0 },
26158 + { "l32i", 53 /* xt_iclass_l32i */,
26160 + Opcode_l32i_encode_fns, 0, 0 },
26161 + { "l32r", 54 /* xt_iclass_l32r */,
26163 + Opcode_l32r_encode_fns, 0, 0 },
26164 + { "l8ui", 55 /* xt_iclass_l8i */,
26166 + Opcode_l8ui_encode_fns, 0, 0 },
26167 + { "loop", 56 /* xt_iclass_loop */,
26168 + XTENSA_OPCODE_IS_LOOP,
26169 + Opcode_loop_encode_fns, 0, 0 },
26170 + { "loopnez", 57 /* xt_iclass_loopz */,
26171 + XTENSA_OPCODE_IS_LOOP,
26172 + Opcode_loopnez_encode_fns, 0, 0 },
26173 + { "loopgtz", 57 /* xt_iclass_loopz */,
26174 + XTENSA_OPCODE_IS_LOOP,
26175 + Opcode_loopgtz_encode_fns, 0, 0 },
26176 + { "movi", 58 /* xt_iclass_movi */,
26178 + Opcode_movi_encode_fns, 0, 0 },
26179 + { "moveqz", 59 /* xt_iclass_movz */,
26181 + Opcode_moveqz_encode_fns, 0, 0 },
26182 + { "movnez", 59 /* xt_iclass_movz */,
26184 + Opcode_movnez_encode_fns, 0, 0 },
26185 + { "movltz", 59 /* xt_iclass_movz */,
26187 + Opcode_movltz_encode_fns, 0, 0 },
26188 + { "movgez", 59 /* xt_iclass_movz */,
26190 + Opcode_movgez_encode_fns, 0, 0 },
26191 + { "neg", 60 /* xt_iclass_neg */,
26193 + Opcode_neg_encode_fns, 0, 0 },
26194 + { "abs", 60 /* xt_iclass_neg */,
26196 + Opcode_abs_encode_fns, 0, 0 },
26197 + { "nop", 61 /* xt_iclass_nop */,
26199 + Opcode_nop_encode_fns, 0, 0 },
26200 + { "ret", 62 /* xt_iclass_return */,
26201 + XTENSA_OPCODE_IS_JUMP,
26202 + Opcode_ret_encode_fns, 0, 0 },
26203 + { "s16i", 63 /* xt_iclass_s16i */,
26205 + Opcode_s16i_encode_fns, 0, 0 },
26206 + { "s32i", 64 /* xt_iclass_s32i */,
26208 + Opcode_s32i_encode_fns, 0, 0 },
26209 + { "s8i", 65 /* xt_iclass_s8i */,
26211 + Opcode_s8i_encode_fns, 0, 0 },
26212 + { "ssr", 66 /* xt_iclass_sar */,
26214 + Opcode_ssr_encode_fns, 0, 0 },
26215 + { "ssl", 66 /* xt_iclass_sar */,
26217 + Opcode_ssl_encode_fns, 0, 0 },
26218 + { "ssa8l", 66 /* xt_iclass_sar */,
26220 + Opcode_ssa8l_encode_fns, 0, 0 },
26221 + { "ssa8b", 66 /* xt_iclass_sar */,
26223 + Opcode_ssa8b_encode_fns, 0, 0 },
26224 + { "ssai", 67 /* xt_iclass_sari */,
26226 + Opcode_ssai_encode_fns, 0, 0 },
26227 + { "sll", 68 /* xt_iclass_shifts */,
26229 + Opcode_sll_encode_fns, 0, 0 },
26230 + { "src", 69 /* xt_iclass_shiftst */,
26232 + Opcode_src_encode_fns, 0, 0 },
26233 + { "srl", 70 /* xt_iclass_shiftt */,
26235 + Opcode_srl_encode_fns, 0, 0 },
26236 + { "sra", 70 /* xt_iclass_shiftt */,
26238 + Opcode_sra_encode_fns, 0, 0 },
26239 + { "slli", 71 /* xt_iclass_slli */,
26241 + Opcode_slli_encode_fns, 0, 0 },
26242 + { "srai", 72 /* xt_iclass_srai */,
26244 + Opcode_srai_encode_fns, 0, 0 },
26245 + { "srli", 73 /* xt_iclass_srli */,
26247 + Opcode_srli_encode_fns, 0, 0 },
26248 + { "memw", 74 /* xt_iclass_memw */,
26250 + Opcode_memw_encode_fns, 0, 0 },
26251 + { "extw", 75 /* xt_iclass_extw */,
26253 + Opcode_extw_encode_fns, 0, 0 },
26254 + { "isync", 76 /* xt_iclass_isync */,
26256 + Opcode_isync_encode_fns, 0, 0 },
26257 + { "rsync", 77 /* xt_iclass_sync */,
26259 + Opcode_rsync_encode_fns, 0, 0 },
26260 + { "esync", 77 /* xt_iclass_sync */,
26262 + Opcode_esync_encode_fns, 0, 0 },
26263 + { "dsync", 77 /* xt_iclass_sync */,
26265 + Opcode_dsync_encode_fns, 0, 0 },
26266 + { "rsil", 78 /* xt_iclass_rsil */,
26268 + Opcode_rsil_encode_fns, 0, 0 },
26269 + { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
26271 + Opcode_rsr_lend_encode_fns, 0, 0 },
26272 + { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
26274 + Opcode_wsr_lend_encode_fns, 0, 0 },
26275 + { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
26277 + Opcode_xsr_lend_encode_fns, 0, 0 },
26278 + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
26280 + Opcode_rsr_lcount_encode_fns, 0, 0 },
26281 + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
26283 + Opcode_wsr_lcount_encode_fns, 0, 0 },
26284 + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
26286 + Opcode_xsr_lcount_encode_fns, 0, 0 },
26287 + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
26289 + Opcode_rsr_lbeg_encode_fns, 0, 0 },
26290 + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
26292 + Opcode_wsr_lbeg_encode_fns, 0, 0 },
26293 + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
26295 + Opcode_xsr_lbeg_encode_fns, 0, 0 },
26296 + { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
26298 + Opcode_rsr_sar_encode_fns, 0, 0 },
26299 + { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
26301 + Opcode_wsr_sar_encode_fns, 0, 0 },
26302 + { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
26304 + Opcode_xsr_sar_encode_fns, 0, 0 },
26305 + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
26307 + Opcode_rsr_litbase_encode_fns, 0, 0 },
26308 + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
26310 + Opcode_wsr_litbase_encode_fns, 0, 0 },
26311 + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
26313 + Opcode_xsr_litbase_encode_fns, 0, 0 },
26314 + { "rsr.176", 94 /* xt_iclass_rsr.176 */,
26316 + Opcode_rsr_176_encode_fns, 0, 0 },
26317 + { "rsr.208", 95 /* xt_iclass_rsr.208 */,
26319 + Opcode_rsr_208_encode_fns, 0, 0 },
26320 + { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
26322 + Opcode_rsr_ps_encode_fns, 0, 0 },
26323 + { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
26325 + Opcode_wsr_ps_encode_fns, 0, 0 },
26326 + { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
26328 + Opcode_xsr_ps_encode_fns, 0, 0 },
26329 + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
26331 + Opcode_rsr_epc1_encode_fns, 0, 0 },
26332 + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
26334 + Opcode_wsr_epc1_encode_fns, 0, 0 },
26335 + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
26337 + Opcode_xsr_epc1_encode_fns, 0, 0 },
26338 + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
26340 + Opcode_rsr_excsave1_encode_fns, 0, 0 },
26341 + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
26343 + Opcode_wsr_excsave1_encode_fns, 0, 0 },
26344 + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
26346 + Opcode_xsr_excsave1_encode_fns, 0, 0 },
26347 + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
26349 + Opcode_rsr_epc2_encode_fns, 0, 0 },
26350 + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
26352 + Opcode_wsr_epc2_encode_fns, 0, 0 },
26353 + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
26355 + Opcode_xsr_epc2_encode_fns, 0, 0 },
26356 + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
26358 + Opcode_rsr_excsave2_encode_fns, 0, 0 },
26359 + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
26361 + Opcode_wsr_excsave2_encode_fns, 0, 0 },
26362 + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
26364 + Opcode_xsr_excsave2_encode_fns, 0, 0 },
26365 + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
26367 + Opcode_rsr_epc3_encode_fns, 0, 0 },
26368 + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
26370 + Opcode_wsr_epc3_encode_fns, 0, 0 },
26371 + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
26373 + Opcode_xsr_epc3_encode_fns, 0, 0 },
26374 + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
26376 + Opcode_rsr_excsave3_encode_fns, 0, 0 },
26377 + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
26379 + Opcode_wsr_excsave3_encode_fns, 0, 0 },
26380 + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
26382 + Opcode_xsr_excsave3_encode_fns, 0, 0 },
26383 + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
26385 + Opcode_rsr_epc4_encode_fns, 0, 0 },
26386 + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
26388 + Opcode_wsr_epc4_encode_fns, 0, 0 },
26389 + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
26391 + Opcode_xsr_epc4_encode_fns, 0, 0 },
26392 + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
26394 + Opcode_rsr_excsave4_encode_fns, 0, 0 },
26395 + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
26397 + Opcode_wsr_excsave4_encode_fns, 0, 0 },
26398 + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
26400 + Opcode_xsr_excsave4_encode_fns, 0, 0 },
26401 + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
26403 + Opcode_rsr_epc5_encode_fns, 0, 0 },
26404 + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
26406 + Opcode_wsr_epc5_encode_fns, 0, 0 },
26407 + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
26409 + Opcode_xsr_epc5_encode_fns, 0, 0 },
26410 + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
26412 + Opcode_rsr_excsave5_encode_fns, 0, 0 },
26413 + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
26415 + Opcode_wsr_excsave5_encode_fns, 0, 0 },
26416 + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
26418 + Opcode_xsr_excsave5_encode_fns, 0, 0 },
26419 + { "rsr.eps2", 129 /* xt_iclass_rsr.eps2 */,
26421 + Opcode_rsr_eps2_encode_fns, 0, 0 },
26422 + { "wsr.eps2", 130 /* xt_iclass_wsr.eps2 */,
26424 + Opcode_wsr_eps2_encode_fns, 0, 0 },
26425 + { "xsr.eps2", 131 /* xt_iclass_xsr.eps2 */,
26427 + Opcode_xsr_eps2_encode_fns, 0, 0 },
26428 + { "rsr.eps3", 132 /* xt_iclass_rsr.eps3 */,
26430 + Opcode_rsr_eps3_encode_fns, 0, 0 },
26431 + { "wsr.eps3", 133 /* xt_iclass_wsr.eps3 */,
26433 + Opcode_wsr_eps3_encode_fns, 0, 0 },
26434 + { "xsr.eps3", 134 /* xt_iclass_xsr.eps3 */,
26436 + Opcode_xsr_eps3_encode_fns, 0, 0 },
26437 + { "rsr.eps4", 135 /* xt_iclass_rsr.eps4 */,
26439 + Opcode_rsr_eps4_encode_fns, 0, 0 },
26440 + { "wsr.eps4", 136 /* xt_iclass_wsr.eps4 */,
26442 + Opcode_wsr_eps4_encode_fns, 0, 0 },
26443 + { "xsr.eps4", 137 /* xt_iclass_xsr.eps4 */,
26445 + Opcode_xsr_eps4_encode_fns, 0, 0 },
26446 + { "rsr.eps5", 138 /* xt_iclass_rsr.eps5 */,
26448 + Opcode_rsr_eps5_encode_fns, 0, 0 },
26449 + { "wsr.eps5", 139 /* xt_iclass_wsr.eps5 */,
26451 + Opcode_wsr_eps5_encode_fns, 0, 0 },
26452 + { "xsr.eps5", 140 /* xt_iclass_xsr.eps5 */,
26454 + Opcode_xsr_eps5_encode_fns, 0, 0 },
26455 + { "rsr.excvaddr", 141 /* xt_iclass_rsr.excvaddr */,
26457 + Opcode_rsr_excvaddr_encode_fns, 0, 0 },
26458 + { "wsr.excvaddr", 142 /* xt_iclass_wsr.excvaddr */,
26460 + Opcode_wsr_excvaddr_encode_fns, 0, 0 },
26461 + { "xsr.excvaddr", 143 /* xt_iclass_xsr.excvaddr */,
26463 + Opcode_xsr_excvaddr_encode_fns, 0, 0 },
26464 + { "rsr.depc", 144 /* xt_iclass_rsr.depc */,
26466 + Opcode_rsr_depc_encode_fns, 0, 0 },
26467 + { "wsr.depc", 145 /* xt_iclass_wsr.depc */,
26469 + Opcode_wsr_depc_encode_fns, 0, 0 },
26470 + { "xsr.depc", 146 /* xt_iclass_xsr.depc */,
26472 + Opcode_xsr_depc_encode_fns, 0, 0 },
26473 + { "rsr.exccause", 147 /* xt_iclass_rsr.exccause */,
26475 + Opcode_rsr_exccause_encode_fns, 0, 0 },
26476 + { "wsr.exccause", 148 /* xt_iclass_wsr.exccause */,
26478 + Opcode_wsr_exccause_encode_fns, 0, 0 },
26479 + { "xsr.exccause", 149 /* xt_iclass_xsr.exccause */,
26481 + Opcode_xsr_exccause_encode_fns, 0, 0 },
26482 + { "rsr.misc0", 150 /* xt_iclass_rsr.misc0 */,
26484 + Opcode_rsr_misc0_encode_fns, 0, 0 },
26485 + { "wsr.misc0", 151 /* xt_iclass_wsr.misc0 */,
26487 + Opcode_wsr_misc0_encode_fns, 0, 0 },
26488 + { "xsr.misc0", 152 /* xt_iclass_xsr.misc0 */,
26490 + Opcode_xsr_misc0_encode_fns, 0, 0 },
26491 + { "rsr.misc1", 153 /* xt_iclass_rsr.misc1 */,
26493 + Opcode_rsr_misc1_encode_fns, 0, 0 },
26494 + { "wsr.misc1", 154 /* xt_iclass_wsr.misc1 */,
26496 + Opcode_wsr_misc1_encode_fns, 0, 0 },
26497 + { "xsr.misc1", 155 /* xt_iclass_xsr.misc1 */,
26499 + Opcode_xsr_misc1_encode_fns, 0, 0 },
26500 + { "rsr.prid", 156 /* xt_iclass_rsr.prid */,
26502 + Opcode_rsr_prid_encode_fns, 0, 0 },
26503 + { "rsr.vecbase", 157 /* xt_iclass_rsr.vecbase */,
26505 + Opcode_rsr_vecbase_encode_fns, 0, 0 },
26506 + { "wsr.vecbase", 158 /* xt_iclass_wsr.vecbase */,
26508 + Opcode_wsr_vecbase_encode_fns, 0, 0 },
26509 + { "xsr.vecbase", 159 /* xt_iclass_xsr.vecbase */,
26511 + Opcode_xsr_vecbase_encode_fns, 0, 0 },
26512 + { "rfi", 160 /* xt_iclass_rfi */,
26513 + XTENSA_OPCODE_IS_JUMP,
26514 + Opcode_rfi_encode_fns, 0, 0 },
26515 + { "waiti", 161 /* xt_iclass_wait */,
26517 + Opcode_waiti_encode_fns, 0, 0 },
26518 + { "rsr.interrupt", 162 /* xt_iclass_rsr.interrupt */,
26520 + Opcode_rsr_interrupt_encode_fns, 0, 0 },
26521 + { "wsr.intset", 163 /* xt_iclass_wsr.intset */,
26523 + Opcode_wsr_intset_encode_fns, 0, 0 },
26524 + { "wsr.intclear", 164 /* xt_iclass_wsr.intclear */,
26526 + Opcode_wsr_intclear_encode_fns, 0, 0 },
26527 + { "rsr.intenable", 165 /* xt_iclass_rsr.intenable */,
26529 + Opcode_rsr_intenable_encode_fns, 0, 0 },
26530 + { "wsr.intenable", 166 /* xt_iclass_wsr.intenable */,
26532 + Opcode_wsr_intenable_encode_fns, 0, 0 },
26533 + { "xsr.intenable", 167 /* xt_iclass_xsr.intenable */,
26535 + Opcode_xsr_intenable_encode_fns, 0, 0 },
26536 + { "break", 168 /* xt_iclass_break */,
26538 + Opcode_break_encode_fns, 0, 0 },
26539 + { "break.n", 169 /* xt_iclass_break.n */,
26541 + Opcode_break_n_encode_fns, 0, 0 },
26542 + { "rsr.dbreaka0", 170 /* xt_iclass_rsr.dbreaka0 */,
26544 + Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
26545 + { "wsr.dbreaka0", 171 /* xt_iclass_wsr.dbreaka0 */,
26547 + Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
26548 + { "xsr.dbreaka0", 172 /* xt_iclass_xsr.dbreaka0 */,
26550 + Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
26551 + { "rsr.dbreakc0", 173 /* xt_iclass_rsr.dbreakc0 */,
26553 + Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
26554 + { "wsr.dbreakc0", 174 /* xt_iclass_wsr.dbreakc0 */,
26556 + Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
26557 + { "xsr.dbreakc0", 175 /* xt_iclass_xsr.dbreakc0 */,
26559 + Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
26560 + { "rsr.dbreaka1", 176 /* xt_iclass_rsr.dbreaka1 */,
26562 + Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
26563 + { "wsr.dbreaka1", 177 /* xt_iclass_wsr.dbreaka1 */,
26565 + Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
26566 + { "xsr.dbreaka1", 178 /* xt_iclass_xsr.dbreaka1 */,
26568 + Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
26569 + { "rsr.dbreakc1", 179 /* xt_iclass_rsr.dbreakc1 */,
26571 + Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
26572 + { "wsr.dbreakc1", 180 /* xt_iclass_wsr.dbreakc1 */,
26574 + Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
26575 + { "xsr.dbreakc1", 181 /* xt_iclass_xsr.dbreakc1 */,
26577 + Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
26578 + { "rsr.ibreaka0", 182 /* xt_iclass_rsr.ibreaka0 */,
26580 + Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
26581 + { "wsr.ibreaka0", 183 /* xt_iclass_wsr.ibreaka0 */,
26583 + Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
26584 + { "xsr.ibreaka0", 184 /* xt_iclass_xsr.ibreaka0 */,
26586 + Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
26587 + { "rsr.ibreaka1", 185 /* xt_iclass_rsr.ibreaka1 */,
26589 + Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
26590 + { "wsr.ibreaka1", 186 /* xt_iclass_wsr.ibreaka1 */,
26592 + Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
26593 + { "xsr.ibreaka1", 187 /* xt_iclass_xsr.ibreaka1 */,
26595 + Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
26596 + { "rsr.ibreakenable", 188 /* xt_iclass_rsr.ibreakenable */,
26598 + Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
26599 + { "wsr.ibreakenable", 189 /* xt_iclass_wsr.ibreakenable */,
26601 + Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
26602 + { "xsr.ibreakenable", 190 /* xt_iclass_xsr.ibreakenable */,
26604 + Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
26605 + { "rsr.debugcause", 191 /* xt_iclass_rsr.debugcause */,
26607 + Opcode_rsr_debugcause_encode_fns, 0, 0 },
26608 + { "wsr.debugcause", 192 /* xt_iclass_wsr.debugcause */,
26610 + Opcode_wsr_debugcause_encode_fns, 0, 0 },
26611 + { "xsr.debugcause", 193 /* xt_iclass_xsr.debugcause */,
26613 + Opcode_xsr_debugcause_encode_fns, 0, 0 },
26614 + { "rsr.icount", 194 /* xt_iclass_rsr.icount */,
26616 + Opcode_rsr_icount_encode_fns, 0, 0 },
26617 + { "wsr.icount", 195 /* xt_iclass_wsr.icount */,
26619 + Opcode_wsr_icount_encode_fns, 0, 0 },
26620 + { "xsr.icount", 196 /* xt_iclass_xsr.icount */,
26622 + Opcode_xsr_icount_encode_fns, 0, 0 },
26623 + { "rsr.icountlevel", 197 /* xt_iclass_rsr.icountlevel */,
26625 + Opcode_rsr_icountlevel_encode_fns, 0, 0 },
26626 + { "wsr.icountlevel", 198 /* xt_iclass_wsr.icountlevel */,
26628 + Opcode_wsr_icountlevel_encode_fns, 0, 0 },
26629 + { "xsr.icountlevel", 199 /* xt_iclass_xsr.icountlevel */,
26631 + Opcode_xsr_icountlevel_encode_fns, 0, 0 },
26632 + { "rsr.ddr", 200 /* xt_iclass_rsr.ddr */,
26634 + Opcode_rsr_ddr_encode_fns, 0, 0 },
26635 + { "wsr.ddr", 201 /* xt_iclass_wsr.ddr */,
26637 + Opcode_wsr_ddr_encode_fns, 0, 0 },
26638 + { "xsr.ddr", 202 /* xt_iclass_xsr.ddr */,
26640 + Opcode_xsr_ddr_encode_fns, 0, 0 },
26641 + { "rfdo", 203 /* xt_iclass_rfdo */,
26642 + XTENSA_OPCODE_IS_JUMP,
26643 + Opcode_rfdo_encode_fns, 0, 0 },
26644 + { "rfdd", 204 /* xt_iclass_rfdd */,
26645 + XTENSA_OPCODE_IS_JUMP,
26646 + Opcode_rfdd_encode_fns, 0, 0 },
26647 + { "wsr.mmid", 205 /* xt_iclass_wsr.mmid */,
26649 + Opcode_wsr_mmid_encode_fns, 0, 0 },
26650 + { "rsr.ccount", 206 /* xt_iclass_rsr.ccount */,
26652 + Opcode_rsr_ccount_encode_fns, 0, 0 },
26653 + { "wsr.ccount", 207 /* xt_iclass_wsr.ccount */,
26655 + Opcode_wsr_ccount_encode_fns, 0, 0 },
26656 + { "xsr.ccount", 208 /* xt_iclass_xsr.ccount */,
26658 + Opcode_xsr_ccount_encode_fns, 0, 0 },
26659 + { "rsr.ccompare0", 209 /* xt_iclass_rsr.ccompare0 */,
26661 + Opcode_rsr_ccompare0_encode_fns, 0, 0 },
26662 + { "wsr.ccompare0", 210 /* xt_iclass_wsr.ccompare0 */,
26664 + Opcode_wsr_ccompare0_encode_fns, 0, 0 },
26665 + { "xsr.ccompare0", 211 /* xt_iclass_xsr.ccompare0 */,
26667 + Opcode_xsr_ccompare0_encode_fns, 0, 0 },
26668 + { "idtlb", 212 /* xt_iclass_idtlb */,
26670 + Opcode_idtlb_encode_fns, 0, 0 },
26671 + { "pdtlb", 213 /* xt_iclass_rdtlb */,
26673 + Opcode_pdtlb_encode_fns, 0, 0 },
26674 + { "rdtlb0", 213 /* xt_iclass_rdtlb */,
26676 + Opcode_rdtlb0_encode_fns, 0, 0 },
26677 + { "rdtlb1", 213 /* xt_iclass_rdtlb */,
26679 + Opcode_rdtlb1_encode_fns, 0, 0 },
26680 + { "wdtlb", 214 /* xt_iclass_wdtlb */,
26682 + Opcode_wdtlb_encode_fns, 0, 0 },
26683 + { "iitlb", 215 /* xt_iclass_iitlb */,
26685 + Opcode_iitlb_encode_fns, 0, 0 },
26686 + { "pitlb", 216 /* xt_iclass_ritlb */,
26688 + Opcode_pitlb_encode_fns, 0, 0 },
26689 + { "ritlb0", 216 /* xt_iclass_ritlb */,
26691 + Opcode_ritlb0_encode_fns, 0, 0 },
26692 + { "ritlb1", 216 /* xt_iclass_ritlb */,
26694 + Opcode_ritlb1_encode_fns, 0, 0 },
26695 + { "witlb", 217 /* xt_iclass_witlb */,
26697 + Opcode_witlb_encode_fns, 0, 0 },
26698 + { "min", 218 /* xt_iclass_minmax */,
26700 + Opcode_min_encode_fns, 0, 0 },
26701 + { "max", 218 /* xt_iclass_minmax */,
26703 + Opcode_max_encode_fns, 0, 0 },
26704 + { "minu", 218 /* xt_iclass_minmax */,
26706 + Opcode_minu_encode_fns, 0, 0 },
26707 + { "maxu", 218 /* xt_iclass_minmax */,
26709 + Opcode_maxu_encode_fns, 0, 0 },
26710 + { "nsa", 219 /* xt_iclass_nsa */,
26712 + Opcode_nsa_encode_fns, 0, 0 },
26713 + { "nsau", 219 /* xt_iclass_nsa */,
26715 + Opcode_nsau_encode_fns, 0, 0 },
26716 + { "sext", 220 /* xt_iclass_sx */,
26718 + Opcode_sext_encode_fns, 0, 0 },
26719 + { "l32ai", 221 /* xt_iclass_l32ai */,
26721 + Opcode_l32ai_encode_fns, 0, 0 },
26722 + { "s32ri", 222 /* xt_iclass_s32ri */,
26724 + Opcode_s32ri_encode_fns, 0, 0 },
26725 + { "s32c1i", 223 /* xt_iclass_s32c1i */,
26727 + Opcode_s32c1i_encode_fns, 0, 0 },
26728 + { "rsr.scompare1", 224 /* xt_iclass_rsr.scompare1 */,
26730 + Opcode_rsr_scompare1_encode_fns, 0, 0 },
26731 + { "wsr.scompare1", 225 /* xt_iclass_wsr.scompare1 */,
26733 + Opcode_wsr_scompare1_encode_fns, 0, 0 },
26734 + { "xsr.scompare1", 226 /* xt_iclass_xsr.scompare1 */,
26736 + Opcode_xsr_scompare1_encode_fns, 0, 0 },
26737 + { "mull", 227 /* xt_mul32 */,
26739 + Opcode_mull_encode_fns, 0, 0 },
26740 + { "muluh", 227 /* xt_mul32 */,
26742 + Opcode_muluh_encode_fns, 0, 0 },
26743 + { "mulsh", 227 /* xt_mul32 */,
26745 + Opcode_mulsh_encode_fns, 0, 0 },
26746 + { "mul16u", 227 /* xt_mul32 */,
26748 + Opcode_mul16u_encode_fns, 0, 0 },
26749 + { "mul16s", 227 /* xt_mul32 */,
26751 + Opcode_mul16s_encode_fns, 0, 0 }
26754 -static xtensa_set_field_fn
26755 -Slot_xt_flix64_slot0_set_field_fns[] = {
26756 - Field_t_Slot_xt_flix64_slot0_set,
26760 - Field_imm8_Slot_xt_flix64_slot0_set,
26761 - Field_s_Slot_xt_flix64_slot0_set,
26762 - Field_imm12b_Slot_xt_flix64_slot0_set,
26763 - Field_imm16_Slot_xt_flix64_slot0_set,
26764 - Field_m_Slot_xt_flix64_slot0_set,
26765 - Field_n_Slot_xt_flix64_slot0_set,
26768 - Field_op1_Slot_xt_flix64_slot0_set,
26769 - Field_op2_Slot_xt_flix64_slot0_set,
26770 - Field_r_Slot_xt_flix64_slot0_set,
26772 - Field_sae4_Slot_xt_flix64_slot0_set,
26773 - Field_sae_Slot_xt_flix64_slot0_set,
26774 - Field_sal_Slot_xt_flix64_slot0_set,
26775 - Field_sargt_Slot_xt_flix64_slot0_set,
26777 - Field_sas_Slot_xt_flix64_slot0_set,
26780 - Field_thi3_Slot_xt_flix64_slot0_set,
26811 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
26812 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
26813 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
26814 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
26815 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
26816 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26878 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26879 - Implicit_Field_set,
26880 - Implicit_Field_set,
26881 - Implicit_Field_set,
26882 - Implicit_Field_set,
26883 - Implicit_Field_set,
26884 - Implicit_Field_set,
26885 - Implicit_Field_set,
26886 - Implicit_Field_set,
26887 - Implicit_Field_set,
26888 - Implicit_Field_set,
26889 - Implicit_Field_set,
26890 - Implicit_Field_set
26893 +/* Slot-specific opcode decode functions. */
26895 -static xtensa_get_field_fn
26896 -Slot_xt_flix64_slot1_get_field_fns[] = {
26897 - Field_t_Slot_xt_flix64_slot1_get,
26901 - Field_imm8_Slot_xt_flix64_slot1_get,
26902 - Field_s_Slot_xt_flix64_slot1_get,
26903 - Field_imm12b_Slot_xt_flix64_slot1_get,
26907 - Field_offset_Slot_xt_flix64_slot1_get,
26910 - Field_op2_Slot_xt_flix64_slot1_get,
26911 - Field_r_Slot_xt_flix64_slot1_get,
26914 - Field_sae_Slot_xt_flix64_slot1_get,
26915 - Field_sal_Slot_xt_flix64_slot1_get,
26916 - Field_sargt_Slot_xt_flix64_slot1_get,
26958 - Field_op0_s4_Slot_xt_flix64_slot1_get,
26959 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
26960 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26961 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26962 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26963 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26964 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26965 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26966 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26967 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26968 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26969 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26970 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26971 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26972 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26973 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26974 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26975 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26976 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26977 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26978 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26979 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
27020 - Implicit_Field_ar0_get,
27021 - Implicit_Field_ar4_get,
27022 - Implicit_Field_ar8_get,
27023 - Implicit_Field_ar12_get,
27024 - Implicit_Field_mr0_get,
27025 - Implicit_Field_mr1_get,
27026 - Implicit_Field_mr2_get,
27027 - Implicit_Field_mr3_get,
27028 - Implicit_Field_bt16_get,
27029 - Implicit_Field_bs16_get,
27030 - Implicit_Field_br16_get,
27031 - Implicit_Field_brall_get
27034 +Slot_inst_decode (const xtensa_insnbuf insn)
27036 + switch (Field_op0_Slot_inst_get (insn))
27039 + switch (Field_op1_Slot_inst_get (insn))
27042 + switch (Field_op2_Slot_inst_get (insn))
27045 + switch (Field_r_Slot_inst_get (insn))
27048 + switch (Field_m_Slot_inst_get (insn))
27051 + if (Field_s_Slot_inst_get (insn) == 0 &&
27052 + Field_n_Slot_inst_get (insn) == 0)
27053 + return 79; /* ill */
27056 + switch (Field_n_Slot_inst_get (insn))
27059 + return 98; /* ret */
27061 + return 14; /* retw */
27063 + return 81; /* jx */
27067 + switch (Field_n_Slot_inst_get (insn))
27070 + return 77; /* callx0 */
27072 + return 10; /* callx4 */
27074 + return 9; /* callx8 */
27076 + return 8; /* callx12 */
27082 + return 12; /* movsp */
27084 + if (Field_s_Slot_inst_get (insn) == 0)
27086 + switch (Field_t_Slot_inst_get (insn))
27089 + return 116; /* isync */
27091 + return 117; /* rsync */
27093 + return 118; /* esync */
27095 + return 119; /* dsync */
27097 + return 0; /* excw */
27099 + return 114; /* memw */
27101 + return 115; /* extw */
27103 + return 97; /* nop */
27108 + switch (Field_t_Slot_inst_get (insn))
27111 + switch (Field_s_Slot_inst_get (insn))
27114 + return 1; /* rfe */
27116 + return 2; /* rfde */
27118 + return 16; /* rfwo */
27120 + return 17; /* rfwu */
27124 + return 202; /* rfi */
27128 + return 210; /* break */
27130 + switch (Field_s_Slot_inst_get (insn))
27133 + if (Field_t_Slot_inst_get (insn) == 0)
27134 + return 3; /* syscall */
27137 + if (Field_t_Slot_inst_get (insn) == 0)
27138 + return 4; /* simcall */
27143 + return 120; /* rsil */
27145 + if (Field_t_Slot_inst_get (insn) == 0)
27146 + return 203; /* waiti */
27151 + return 49; /* and */
27153 + return 50; /* or */
27155 + return 51; /* xor */
27157 + switch (Field_r_Slot_inst_get (insn))
27160 + if (Field_t_Slot_inst_get (insn) == 0)
27161 + return 102; /* ssr */
27164 + if (Field_t_Slot_inst_get (insn) == 0)
27165 + return 103; /* ssl */
27168 + if (Field_t_Slot_inst_get (insn) == 0)
27169 + return 104; /* ssa8l */
27172 + if (Field_t_Slot_inst_get (insn) == 0)
27173 + return 105; /* ssa8b */
27176 + if (Field_thi3_Slot_inst_get (insn) == 0)
27177 + return 106; /* ssai */
27180 + if (Field_s_Slot_inst_get (insn) == 0)
27181 + return 13; /* rotw */
27184 + return 268; /* nsa */
27186 + return 269; /* nsau */
27190 + switch (Field_r_Slot_inst_get (insn))
27193 + return 261; /* ritlb0 */
27195 + if (Field_t_Slot_inst_get (insn) == 0)
27196 + return 259; /* iitlb */
27199 + return 260; /* pitlb */
27201 + return 263; /* witlb */
27203 + return 262; /* ritlb1 */
27205 + return 256; /* rdtlb0 */
27207 + if (Field_t_Slot_inst_get (insn) == 0)
27208 + return 254; /* idtlb */
27211 + return 255; /* pdtlb */
27213 + return 258; /* wdtlb */
27215 + return 257; /* rdtlb1 */
27219 + switch (Field_s_Slot_inst_get (insn))
27222 + return 95; /* neg */
27224 + return 96; /* abs */
27228 + return 41; /* add */
27230 + return 43; /* addx2 */
27232 + return 44; /* addx4 */
27234 + return 45; /* addx8 */
27236 + return 42; /* sub */
27238 + return 46; /* subx2 */
27240 + return 47; /* subx4 */
27242 + return 48; /* subx8 */
27246 + switch (Field_op2_Slot_inst_get (insn))
27250 + return 111; /* slli */
27253 + return 112; /* srai */
27255 + return 113; /* srli */
27257 + switch (Field_sr_Slot_inst_get (insn))
27260 + return 129; /* xsr.lbeg */
27262 + return 123; /* xsr.lend */
27264 + return 126; /* xsr.lcount */
27266 + return 132; /* xsr.sar */
27268 + return 135; /* xsr.litbase */
27270 + return 276; /* xsr.scompare1 */
27272 + return 22; /* xsr.windowbase */
27274 + return 25; /* xsr.windowstart */
27276 + return 232; /* xsr.ibreakenable */
27278 + return 244; /* xsr.ddr */
27280 + return 226; /* xsr.ibreaka0 */
27282 + return 229; /* xsr.ibreaka1 */
27284 + return 214; /* xsr.dbreaka0 */
27286 + return 220; /* xsr.dbreaka1 */
27288 + return 217; /* xsr.dbreakc0 */
27290 + return 223; /* xsr.dbreakc1 */
27292 + return 143; /* xsr.epc1 */
27294 + return 149; /* xsr.epc2 */
27296 + return 155; /* xsr.epc3 */
27298 + return 161; /* xsr.epc4 */
27300 + return 167; /* xsr.epc5 */
27302 + return 188; /* xsr.depc */
27304 + return 173; /* xsr.eps2 */
27306 + return 176; /* xsr.eps3 */
27308 + return 179; /* xsr.eps4 */
27310 + return 182; /* xsr.eps5 */
27312 + return 146; /* xsr.excsave1 */
27314 + return 152; /* xsr.excsave2 */
27316 + return 158; /* xsr.excsave3 */
27318 + return 164; /* xsr.excsave4 */
27320 + return 170; /* xsr.excsave5 */
27322 + return 209; /* xsr.intenable */
27324 + return 140; /* xsr.ps */
27326 + return 201; /* xsr.vecbase */
27328 + return 191; /* xsr.exccause */
27330 + return 235; /* xsr.debugcause */
27332 + return 250; /* xsr.ccount */
27334 + return 238; /* xsr.icount */
27336 + return 241; /* xsr.icountlevel */
27338 + return 185; /* xsr.excvaddr */
27340 + return 253; /* xsr.ccompare0 */
27342 + return 194; /* xsr.misc0 */
27344 + return 197; /* xsr.misc1 */
27348 + return 108; /* src */
27350 + if (Field_s_Slot_inst_get (insn) == 0)
27351 + return 109; /* srl */
27354 + if (Field_t_Slot_inst_get (insn) == 0)
27355 + return 107; /* sll */
27358 + if (Field_s_Slot_inst_get (insn) == 0)
27359 + return 110; /* sra */
27362 + return 280; /* mul16u */
27364 + return 281; /* mul16s */
27366 + switch (Field_r_Slot_inst_get (insn))
27369 + if (Field_t_Slot_inst_get (insn) == 0)
27370 + return 245; /* rfdo */
27371 + if (Field_t_Slot_inst_get (insn) == 1)
27372 + return 246; /* rfdd */
27379 + switch (Field_op2_Slot_inst_get (insn))
27382 + return 277; /* mull */
27384 + return 278; /* muluh */
27386 + return 279; /* mulsh */
27390 + switch (Field_op2_Slot_inst_get (insn))
27393 + switch (Field_sr_Slot_inst_get (insn))
27396 + return 127; /* rsr.lbeg */
27398 + return 121; /* rsr.lend */
27400 + return 124; /* rsr.lcount */
27402 + return 130; /* rsr.sar */
27404 + return 133; /* rsr.litbase */
27406 + return 274; /* rsr.scompare1 */
27408 + return 20; /* rsr.windowbase */
27410 + return 23; /* rsr.windowstart */
27412 + return 230; /* rsr.ibreakenable */
27414 + return 242; /* rsr.ddr */
27416 + return 224; /* rsr.ibreaka0 */
27418 + return 227; /* rsr.ibreaka1 */
27420 + return 212; /* rsr.dbreaka0 */
27422 + return 218; /* rsr.dbreaka1 */
27424 + return 215; /* rsr.dbreakc0 */
27426 + return 221; /* rsr.dbreakc1 */
27428 + return 136; /* rsr.176 */
27430 + return 141; /* rsr.epc1 */
27432 + return 147; /* rsr.epc2 */
27434 + return 153; /* rsr.epc3 */
27436 + return 159; /* rsr.epc4 */
27438 + return 165; /* rsr.epc5 */
27440 + return 186; /* rsr.depc */
27442 + return 171; /* rsr.eps2 */
27444 + return 174; /* rsr.eps3 */
27446 + return 177; /* rsr.eps4 */
27448 + return 180; /* rsr.eps5 */
27450 + return 137; /* rsr.208 */
27452 + return 144; /* rsr.excsave1 */
27454 + return 150; /* rsr.excsave2 */
27456 + return 156; /* rsr.excsave3 */
27458 + return 162; /* rsr.excsave4 */
27460 + return 168; /* rsr.excsave5 */
27462 + return 204; /* rsr.interrupt */
27464 + return 207; /* rsr.intenable */
27466 + return 138; /* rsr.ps */
27468 + return 199; /* rsr.vecbase */
27470 + return 189; /* rsr.exccause */
27472 + return 233; /* rsr.debugcause */
27474 + return 248; /* rsr.ccount */
27476 + return 198; /* rsr.prid */
27478 + return 236; /* rsr.icount */
27480 + return 239; /* rsr.icountlevel */
27482 + return 183; /* rsr.excvaddr */
27484 + return 251; /* rsr.ccompare0 */
27486 + return 192; /* rsr.misc0 */
27488 + return 195; /* rsr.misc1 */
27492 + switch (Field_sr_Slot_inst_get (insn))
27495 + return 128; /* wsr.lbeg */
27497 + return 122; /* wsr.lend */
27499 + return 125; /* wsr.lcount */
27501 + return 131; /* wsr.sar */
27503 + return 134; /* wsr.litbase */
27505 + return 275; /* wsr.scompare1 */
27507 + return 21; /* wsr.windowbase */
27509 + return 24; /* wsr.windowstart */
27511 + return 247; /* wsr.mmid */
27513 + return 231; /* wsr.ibreakenable */
27515 + return 243; /* wsr.ddr */
27517 + return 225; /* wsr.ibreaka0 */
27519 + return 228; /* wsr.ibreaka1 */
27521 + return 213; /* wsr.dbreaka0 */
27523 + return 219; /* wsr.dbreaka1 */
27525 + return 216; /* wsr.dbreakc0 */
27527 + return 222; /* wsr.dbreakc1 */
27529 + return 142; /* wsr.epc1 */
27531 + return 148; /* wsr.epc2 */
27533 + return 154; /* wsr.epc3 */
27535 + return 160; /* wsr.epc4 */
27537 + return 166; /* wsr.epc5 */
27539 + return 187; /* wsr.depc */
27541 + return 172; /* wsr.eps2 */
27543 + return 175; /* wsr.eps3 */
27545 + return 178; /* wsr.eps4 */
27547 + return 181; /* wsr.eps5 */
27549 + return 145; /* wsr.excsave1 */
27551 + return 151; /* wsr.excsave2 */
27553 + return 157; /* wsr.excsave3 */
27555 + return 163; /* wsr.excsave4 */
27557 + return 169; /* wsr.excsave5 */
27559 + return 205; /* wsr.intset */
27561 + return 206; /* wsr.intclear */
27563 + return 208; /* wsr.intenable */
27565 + return 139; /* wsr.ps */
27567 + return 200; /* wsr.vecbase */
27569 + return 190; /* wsr.exccause */
27571 + return 234; /* wsr.debugcause */
27573 + return 249; /* wsr.ccount */
27575 + return 237; /* wsr.icount */
27577 + return 240; /* wsr.icountlevel */
27579 + return 184; /* wsr.excvaddr */
27581 + return 252; /* wsr.ccompare0 */
27583 + return 193; /* wsr.misc0 */
27585 + return 196; /* wsr.misc1 */
27589 + return 270; /* sext */
27591 + return 264; /* min */
27593 + return 265; /* max */
27595 + return 266; /* minu */
27597 + return 267; /* maxu */
27599 + return 91; /* moveqz */
27601 + return 92; /* movnez */
27603 + return 93; /* movltz */
27605 + return 94; /* movgez */
27607 + if (Field_st_Slot_inst_get (insn) == 231)
27608 + return 37; /* rur.threadptr */
27611 + if (Field_sr_Slot_inst_get (insn) == 231)
27612 + return 38; /* wur.threadptr */
27618 + return 78; /* extui */
27620 + switch (Field_op2_Slot_inst_get (insn))
27623 + return 18; /* l32e */
27625 + return 19; /* s32e */
27631 + return 85; /* l32r */
27633 + switch (Field_r_Slot_inst_get (insn))
27636 + return 86; /* l8ui */
27638 + return 82; /* l16ui */
27640 + return 84; /* l32i */
27642 + return 101; /* s8i */
27644 + return 99; /* s16i */
27646 + return 100; /* s32i */
27648 + return 83; /* l16si */
27650 + return 90; /* movi */
27652 + return 271; /* l32ai */
27654 + return 39; /* addi */
27656 + return 40; /* addmi */
27658 + return 273; /* s32c1i */
27660 + return 272; /* s32ri */
27664 + switch (Field_n_Slot_inst_get (insn))
27667 + return 76; /* call0 */
27669 + return 7; /* call4 */
27671 + return 6; /* call8 */
27673 + return 5; /* call12 */
27677 + switch (Field_n_Slot_inst_get (insn))
27680 + return 80; /* j */
27682 + switch (Field_m_Slot_inst_get (insn))
27685 + return 72; /* beqz */
27687 + return 73; /* bnez */
27689 + return 75; /* bltz */
27691 + return 74; /* bgez */
27695 + switch (Field_m_Slot_inst_get (insn))
27698 + return 52; /* beqi */
27700 + return 53; /* bnei */
27702 + return 55; /* blti */
27704 + return 54; /* bgei */
27708 + switch (Field_m_Slot_inst_get (insn))
27711 + return 11; /* entry */
27713 + switch (Field_r_Slot_inst_get (insn))
27716 + return 87; /* loop */
27718 + return 88; /* loopnez */
27720 + return 89; /* loopgtz */
27724 + return 59; /* bltui */
27726 + return 58; /* bgeui */
27732 + switch (Field_r_Slot_inst_get (insn))
27735 + return 67; /* bnone */
27737 + return 60; /* beq */
27739 + return 63; /* blt */
27741 + return 65; /* bltu */
27743 + return 68; /* ball */
27745 + return 70; /* bbc */
27748 + return 56; /* bbci */
27750 + return 66; /* bany */
27752 + return 61; /* bne */
27754 + return 62; /* bge */
27756 + return 64; /* bgeu */
27758 + return 69; /* bnall */
27760 + return 71; /* bbs */
27763 + return 57; /* bbsi */
27770 -static xtensa_set_field_fn
27771 -Slot_xt_flix64_slot1_set_field_fns[] = {
27772 - Field_t_Slot_xt_flix64_slot1_set,
27776 - Field_imm8_Slot_xt_flix64_slot1_set,
27777 - Field_s_Slot_xt_flix64_slot1_set,
27778 - Field_imm12b_Slot_xt_flix64_slot1_set,
27782 - Field_offset_Slot_xt_flix64_slot1_set,
27785 - Field_op2_Slot_xt_flix64_slot1_set,
27786 - Field_r_Slot_xt_flix64_slot1_set,
27789 - Field_sae_Slot_xt_flix64_slot1_set,
27790 - Field_sal_Slot_xt_flix64_slot1_set,
27791 - Field_sargt_Slot_xt_flix64_slot1_set,
27833 - Field_op0_s4_Slot_xt_flix64_slot1_set,
27834 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
27835 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27836 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27837 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27838 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27839 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27840 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27841 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27842 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27843 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27844 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27845 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27846 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27847 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27848 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27849 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27850 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27851 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27852 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27853 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27854 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27895 - Implicit_Field_set,
27896 - Implicit_Field_set,
27897 - Implicit_Field_set,
27898 - Implicit_Field_set,
27899 - Implicit_Field_set,
27900 - Implicit_Field_set,
27901 - Implicit_Field_set,
27902 - Implicit_Field_set,
27903 - Implicit_Field_set,
27904 - Implicit_Field_set,
27905 - Implicit_Field_set,
27906 - Implicit_Field_set
27909 +Slot_inst16b_decode (const xtensa_insnbuf insn)
27911 + switch (Field_op0_Slot_inst16b_get (insn))
27914 + switch (Field_i_Slot_inst16b_get (insn))
27917 + return 33; /* movi.n */
27919 + switch (Field_z_Slot_inst16b_get (insn))
27922 + return 28; /* beqz.n */
27924 + return 29; /* bnez.n */
27930 + switch (Field_r_Slot_inst16b_get (insn))
27933 + return 32; /* mov.n */
27935 + switch (Field_t_Slot_inst16b_get (insn))
27938 + return 35; /* ret.n */
27940 + return 15; /* retw.n */
27942 + return 211; /* break.n */
27944 + if (Field_s_Slot_inst16b_get (insn) == 0)
27945 + return 34; /* nop.n */
27948 + if (Field_s_Slot_inst16b_get (insn) == 0)
27949 + return 30; /* ill.n */
27960 +Slot_inst16a_decode (const xtensa_insnbuf insn)
27962 + switch (Field_op0_Slot_inst16a_get (insn))
27965 + return 31; /* l32i.n */
27967 + return 36; /* s32i.n */
27969 + return 26; /* add.n */
27971 + return 27; /* addi.n */
27976 -static xtensa_get_field_fn
27977 -Slot_xt_flix64_slot2_get_field_fns[] = {
27978 - Field_t_Slot_xt_flix64_slot2_get,
27983 - Field_s_Slot_xt_flix64_slot2_get,
27992 - Field_r_Slot_xt_flix64_slot2_get,
27997 - Field_sargt_Slot_xt_flix64_slot2_get,
28012 - Field_imm7_Slot_xt_flix64_slot2_get,
28061 - Field_op0_s5_Slot_xt_flix64_slot2_get,
28062 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28063 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28064 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28065 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28066 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28067 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28068 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28069 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28070 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28071 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28072 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28073 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28074 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28101 - Implicit_Field_ar0_get,
28102 - Implicit_Field_ar4_get,
28103 - Implicit_Field_ar8_get,
28104 - Implicit_Field_ar12_get,
28105 - Implicit_Field_mr0_get,
28106 - Implicit_Field_mr1_get,
28107 - Implicit_Field_mr2_get,
28108 - Implicit_Field_mr3_get,
28109 - Implicit_Field_bt16_get,
28110 - Implicit_Field_bs16_get,
28111 - Implicit_Field_br16_get,
28112 - Implicit_Field_brall_get
28115 +/* Instruction slots. */
28117 -static xtensa_set_field_fn
28118 -Slot_xt_flix64_slot2_set_field_fns[] = {
28119 - Field_t_Slot_xt_flix64_slot2_set,
28124 - Field_s_Slot_xt_flix64_slot2_set,
28133 - Field_r_Slot_xt_flix64_slot2_set,
28138 - Field_sargt_Slot_xt_flix64_slot2_set,
28153 - Field_imm7_Slot_xt_flix64_slot2_set,
28202 - Field_op0_s5_Slot_xt_flix64_slot2_set,
28203 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28204 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28205 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28206 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28207 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28208 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28209 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28210 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28211 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28212 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28213 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28214 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28215 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28227 +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
28228 + xtensa_insnbuf slotbuf)
28230 + slotbuf[0] = (insn[0] & 0xffffff);
28234 +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
28235 + const xtensa_insnbuf slotbuf)
28237 + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
28241 +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
28242 + xtensa_insnbuf slotbuf)
28244 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28248 +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
28249 + const xtensa_insnbuf slotbuf)
28251 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28255 +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
28256 + xtensa_insnbuf slotbuf)
28258 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28262 +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
28263 + const xtensa_insnbuf slotbuf)
28265 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28268 +static xtensa_get_field_fn
28269 +Slot_inst_get_field_fns[] = {
28270 + Field_t_Slot_inst_get,
28271 + Field_bbi4_Slot_inst_get,
28272 + Field_bbi_Slot_inst_get,
28273 + Field_imm12_Slot_inst_get,
28274 + Field_imm8_Slot_inst_get,
28275 + Field_s_Slot_inst_get,
28276 + Field_imm12b_Slot_inst_get,
28277 + Field_imm16_Slot_inst_get,
28278 + Field_m_Slot_inst_get,
28279 + Field_n_Slot_inst_get,
28280 + Field_offset_Slot_inst_get,
28281 + Field_op0_Slot_inst_get,
28282 + Field_op1_Slot_inst_get,
28283 + Field_op2_Slot_inst_get,
28284 + Field_r_Slot_inst_get,
28285 + Field_sa4_Slot_inst_get,
28286 + Field_sae4_Slot_inst_get,
28287 + Field_sae_Slot_inst_get,
28288 + Field_sal_Slot_inst_get,
28289 + Field_sargt_Slot_inst_get,
28290 + Field_sas4_Slot_inst_get,
28291 + Field_sas_Slot_inst_get,
28292 + Field_sr_Slot_inst_get,
28293 + Field_st_Slot_inst_get,
28294 + Field_thi3_Slot_inst_get,
28295 + Field_imm4_Slot_inst_get,
28296 + Field_mn_Slot_inst_get,
28300 @@ -20837,6 +9122,43 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28304 + Field_xt_wbr15_imm_Slot_inst_get,
28305 + Field_xt_wbr18_imm_Slot_inst_get,
28306 + Implicit_Field_ar0_get,
28307 + Implicit_Field_ar4_get,
28308 + Implicit_Field_ar8_get,
28309 + Implicit_Field_ar12_get
28312 +static xtensa_set_field_fn
28313 +Slot_inst_set_field_fns[] = {
28314 + Field_t_Slot_inst_set,
28315 + Field_bbi4_Slot_inst_set,
28316 + Field_bbi_Slot_inst_set,
28317 + Field_imm12_Slot_inst_set,
28318 + Field_imm8_Slot_inst_set,
28319 + Field_s_Slot_inst_set,
28320 + Field_imm12b_Slot_inst_set,
28321 + Field_imm16_Slot_inst_set,
28322 + Field_m_Slot_inst_set,
28323 + Field_n_Slot_inst_set,
28324 + Field_offset_Slot_inst_set,
28325 + Field_op0_Slot_inst_set,
28326 + Field_op1_Slot_inst_set,
28327 + Field_op2_Slot_inst_set,
28328 + Field_r_Slot_inst_set,
28329 + Field_sa4_Slot_inst_set,
28330 + Field_sae4_Slot_inst_set,
28331 + Field_sae_Slot_inst_set,
28332 + Field_sal_Slot_inst_set,
28333 + Field_sargt_Slot_inst_set,
28334 + Field_sas4_Slot_inst_set,
28335 + Field_sas_Slot_inst_set,
28336 + Field_sr_Slot_inst_set,
28337 + Field_st_Slot_inst_set,
28338 + Field_thi3_Slot_inst_set,
28339 + Field_imm4_Slot_inst_set,
28340 + Field_mn_Slot_inst_set,
28344 @@ -20845,14 +9167,8 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28348 - Implicit_Field_set,
28349 - Implicit_Field_set,
28350 - Implicit_Field_set,
28351 - Implicit_Field_set,
28352 - Implicit_Field_set,
28353 - Implicit_Field_set,
28354 - Implicit_Field_set,
28355 - Implicit_Field_set,
28356 + Field_xt_wbr15_imm_Slot_inst_set,
28357 + Field_xt_wbr18_imm_Slot_inst_set,
28358 Implicit_Field_set,
28359 Implicit_Field_set,
28360 Implicit_Field_set,
28361 @@ -20860,94 +9176,22 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28364 static xtensa_get_field_fn
28365 -Slot_xt_flix64_slot3_get_field_fns[] = {
28366 - Field_t_Slot_xt_flix64_slot3_get,
28368 - Field_bbi_Slot_xt_flix64_slot3_get,
28371 - Field_s_Slot_xt_flix64_slot3_get,
28380 - Field_r_Slot_xt_flix64_slot3_get,
28420 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
28442 +Slot_inst16a_get_field_fns[] = {
28443 + Field_t_Slot_inst16a_get,
28448 + Field_s_Slot_inst16a_get,
28454 + Field_op0_Slot_inst16a_get,
28457 + Field_r_Slot_inst16a_get,
28461 @@ -20955,93 +9199,44 @@ Slot_xt_flix64_slot3_get_field_fns[] = {
28465 + Field_sr_Slot_inst16a_get,
28466 + Field_st_Slot_inst16a_get,
28468 + Field_imm4_Slot_inst16a_get,
28470 + Field_i_Slot_inst16a_get,
28471 + Field_imm6lo_Slot_inst16a_get,
28472 + Field_imm6hi_Slot_inst16a_get,
28473 + Field_imm7lo_Slot_inst16a_get,
28474 + Field_imm7hi_Slot_inst16a_get,
28475 + Field_z_Slot_inst16a_get,
28476 + Field_imm6_Slot_inst16a_get,
28477 + Field_imm7_Slot_inst16a_get,
28479 - Field_op0_s6_Slot_xt_flix64_slot3_get,
28480 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28481 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
28482 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28483 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28484 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28485 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28486 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28487 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28488 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28489 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28490 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28491 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28492 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28493 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28494 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28495 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28496 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28497 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28498 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28499 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28500 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28501 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28502 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28503 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28505 Implicit_Field_ar0_get,
28506 Implicit_Field_ar4_get,
28507 Implicit_Field_ar8_get,
28508 - Implicit_Field_ar12_get,
28509 - Implicit_Field_mr0_get,
28510 - Implicit_Field_mr1_get,
28511 - Implicit_Field_mr2_get,
28512 - Implicit_Field_mr3_get,
28513 - Implicit_Field_bt16_get,
28514 - Implicit_Field_bs16_get,
28515 - Implicit_Field_br16_get,
28516 - Implicit_Field_brall_get
28517 + Implicit_Field_ar12_get
28520 static xtensa_set_field_fn
28521 -Slot_xt_flix64_slot3_set_field_fns[] = {
28522 - Field_t_Slot_xt_flix64_slot3_set,
28524 - Field_bbi_Slot_xt_flix64_slot3_set,
28527 - Field_s_Slot_xt_flix64_slot3_set,
28536 - Field_r_Slot_xt_flix64_slot3_set,
28553 +Slot_inst16a_set_field_fns[] = {
28554 + Field_t_Slot_inst16a_set,
28559 + Field_s_Slot_inst16a_set,
28565 + Field_op0_Slot_inst16a_set,
28568 + Field_r_Slot_inst16a_set,
28572 @@ -21049,22 +9244,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28576 + Field_sr_Slot_inst16a_set,
28577 + Field_st_Slot_inst16a_set,
28579 + Field_imm4_Slot_inst16a_set,
28581 + Field_i_Slot_inst16a_set,
28582 + Field_imm6lo_Slot_inst16a_set,
28583 + Field_imm6hi_Slot_inst16a_set,
28584 + Field_imm7lo_Slot_inst16a_set,
28585 + Field_imm7hi_Slot_inst16a_set,
28586 + Field_z_Slot_inst16a_set,
28587 + Field_imm6_Slot_inst16a_set,
28588 + Field_imm7_Slot_inst16a_set,
28591 + Implicit_Field_set,
28592 + Implicit_Field_set,
28593 + Implicit_Field_set,
28594 + Implicit_Field_set
28597 +static xtensa_get_field_fn
28598 +Slot_inst16b_get_field_fns[] = {
28599 + Field_t_Slot_inst16b_get,
28601 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
28605 + Field_s_Slot_inst16b_get,
28611 + Field_op0_Slot_inst16b_get,
28614 + Field_r_Slot_inst16b_get,
28618 @@ -21072,21 +9289,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28622 + Field_sr_Slot_inst16b_get,
28623 + Field_st_Slot_inst16b_get,
28625 + Field_imm4_Slot_inst16b_get,
28627 + Field_i_Slot_inst16b_get,
28628 + Field_imm6lo_Slot_inst16b_get,
28629 + Field_imm6hi_Slot_inst16b_get,
28630 + Field_imm7lo_Slot_inst16b_get,
28631 + Field_imm7hi_Slot_inst16b_get,
28632 + Field_z_Slot_inst16b_get,
28633 + Field_imm6_Slot_inst16b_get,
28634 + Field_imm7_Slot_inst16b_get,
28637 + Implicit_Field_ar0_get,
28638 + Implicit_Field_ar4_get,
28639 + Implicit_Field_ar8_get,
28640 + Implicit_Field_ar12_get
28643 +static xtensa_set_field_fn
28644 +Slot_inst16b_set_field_fns[] = {
28645 + Field_t_Slot_inst16b_set,
28650 + Field_s_Slot_inst16b_set,
28656 + Field_op0_Slot_inst16b_set,
28659 + Field_r_Slot_inst16b_set,
28663 @@ -21094,46 +9334,24 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28667 + Field_sr_Slot_inst16b_set,
28668 + Field_st_Slot_inst16b_set,
28670 + Field_imm4_Slot_inst16b_set,
28672 + Field_i_Slot_inst16b_set,
28673 + Field_imm6lo_Slot_inst16b_set,
28674 + Field_imm6hi_Slot_inst16b_set,
28675 + Field_imm7lo_Slot_inst16b_set,
28676 + Field_imm7hi_Slot_inst16b_set,
28677 + Field_z_Slot_inst16b_set,
28678 + Field_imm6_Slot_inst16b_set,
28679 + Field_imm7_Slot_inst16b_set,
28681 - Field_op0_s6_Slot_xt_flix64_slot3_set,
28682 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28683 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
28684 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28685 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28686 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28687 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28688 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28689 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28690 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28691 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28692 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28693 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28694 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28695 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28696 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28697 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28698 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28699 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28700 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28701 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28702 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28703 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28704 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28705 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28707 Implicit_Field_set,
28708 Implicit_Field_set,
28709 Implicit_Field_set,
28710 - Implicit_Field_set,
28711 - Implicit_Field_set,
28712 - Implicit_Field_set,
28713 - Implicit_Field_set,
28714 - Implicit_Field_set,
28715 - Implicit_Field_set,
28716 - Implicit_Field_set,
28717 - Implicit_Field_set,
28721 @@ -21149,27 +9367,7 @@ static xtensa_slot_internal slots[] = {
28722 { "Inst16b", "x16b", 0,
28723 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
28724 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
28725 - Slot_inst16b_decode, "nop.n" },
28726 - { "xt_flix64_slot0", "xt_format1", 0,
28727 - Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
28728 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28729 - Slot_xt_flix64_slot0_decode, "nop" },
28730 - { "xt_flix64_slot0", "xt_format2", 0,
28731 - Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
28732 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28733 - Slot_xt_flix64_slot0_decode, "nop" },
28734 - { "xt_flix64_slot1", "xt_format1", 1,
28735 - Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
28736 - Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
28737 - Slot_xt_flix64_slot1_decode, "nop" },
28738 - { "xt_flix64_slot2", "xt_format1", 2,
28739 - Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
28740 - Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
28741 - Slot_xt_flix64_slot2_decode, "nop" },
28742 - { "xt_flix64_slot3", "xt_format2", 1,
28743 - Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
28744 - Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
28745 - Slot_xt_flix64_slot3_decode, "nop" }
28746 + Slot_inst16b_decode, "nop.n" }
28750 @@ -21179,35 +9377,18 @@ static void
28751 Format_x24_encode (xtensa_insnbuf insn)
28758 Format_x16a_encode (xtensa_insnbuf insn)
28762 + insn[0] = 0x800000;
28766 Format_x16b_encode (xtensa_insnbuf insn)
28773 -Format_xt_format1_encode (xtensa_insnbuf insn)
28780 -Format_xt_format2_encode (xtensa_insnbuf insn)
28784 + insn[0] = 0xc00000;
28787 static int Format_x24_slots[] = { 0 };
28788 @@ -21216,32 +9397,22 @@ static int Format_x16a_slots[] = { 1 };
28790 static int Format_x16b_slots[] = { 2 };
28792 -static int Format_xt_format1_slots[] = { 3, 5, 6 };
28794 -static int Format_xt_format2_slots[] = { 4, 7 };
28796 static xtensa_format_internal formats[] = {
28797 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
28798 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
28799 - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
28800 - { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
28801 - { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
28802 + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
28807 format_decoder (const xtensa_insnbuf insn)
28809 - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
28810 + if ((insn[0] & 0x800000) == 0)
28811 return 0; /* x24 */
28812 - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
28813 + if ((insn[0] & 0xc00000) == 0x800000)
28814 return 1; /* x16a */
28815 - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
28816 + if ((insn[0] & 0xe00000) == 0xc00000)
28817 return 2; /* x16b */
28818 - if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
28819 - return 3; /* xt_format1 */
28820 - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
28821 - return 4; /* xt_format2 */
28825 @@ -21260,14 +9431,14 @@ static int length_table[16] = {
28836 length_decoder (const unsigned char *insn)
28838 - int op0 = insn[0] & 0xf;
28839 + int op0 = (insn[0] >> 4) & 0xf;
28840 return length_table[op0];
28843 @@ -21275,15 +9446,15 @@ length_decoder (const unsigned char *insn)
28844 /* Top-level ISA structure. */
28846 xtensa_isa_internal xtensa_modules = {
28847 - 0 /* little-endian */,
28848 - 8 /* insn_size */, 0,
28849 - 5, formats, format_decoder, length_decoder,
28851 - 135 /* num_fields */,
28856 + 1 /* big-endian */,
28857 + 3 /* insn_size */, 0,
28858 + 3, formats, format_decoder, length_decoder,
28860 + 41 /* num_fields */,
28865 NUM_STATES, states, 0,
28866 NUM_SYSREGS, sysregs, 0,
28867 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
28868 diff --git a/include/xtensa-config.h b/include/xtensa-config.h
28869 index 30f4f41..fe9b051 100644
28870 --- a/include/xtensa-config.h
28871 +++ b/include/xtensa-config.h
28873 /* Xtensa configuration settings.
28874 - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
28875 + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
28876 Free Software Foundation, Inc.
28877 - Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
28878 + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
28880 This program is free software; you can redistribute it and/or modify
28881 it under the terms of the GNU General Public License as published by
28883 #define XCHAL_HAVE_L32R 1
28885 #undef XSHAL_USE_ABSOLUTE_LITERALS
28886 -#define XSHAL_USE_ABSOLUTE_LITERALS 0
28888 -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
28889 -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
28890 +#define XSHAL_USE_ABSOLUTE_LITERALS 1
28892 #undef XCHAL_HAVE_MAC16
28893 #define XCHAL_HAVE_MAC16 0
28894 @@ -59,10 +56,10 @@
28895 #define XCHAL_HAVE_MUL32 1
28897 #undef XCHAL_HAVE_MUL32_HIGH
28898 -#define XCHAL_HAVE_MUL32_HIGH 0
28899 +#define XCHAL_HAVE_MUL32_HIGH 1
28901 #undef XCHAL_HAVE_DIV32
28902 -#define XCHAL_HAVE_DIV32 1
28903 +#define XCHAL_HAVE_DIV32 0
28905 #undef XCHAL_HAVE_NSA
28906 #define XCHAL_HAVE_NSA 1
28907 @@ -103,8 +100,6 @@
28908 #undef XCHAL_HAVE_FP_RSQRT
28909 #define XCHAL_HAVE_FP_RSQRT 0
28911 -#undef XCHAL_HAVE_DFP_accel
28912 -#define XCHAL_HAVE_DFP_accel 0
28913 #undef XCHAL_HAVE_WINDOWED
28914 #define XCHAL_HAVE_WINDOWED 1
28916 @@ -119,32 +114,32 @@
28919 #undef XCHAL_ICACHE_SIZE
28920 -#define XCHAL_ICACHE_SIZE 16384
28921 +#define XCHAL_ICACHE_SIZE 0
28923 #undef XCHAL_DCACHE_SIZE
28924 -#define XCHAL_DCACHE_SIZE 16384
28925 +#define XCHAL_DCACHE_SIZE 0
28927 #undef XCHAL_ICACHE_LINESIZE
28928 -#define XCHAL_ICACHE_LINESIZE 32
28929 +#define XCHAL_ICACHE_LINESIZE 16
28931 #undef XCHAL_DCACHE_LINESIZE
28932 -#define XCHAL_DCACHE_LINESIZE 32
28933 +#define XCHAL_DCACHE_LINESIZE 16
28935 #undef XCHAL_ICACHE_LINEWIDTH
28936 -#define XCHAL_ICACHE_LINEWIDTH 5
28937 +#define XCHAL_ICACHE_LINEWIDTH 4
28939 #undef XCHAL_DCACHE_LINEWIDTH
28940 -#define XCHAL_DCACHE_LINEWIDTH 5
28941 +#define XCHAL_DCACHE_LINEWIDTH 4
28943 #undef XCHAL_DCACHE_IS_WRITEBACK
28944 -#define XCHAL_DCACHE_IS_WRITEBACK 1
28945 +#define XCHAL_DCACHE_IS_WRITEBACK 0
28948 #undef XCHAL_HAVE_MMU
28949 #define XCHAL_HAVE_MMU 1
28951 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
28952 -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
28953 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29
28956 #undef XCHAL_HAVE_DEBUG
28957 @@ -157,8 +152,11 @@
28958 #define XCHAL_NUM_DBREAK 2
28960 #undef XCHAL_DEBUGLEVEL
28961 -#define XCHAL_DEBUGLEVEL 6
28962 +#define XCHAL_DEBUGLEVEL 4
28965 +#undef XCHAL_EXCM_LEVEL
28966 +#define XCHAL_EXCM_LEVEL 3
28968 #undef XCHAL_MAX_INSTRUCTION_SIZE
28969 #define XCHAL_MAX_INSTRUCTION_SIZE 3