1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
143 static inline const char *pci_power_name(pci_power_t state)
145 return pci_power_names[1 + (__force int) state];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t;
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t;
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
184 typedef unsigned short __bitwise pci_dev_flags_t;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
210 enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
215 typedef unsigned short __bitwise pci_bus_flags_t;
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
224 enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236 /* Based on the PCI Hotplug Spec, but some values are made up by us */
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
267 struct pci_cap_saved_data {
274 struct pci_cap_saved_state {
275 struct hlist_node next;
276 struct pci_cap_saved_data cap;
280 struct pcie_link_state;
285 /* The pci_dev structure describes PCI devices */
287 struct list_head bus_list; /* Node in per-bus list */
288 struct pci_bus *bus; /* Bus this device is on */
289 struct pci_bus *subordinate; /* Bus this device bridges to */
291 void *sysdata; /* Hook for sys-specific extension */
292 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
293 struct pci_slot *slot; /* Physical slot this device is in */
295 unsigned int devfn; /* Encoded device & function index */
296 unsigned short vendor;
297 unsigned short device;
298 unsigned short subsystem_vendor;
299 unsigned short subsystem_device;
300 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
301 u8 revision; /* PCI revision, low byte of class word */
302 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
303 #ifdef CONFIG_PCIEAER
304 u16 aer_cap; /* AER capability offset */
305 struct aer_stats *aer_stats; /* AER stats for this device */
307 u8 pcie_cap; /* PCIe capability offset */
308 u8 msi_cap; /* MSI capability offset */
309 u8 msix_cap; /* MSI-X capability offset */
310 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
311 u8 rom_base_reg; /* Config register controlling ROM */
312 u8 pin; /* Interrupt pin this device uses */
313 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
314 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
316 struct pci_driver *driver; /* Driver bound to this device */
317 u64 dma_mask; /* Mask of the bits of bus address this
318 device implements. Normally this is
319 0xffffffff. You only need to change
320 this if your device has broken DMA
321 or supports 64-bit transfers. */
323 struct device_dma_parameters dma_parms;
325 pci_power_t current_state; /* Current operating state. In ACPI,
326 this is D0-D3, D0 being fully
327 functional, and D3 being off. */
328 u8 pm_cap; /* PM capability offset */
329 unsigned int pme_support:5; /* Bitmask of states from which PME#
331 unsigned int pme_poll:1; /* Poll device's PME status bit */
332 unsigned int d1_support:1; /* Low power state D1 is supported */
333 unsigned int d2_support:1; /* Low power state D2 is supported */
334 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold:1; /* D3cold is forbidden */
336 unsigned int bridge_d3:1; /* Allow D3 for bridge */
337 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
338 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
339 decoding during BAR sizing */
340 unsigned int wakeup_prepared:1;
341 unsigned int runtime_d3cold:1; /* Whether go through runtime
342 D3cold, not set for devices
343 powered on/off by the
344 corresponding bridge */
345 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
346 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
347 controlled exclusively by
349 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
351 unsigned int d3_delay; /* D3->D0 transition time in ms */
352 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
354 #ifdef CONFIG_PCIEASPM
355 struct pcie_link_state *link_state; /* ASPM link state */
356 unsigned int ltr_path:1; /* Latency Tolerance Reporting
357 supported from root to here */
359 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
361 pci_channel_state_t error_state; /* Current connectivity state */
362 struct device dev; /* Generic device interface */
364 int cfg_size; /* Size of config space */
367 * Instead of touching interrupt line and base address registers
368 * directly, use the values stored here. They might be different!
371 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
373 bool match_driver; /* Skip attaching driver */
375 unsigned int transparent:1; /* Subtractive decode bridge */
376 unsigned int io_window:1; /* Bridge has I/O window */
377 unsigned int pref_window:1; /* Bridge has pref mem window */
378 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
379 unsigned int multifunction:1; /* Multi-function device */
381 unsigned int is_busmaster:1; /* Is busmaster */
382 unsigned int no_msi:1; /* May not use MSI */
383 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
384 unsigned int block_cfg_access:1; /* Config space access blocked */
385 unsigned int broken_parity_status:1; /* Generates false positive parity */
386 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
387 unsigned int msi_enabled:1;
388 unsigned int msix_enabled:1;
389 unsigned int ari_enabled:1; /* ARI forwarding */
390 unsigned int ats_enabled:1; /* Address Translation Svc */
391 unsigned int pasid_enabled:1; /* Process Address Space ID */
392 unsigned int pri_enabled:1; /* Page Request Interface */
393 unsigned int is_managed:1;
394 unsigned int needs_freset:1; /* Requires fundamental reset */
395 unsigned int state_saved:1;
396 unsigned int is_physfn:1;
397 unsigned int is_virtfn:1;
398 unsigned int reset_fn:1;
399 unsigned int is_hotplug_bridge:1;
400 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
401 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
402 unsigned int __aer_firmware_first_valid:1;
403 unsigned int __aer_firmware_first:1;
404 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
405 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
406 unsigned int irq_managed:1;
407 unsigned int has_secondary_link:1;
408 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
409 unsigned int is_probed:1; /* Device probing in progress */
410 pci_dev_flags_t dev_flags;
411 atomic_t enable_cnt; /* pci_enable_device has been called */
413 u32 saved_config_space[16]; /* Config space saved at suspend time */
414 struct hlist_head saved_cap_space;
415 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
416 int rom_attr_enabled; /* Display of ROM attribute enabled? */
417 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
418 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
420 #ifdef CONFIG_HOTPLUG_PCI_PCIE
421 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
423 #ifdef CONFIG_PCIE_PTM
424 unsigned int ptm_root:1;
425 unsigned int ptm_enabled:1;
428 #ifdef CONFIG_PCI_MSI
429 const struct attribute_group **msi_irq_groups;
432 #ifdef CONFIG_PCI_ATS
434 struct pci_sriov *sriov; /* PF: SR-IOV info */
435 struct pci_dev *physfn; /* VF: related PF */
437 u16 ats_cap; /* ATS Capability offset */
438 u8 ats_stu; /* ATS Smallest Translation Unit */
439 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
441 #ifdef CONFIG_PCI_PRI
442 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
444 #ifdef CONFIG_PCI_PASID
447 phys_addr_t rom; /* Physical address if not from BAR */
448 size_t romlen; /* Length if not from BAR */
449 char *driver_override; /* Driver name to force a match */
451 unsigned long priv_flags; /* Private flags for the PCI driver */
454 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
456 #ifdef CONFIG_PCI_IOV
463 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
465 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
466 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
468 static inline int pci_channel_offline(struct pci_dev *pdev)
470 return (pdev->error_state != pci_channel_io_normal);
473 struct pci_host_bridge {
475 struct pci_bus *bus; /* Root bus */
479 struct list_head windows; /* resource_entry */
480 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
481 int (*map_irq)(const struct pci_dev *, u8, u8);
482 void (*release_fn)(struct pci_host_bridge *);
484 struct msi_controller *msi;
485 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
486 unsigned int no_ext_tags:1; /* No Extended Tags */
487 unsigned int native_aer:1; /* OS may use PCIe AER */
488 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
489 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
490 unsigned int native_pme:1; /* OS may use PCIe PME */
491 unsigned int native_ltr:1; /* OS may use PCIe LTR */
492 /* Resource alignment requirements */
493 resource_size_t (*align_resource)(struct pci_dev *dev,
494 const struct resource *res,
495 resource_size_t start,
496 resource_size_t size,
497 resource_size_t align);
498 unsigned long private[0] ____cacheline_aligned;
501 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
503 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
505 return (void *)bridge->private;
508 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
510 return container_of(priv, struct pci_host_bridge, private);
513 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
514 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
516 void pci_free_host_bridge(struct pci_host_bridge *bridge);
517 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
519 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
520 void (*release_fn)(struct pci_host_bridge *),
523 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
526 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
527 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
528 * buses below host bridges or subtractive decode bridges) go in the list.
529 * Use pci_bus_for_each_resource() to iterate through all the resources.
533 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
534 * and there's no way to program the bridge with the details of the window.
535 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
536 * decode bit set, because they are explicit and can be programmed with _SRS.
538 #define PCI_SUBTRACTIVE_DECODE 0x1
540 struct pci_bus_resource {
541 struct list_head list;
542 struct resource *res;
546 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
549 struct list_head node; /* Node in list of buses */
550 struct pci_bus *parent; /* Parent bus this bridge is on */
551 struct list_head children; /* List of child buses */
552 struct list_head devices; /* List of devices on this bus */
553 struct pci_dev *self; /* Bridge device as seen by parent */
554 struct list_head slots; /* List of slots on this bus;
555 protected by pci_slot_mutex */
556 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
557 struct list_head resources; /* Address space routed to this bus */
558 struct resource busn_res; /* Bus numbers routed to this bus */
560 struct pci_ops *ops; /* Configuration access functions */
561 struct msi_controller *msi; /* MSI controller */
562 void *sysdata; /* Hook for sys-specific extension */
563 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
565 unsigned char number; /* Bus number */
566 unsigned char primary; /* Number of primary bridge */
567 unsigned char max_bus_speed; /* enum pci_bus_speed */
568 unsigned char cur_bus_speed; /* enum pci_bus_speed */
569 #ifdef CONFIG_PCI_DOMAINS_GENERIC
575 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
576 pci_bus_flags_t bus_flags; /* Inherited by child buses */
577 struct device *bridge;
579 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
580 struct bin_attribute *legacy_mem; /* Legacy mem */
581 unsigned int is_added:1;
584 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
587 * Returns true if the PCI bus is root (behind host-PCI bridge),
590 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
591 * This is incorrect because "virtual" buses added for SR-IOV (via
592 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
594 static inline bool pci_is_root_bus(struct pci_bus *pbus)
596 return !(pbus->parent);
600 * pci_is_bridge - check if the PCI device is a bridge
603 * Return true if the PCI device is bridge whether it has subordinate
606 static inline bool pci_is_bridge(struct pci_dev *dev)
608 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
609 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
612 #define for_each_pci_bridge(dev, bus) \
613 list_for_each_entry(dev, &bus->devices, bus_list) \
614 if (!pci_is_bridge(dev)) {} else
616 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
618 dev = pci_physfn(dev);
619 if (pci_is_root_bus(dev->bus))
622 return dev->bus->self;
625 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
626 void pci_put_host_bridge_device(struct device *dev);
628 #ifdef CONFIG_PCI_MSI
629 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
631 return pci_dev->msi_enabled || pci_dev->msix_enabled;
634 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
637 /* Error values that may be returned by PCI functions */
638 #define PCIBIOS_SUCCESSFUL 0x00
639 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
640 #define PCIBIOS_BAD_VENDOR_ID 0x83
641 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
642 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
643 #define PCIBIOS_SET_FAILED 0x88
644 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
646 /* Translate above to generic errno for passing back through non-PCI code */
647 static inline int pcibios_err_to_errno(int err)
649 if (err <= PCIBIOS_SUCCESSFUL)
650 return err; /* Assume already errno */
653 case PCIBIOS_FUNC_NOT_SUPPORTED:
655 case PCIBIOS_BAD_VENDOR_ID:
657 case PCIBIOS_DEVICE_NOT_FOUND:
659 case PCIBIOS_BAD_REGISTER_NUMBER:
661 case PCIBIOS_SET_FAILED:
663 case PCIBIOS_BUFFER_TOO_SMALL:
670 /* Low-level architecture-dependent routines */
673 int (*add_bus)(struct pci_bus *bus);
674 void (*remove_bus)(struct pci_bus *bus);
675 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
676 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
677 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
681 * ACPI needs to be able to access PCI config space before we've done a
682 * PCI bus scan and created pci_bus structures.
684 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
685 int reg, int len, u32 *val);
686 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
687 int reg, int len, u32 val);
689 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
690 typedef u64 pci_bus_addr_t;
692 typedef u32 pci_bus_addr_t;
695 struct pci_bus_region {
696 pci_bus_addr_t start;
701 spinlock_t lock; /* Protects list, index */
702 struct list_head list; /* For IDs added at runtime */
707 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
708 * a set of callbacks in struct pci_error_handlers, that device driver
709 * will be notified of PCI bus errors, and will be driven to recovery
710 * when an error occurs.
713 typedef unsigned int __bitwise pci_ers_result_t;
715 enum pci_ers_result {
716 /* No result/none/not supported in device driver */
717 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
719 /* Device driver can recover without slot reset */
720 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
722 /* Device driver wants slot to be reset */
723 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
725 /* Device has completely failed, is unrecoverable */
726 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
728 /* Device driver is fully recovered and operational */
729 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
731 /* No AER capabilities registered for the driver */
732 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
735 /* PCI bus error event callbacks */
736 struct pci_error_handlers {
737 /* PCI bus error detected on this device */
738 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
739 enum pci_channel_state error);
741 /* MMIO has been re-enabled, but not DMA */
742 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
744 /* PCI slot has been reset */
745 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
747 /* PCI function reset prepare or completed */
748 void (*reset_prepare)(struct pci_dev *dev);
749 void (*reset_done)(struct pci_dev *dev);
751 /* Device driver may resume normal operations */
752 void (*resume)(struct pci_dev *dev);
758 struct list_head node;
760 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
761 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
762 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
763 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
764 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
765 int (*resume_early)(struct pci_dev *dev);
766 int (*resume) (struct pci_dev *dev); /* Device woken up */
767 void (*shutdown) (struct pci_dev *dev);
768 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
769 const struct pci_error_handlers *err_handler;
770 const struct attribute_group **groups;
771 struct device_driver driver;
772 struct pci_dynids dynids;
775 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
778 * PCI_DEVICE - macro used to describe a specific PCI device
779 * @vend: the 16 bit PCI Vendor ID
780 * @dev: the 16 bit PCI Device ID
782 * This macro is used to create a struct pci_device_id that matches a
783 * specific device. The subvendor and subdevice fields will be set to
786 #define PCI_DEVICE(vend,dev) \
787 .vendor = (vend), .device = (dev), \
788 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
791 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
792 * @vend: the 16 bit PCI Vendor ID
793 * @dev: the 16 bit PCI Device ID
794 * @subvend: the 16 bit PCI Subvendor ID
795 * @subdev: the 16 bit PCI Subdevice ID
797 * This macro is used to create a struct pci_device_id that matches a
798 * specific device with subsystem information.
800 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
801 .vendor = (vend), .device = (dev), \
802 .subvendor = (subvend), .subdevice = (subdev)
805 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
806 * @dev_class: the class, subclass, prog-if triple for this device
807 * @dev_class_mask: the class mask for this device
809 * This macro is used to create a struct pci_device_id that matches a
810 * specific PCI class. The vendor, device, subvendor, and subdevice
811 * fields will be set to PCI_ANY_ID.
813 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
814 .class = (dev_class), .class_mask = (dev_class_mask), \
815 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
816 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
819 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
820 * @vend: the vendor name
821 * @dev: the 16 bit PCI Device ID
823 * This macro is used to create a struct pci_device_id that matches a
824 * specific PCI device. The subvendor, and subdevice fields will be set
825 * to PCI_ANY_ID. The macro allows the next field to follow as the device
828 #define PCI_VDEVICE(vend, dev) \
829 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
830 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
833 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
834 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
835 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
836 * @data: the driver data to be filled
838 * This macro is used to create a struct pci_device_id that matches a
839 * specific PCI device. The subvendor, and subdevice fields will be set
842 #define PCI_DEVICE_DATA(vend, dev, data) \
843 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
844 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
845 .driver_data = (kernel_ulong_t)(data)
848 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
849 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
850 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
851 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
852 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
853 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
854 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
857 /* These external functions are only available when PCI support is enabled */
860 extern unsigned int pci_flags;
862 static inline void pci_set_flags(int flags) { pci_flags = flags; }
863 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
864 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
865 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
867 void pcie_bus_configure_settings(struct pci_bus *bus);
869 enum pcie_bus_config_types {
870 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
871 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
872 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
873 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
874 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
877 extern enum pcie_bus_config_types pcie_bus_config;
879 extern struct bus_type pci_bus_type;
881 /* Do NOT directly access these two variables, unless you are arch-specific PCI
882 * code, or PCI core code. */
883 extern struct list_head pci_root_buses; /* List of all known PCI buses */
884 /* Some device drivers need know if PCI is initiated */
885 int no_pci_devices(void);
887 void pcibios_resource_survey_bus(struct pci_bus *bus);
888 void pcibios_bus_add_device(struct pci_dev *pdev);
889 void pcibios_add_bus(struct pci_bus *bus);
890 void pcibios_remove_bus(struct pci_bus *bus);
891 void pcibios_fixup_bus(struct pci_bus *);
892 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
893 /* Architecture-specific versions may override this (weak) */
894 char *pcibios_setup(char *str);
896 /* Used only when drivers/pci/setup.c is used */
897 resource_size_t pcibios_align_resource(void *, const struct resource *,
901 /* Weak but can be overriden by arch */
902 void pci_fixup_cardbus(struct pci_bus *);
904 /* Generic PCI functions used internally */
906 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
907 struct resource *res);
908 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
909 struct pci_bus_region *region);
910 void pcibios_scan_specific_bus(int busn);
911 struct pci_bus *pci_find_bus(int domain, int busnr);
912 void pci_bus_add_devices(const struct pci_bus *bus);
913 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
914 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
915 struct pci_ops *ops, void *sysdata,
916 struct list_head *resources);
917 int pci_host_probe(struct pci_host_bridge *bridge);
918 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
919 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
920 void pci_bus_release_busn_res(struct pci_bus *b);
921 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
922 struct pci_ops *ops, void *sysdata,
923 struct list_head *resources);
924 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
925 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
927 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
928 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
930 struct hotplug_slot *hotplug);
931 void pci_destroy_slot(struct pci_slot *slot);
933 void pci_dev_assign_slot(struct pci_dev *dev);
935 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
937 int pci_scan_slot(struct pci_bus *bus, int devfn);
938 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
939 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
940 unsigned int pci_scan_child_bus(struct pci_bus *bus);
941 void pci_bus_add_device(struct pci_dev *dev);
942 void pci_read_bridge_bases(struct pci_bus *child);
943 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
944 struct resource *res);
945 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
946 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
947 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
948 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
949 struct pci_dev *pci_dev_get(struct pci_dev *dev);
950 void pci_dev_put(struct pci_dev *dev);
951 void pci_remove_bus(struct pci_bus *b);
952 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
953 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
954 void pci_stop_root_bus(struct pci_bus *bus);
955 void pci_remove_root_bus(struct pci_bus *bus);
956 void pci_setup_cardbus(struct pci_bus *bus);
957 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
958 void pci_sort_breadthfirst(void);
959 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
960 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
962 /* Generic PCI functions exported to card drivers */
964 enum pci_lost_interrupt_reason {
965 PCI_LOST_IRQ_NO_INFORMATION = 0,
966 PCI_LOST_IRQ_DISABLE_MSI,
967 PCI_LOST_IRQ_DISABLE_MSIX,
968 PCI_LOST_IRQ_DISABLE_ACPI,
970 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
971 int pci_find_capability(struct pci_dev *dev, int cap);
972 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
973 int pci_find_ext_capability(struct pci_dev *dev, int cap);
974 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
975 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
976 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
977 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
979 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
980 struct pci_dev *from);
981 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
982 unsigned int ss_vendor, unsigned int ss_device,
983 struct pci_dev *from);
984 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
985 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
987 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
988 int pci_dev_present(const struct pci_device_id *ids);
990 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
992 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
993 int where, u16 *val);
994 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
995 int where, u32 *val);
996 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
998 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1000 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1001 int where, u32 val);
1003 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1004 int where, int size, u32 *val);
1005 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1006 int where, int size, u32 val);
1007 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1008 int where, int size, u32 *val);
1009 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1010 int where, int size, u32 val);
1012 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1014 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1015 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1016 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1017 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1018 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1019 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1021 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1022 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1023 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1024 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1025 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1026 u16 clear, u16 set);
1027 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1028 u32 clear, u32 set);
1030 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1033 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1036 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1039 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1042 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1045 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1048 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1051 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1054 /* User-space driven config access */
1055 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1056 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1057 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1058 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1059 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1060 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1062 int __must_check pci_enable_device(struct pci_dev *dev);
1063 int __must_check pci_enable_device_io(struct pci_dev *dev);
1064 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1065 int __must_check pci_reenable_device(struct pci_dev *);
1066 int __must_check pcim_enable_device(struct pci_dev *pdev);
1067 void pcim_pin_device(struct pci_dev *pdev);
1069 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1072 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1073 * writable and no quirk has marked the feature broken.
1075 return !pdev->broken_intx_masking;
1078 static inline int pci_is_enabled(struct pci_dev *pdev)
1080 return (atomic_read(&pdev->enable_cnt) > 0);
1083 static inline int pci_is_managed(struct pci_dev *pdev)
1085 return pdev->is_managed;
1088 void pci_disable_device(struct pci_dev *dev);
1090 extern unsigned int pcibios_max_latency;
1091 void pci_set_master(struct pci_dev *dev);
1092 void pci_clear_master(struct pci_dev *dev);
1094 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1095 int pci_set_cacheline_size(struct pci_dev *dev);
1096 #define HAVE_PCI_SET_MWI
1097 int __must_check pci_set_mwi(struct pci_dev *dev);
1098 int __must_check pcim_set_mwi(struct pci_dev *dev);
1099 int pci_try_set_mwi(struct pci_dev *dev);
1100 void pci_clear_mwi(struct pci_dev *dev);
1101 void pci_intx(struct pci_dev *dev, int enable);
1102 bool pci_check_and_mask_intx(struct pci_dev *dev);
1103 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1104 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1105 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1106 int pcix_get_max_mmrbc(struct pci_dev *dev);
1107 int pcix_get_mmrbc(struct pci_dev *dev);
1108 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1109 int pcie_get_readrq(struct pci_dev *dev);
1110 int pcie_set_readrq(struct pci_dev *dev, int rq);
1111 int pcie_get_mps(struct pci_dev *dev);
1112 int pcie_set_mps(struct pci_dev *dev, int mps);
1113 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1114 enum pci_bus_speed *speed,
1115 enum pcie_link_width *width);
1116 void pcie_print_link_status(struct pci_dev *dev);
1117 bool pcie_has_flr(struct pci_dev *dev);
1118 int pcie_flr(struct pci_dev *dev);
1119 int __pci_reset_function_locked(struct pci_dev *dev);
1120 int pci_reset_function(struct pci_dev *dev);
1121 int pci_reset_function_locked(struct pci_dev *dev);
1122 int pci_try_reset_function(struct pci_dev *dev);
1123 int pci_probe_reset_slot(struct pci_slot *slot);
1124 int pci_probe_reset_bus(struct pci_bus *bus);
1125 int pci_reset_bus(struct pci_dev *dev);
1126 void pci_reset_secondary_bus(struct pci_dev *dev);
1127 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1128 void pci_update_resource(struct pci_dev *dev, int resno);
1129 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1130 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1131 void pci_release_resource(struct pci_dev *dev, int resno);
1132 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1133 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1134 bool pci_device_is_present(struct pci_dev *pdev);
1135 void pci_ignore_hotplug(struct pci_dev *dev);
1137 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1138 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1139 const char *fmt, ...);
1140 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1142 /* ROM control related routines */
1143 int pci_enable_rom(struct pci_dev *pdev);
1144 void pci_disable_rom(struct pci_dev *pdev);
1145 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1146 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1148 /* Power management related routines */
1149 int pci_save_state(struct pci_dev *dev);
1150 void pci_restore_state(struct pci_dev *dev);
1151 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1152 int pci_load_saved_state(struct pci_dev *dev,
1153 struct pci_saved_state *state);
1154 int pci_load_and_free_saved_state(struct pci_dev *dev,
1155 struct pci_saved_state **state);
1156 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1157 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1159 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1160 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1161 u16 cap, unsigned int size);
1162 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1163 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1164 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1165 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1166 void pci_pme_active(struct pci_dev *dev, bool enable);
1167 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1168 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1169 int pci_prepare_to_sleep(struct pci_dev *dev);
1170 int pci_back_from_sleep(struct pci_dev *dev);
1171 bool pci_dev_run_wake(struct pci_dev *dev);
1172 bool pci_check_pme_status(struct pci_dev *dev);
1173 void pci_pme_wakeup_bus(struct pci_bus *bus);
1174 void pci_d3cold_enable(struct pci_dev *dev);
1175 void pci_d3cold_disable(struct pci_dev *dev);
1176 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1177 void pci_wakeup_bus(struct pci_bus *bus);
1178 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1180 /* PCI Virtual Channel */
1181 int pci_save_vc_state(struct pci_dev *dev);
1182 void pci_restore_vc_state(struct pci_dev *dev);
1183 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1185 /* For use by arch with custom probe code */
1186 void set_pcie_port_type(struct pci_dev *pdev);
1187 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1189 /* Functions for PCI Hotplug drivers to use */
1190 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1191 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1192 unsigned int pci_rescan_bus(struct pci_bus *bus);
1193 void pci_lock_rescan_remove(void);
1194 void pci_unlock_rescan_remove(void);
1196 /* Vital Product Data routines */
1197 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1198 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1199 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1201 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1202 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1203 void pci_bus_assign_resources(const struct pci_bus *bus);
1204 void pci_bus_claim_resources(struct pci_bus *bus);
1205 void pci_bus_size_bridges(struct pci_bus *bus);
1206 int pci_claim_resource(struct pci_dev *, int);
1207 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1208 void pci_assign_unassigned_resources(void);
1209 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1210 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1211 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1212 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1213 void pdev_enable_device(struct pci_dev *);
1214 int pci_enable_resources(struct pci_dev *, int mask);
1215 void pci_assign_irq(struct pci_dev *dev);
1216 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1217 #define HAVE_PCI_REQ_REGIONS 2
1218 int __must_check pci_request_regions(struct pci_dev *, const char *);
1219 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1220 void pci_release_regions(struct pci_dev *);
1221 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1222 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1223 void pci_release_region(struct pci_dev *, int);
1224 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1225 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1226 void pci_release_selected_regions(struct pci_dev *, int);
1228 /* drivers/pci/bus.c */
1229 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1230 void pci_bus_put(struct pci_bus *bus);
1231 void pci_add_resource(struct list_head *resources, struct resource *res);
1232 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1233 resource_size_t offset);
1234 void pci_free_resource_list(struct list_head *resources);
1235 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1236 unsigned int flags);
1237 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1238 void pci_bus_remove_resources(struct pci_bus *bus);
1239 int devm_request_pci_bus_resources(struct device *dev,
1240 struct list_head *resources);
1242 /* Temporary until new and working PCI SBR API in place */
1243 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1245 #define pci_bus_for_each_resource(bus, res, i) \
1247 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1250 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1251 struct resource *res, resource_size_t size,
1252 resource_size_t align, resource_size_t min,
1253 unsigned long type_mask,
1254 resource_size_t (*alignf)(void *,
1255 const struct resource *,
1261 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1262 resource_size_t size);
1263 unsigned long pci_address_to_pio(phys_addr_t addr);
1264 phys_addr_t pci_pio_to_address(unsigned long pio);
1265 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1266 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1267 phys_addr_t phys_addr);
1268 void pci_unmap_iospace(struct resource *res);
1269 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1270 resource_size_t offset,
1271 resource_size_t size);
1272 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1273 struct resource *res);
1275 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1277 struct pci_bus_region region;
1279 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1280 return region.start;
1283 /* Proper probing supporting hot-pluggable devices */
1284 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1285 const char *mod_name);
1287 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1288 #define pci_register_driver(driver) \
1289 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1291 void pci_unregister_driver(struct pci_driver *dev);
1294 * module_pci_driver() - Helper macro for registering a PCI driver
1295 * @__pci_driver: pci_driver struct
1297 * Helper macro for PCI drivers which do not do anything special in module
1298 * init/exit. This eliminates a lot of boilerplate. Each module may only
1299 * use this macro once, and calling it replaces module_init() and module_exit()
1301 #define module_pci_driver(__pci_driver) \
1302 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1305 * builtin_pci_driver() - Helper macro for registering a PCI driver
1306 * @__pci_driver: pci_driver struct
1308 * Helper macro for PCI drivers which do not do anything special in their
1309 * init code. This eliminates a lot of boilerplate. Each driver may only
1310 * use this macro once, and calling it replaces device_initcall(...)
1312 #define builtin_pci_driver(__pci_driver) \
1313 builtin_driver(__pci_driver, pci_register_driver)
1315 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1316 int pci_add_dynid(struct pci_driver *drv,
1317 unsigned int vendor, unsigned int device,
1318 unsigned int subvendor, unsigned int subdevice,
1319 unsigned int class, unsigned int class_mask,
1320 unsigned long driver_data);
1321 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1322 struct pci_dev *dev);
1323 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1326 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1328 int pci_cfg_space_size(struct pci_dev *dev);
1329 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1330 void pci_setup_bridge(struct pci_bus *bus);
1331 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1332 unsigned long type);
1334 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1335 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1337 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1338 unsigned int command_bits, u32 flags);
1340 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1341 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1342 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1343 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1344 #define PCI_IRQ_ALL_TYPES \
1345 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1347 /* kmem_cache style wrapper around pci_alloc_consistent() */
1349 #include <linux/pci-dma.h>
1350 #include <linux/dmapool.h>
1352 #define pci_pool dma_pool
1353 #define pci_pool_create(name, pdev, size, align, allocation) \
1354 dma_pool_create(name, &pdev->dev, size, align, allocation)
1355 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1356 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1357 #define pci_pool_zalloc(pool, flags, handle) \
1358 dma_pool_zalloc(pool, flags, handle)
1359 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1362 u32 vector; /* Kernel uses to write allocated vector */
1363 u16 entry; /* Driver uses to specify entry, OS writes */
1366 #ifdef CONFIG_PCI_MSI
1367 int pci_msi_vec_count(struct pci_dev *dev);
1368 void pci_disable_msi(struct pci_dev *dev);
1369 int pci_msix_vec_count(struct pci_dev *dev);
1370 void pci_disable_msix(struct pci_dev *dev);
1371 void pci_restore_msi_state(struct pci_dev *dev);
1372 int pci_msi_enabled(void);
1373 int pci_enable_msi(struct pci_dev *dev);
1374 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1375 int minvec, int maxvec);
1376 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1377 struct msix_entry *entries, int nvec)
1379 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1384 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1385 unsigned int max_vecs, unsigned int flags,
1386 const struct irq_affinity *affd);
1388 void pci_free_irq_vectors(struct pci_dev *dev);
1389 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1390 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1391 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1394 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1395 static inline void pci_disable_msi(struct pci_dev *dev) { }
1396 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1397 static inline void pci_disable_msix(struct pci_dev *dev) { }
1398 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1399 static inline int pci_msi_enabled(void) { return 0; }
1400 static inline int pci_enable_msi(struct pci_dev *dev)
1402 static inline int pci_enable_msix_range(struct pci_dev *dev,
1403 struct msix_entry *entries, int minvec, int maxvec)
1405 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1406 struct msix_entry *entries, int nvec)
1410 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1411 unsigned int max_vecs, unsigned int flags,
1412 const struct irq_affinity *aff_desc)
1414 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1419 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1423 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1425 if (WARN_ON_ONCE(nr > 0))
1429 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1432 return cpu_possible_mask;
1435 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1437 return first_online_node;
1442 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1443 unsigned int max_vecs, unsigned int flags)
1445 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1450 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1451 * @d: the INTx IRQ domain
1452 * @node: the DT node for the device whose interrupt we're translating
1453 * @intspec: the interrupt specifier data from the DT
1454 * @intsize: the number of entries in @intspec
1455 * @out_hwirq: pointer at which to write the hwirq number
1456 * @out_type: pointer at which to write the interrupt type
1458 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1459 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1460 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1461 * INTx value to obtain the hwirq number.
1463 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1465 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1466 struct device_node *node,
1468 unsigned int intsize,
1469 unsigned long *out_hwirq,
1470 unsigned int *out_type)
1472 const u32 intx = intspec[0];
1474 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1477 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1481 #ifdef CONFIG_PCIEPORTBUS
1482 extern bool pcie_ports_disabled;
1483 extern bool pcie_ports_native;
1485 #define pcie_ports_disabled true
1486 #define pcie_ports_native false
1489 #ifdef CONFIG_PCIEASPM
1490 bool pcie_aspm_support_enabled(void);
1492 static inline bool pcie_aspm_support_enabled(void) { return false; }
1495 #ifdef CONFIG_PCIEAER
1496 bool pci_aer_available(void);
1498 static inline bool pci_aer_available(void) { return false; }
1501 #ifdef CONFIG_PCIE_ECRC
1502 void pcie_set_ecrc_checking(struct pci_dev *dev);
1503 void pcie_ecrc_get_policy(char *str);
1505 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1506 static inline void pcie_ecrc_get_policy(char *str) { }
1509 bool pci_ats_disabled(void);
1511 #ifdef CONFIG_PCI_ATS
1512 /* Address Translation Service */
1513 void pci_ats_init(struct pci_dev *dev);
1514 int pci_enable_ats(struct pci_dev *dev, int ps);
1515 void pci_disable_ats(struct pci_dev *dev);
1516 int pci_ats_queue_depth(struct pci_dev *dev);
1518 static inline void pci_ats_init(struct pci_dev *d) { }
1519 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1520 static inline void pci_disable_ats(struct pci_dev *d) { }
1521 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1524 #ifdef CONFIG_PCIE_PTM
1525 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1527 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1531 void pci_cfg_access_lock(struct pci_dev *dev);
1532 bool pci_cfg_access_trylock(struct pci_dev *dev);
1533 void pci_cfg_access_unlock(struct pci_dev *dev);
1536 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1537 * a PCI domain is defined to be a set of PCI buses which share
1538 * configuration space.
1540 #ifdef CONFIG_PCI_DOMAINS
1541 extern int pci_domains_supported;
1543 enum { pci_domains_supported = 0 };
1544 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1545 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1546 #endif /* CONFIG_PCI_DOMAINS */
1549 * Generic implementation for PCI domain support. If your
1550 * architecture does not need custom management of PCI
1551 * domains then this implementation will be used
1553 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1554 static inline int pci_domain_nr(struct pci_bus *bus)
1556 return bus->domain_nr;
1559 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1561 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1564 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1567 /* Some architectures require additional setup to direct VGA traffic */
1568 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1569 unsigned int command_bits, u32 flags);
1570 void pci_register_set_vga_state(arch_set_vga_state_t func);
1573 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1575 return pci_request_selected_regions(pdev,
1576 pci_select_bars(pdev, IORESOURCE_IO), name);
1580 pci_release_io_regions(struct pci_dev *pdev)
1582 return pci_release_selected_regions(pdev,
1583 pci_select_bars(pdev, IORESOURCE_IO));
1587 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1589 return pci_request_selected_regions(pdev,
1590 pci_select_bars(pdev, IORESOURCE_MEM), name);
1594 pci_release_mem_regions(struct pci_dev *pdev)
1596 return pci_release_selected_regions(pdev,
1597 pci_select_bars(pdev, IORESOURCE_MEM));
1600 #else /* CONFIG_PCI is not enabled */
1602 static inline void pci_set_flags(int flags) { }
1603 static inline void pci_add_flags(int flags) { }
1604 static inline void pci_clear_flags(int flags) { }
1605 static inline int pci_has_flag(int flag) { return 0; }
1608 * If the system does not have PCI, clearly these return errors. Define
1609 * these as simple inline functions to avoid hair in drivers.
1611 #define _PCI_NOP(o, s, t) \
1612 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1614 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1616 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1617 _PCI_NOP(o, word, u16 x) \
1618 _PCI_NOP(o, dword, u32 x)
1619 _PCI_NOP_ALL(read, *)
1620 _PCI_NOP_ALL(write,)
1622 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1623 unsigned int device,
1624 struct pci_dev *from)
1627 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1628 unsigned int device,
1629 unsigned int ss_vendor,
1630 unsigned int ss_device,
1631 struct pci_dev *from)
1634 static inline struct pci_dev *pci_get_class(unsigned int class,
1635 struct pci_dev *from)
1638 #define pci_dev_present(ids) (0)
1639 #define no_pci_devices() (1)
1640 #define pci_dev_put(dev) do { } while (0)
1642 static inline void pci_set_master(struct pci_dev *dev) { }
1643 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1644 static inline void pci_disable_device(struct pci_dev *dev) { }
1645 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1647 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1648 struct module *owner,
1649 const char *mod_name)
1651 static inline int pci_register_driver(struct pci_driver *drv)
1653 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1654 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1656 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1659 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1662 /* Power management related routines */
1663 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1664 static inline void pci_restore_state(struct pci_dev *dev) { }
1665 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1667 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1669 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1672 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1676 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1677 struct resource *res)
1679 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1681 static inline void pci_release_regions(struct pci_dev *dev) { }
1683 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1685 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1686 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1688 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1690 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1692 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1695 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1696 unsigned int bus, unsigned int devfn)
1699 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1700 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1702 #define dev_is_pci(d) (false)
1703 #define dev_is_pf(d) (false)
1704 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1706 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1707 struct device_node *node,
1709 unsigned int intsize,
1710 unsigned long *out_hwirq,
1711 unsigned int *out_type)
1713 #endif /* CONFIG_PCI */
1715 /* Include architecture-dependent settings and functions */
1717 #include <asm/pci.h>
1719 /* These two functions provide almost identical functionality. Depennding
1720 * on the architecture, one will be implemented as a wrapper around the
1721 * other (in drivers/pci/mmap.c).
1723 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1724 * is expected to be an offset within that region.
1726 * pci_mmap_page_range() is the legacy architecture-specific interface,
1727 * which accepts a "user visible" resource address converted by
1728 * pci_resource_to_user(), as used in the legacy mmap() interface in
1731 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1732 struct vm_area_struct *vma,
1733 enum pci_mmap_state mmap_state, int write_combine);
1734 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1735 struct vm_area_struct *vma,
1736 enum pci_mmap_state mmap_state, int write_combine);
1738 #ifndef arch_can_pci_mmap_wc
1739 #define arch_can_pci_mmap_wc() 0
1742 #ifndef arch_can_pci_mmap_io
1743 #define arch_can_pci_mmap_io() 0
1744 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1746 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1749 #ifndef pci_root_bus_fwnode
1750 #define pci_root_bus_fwnode(bus) NULL
1754 * These helpers provide future and backwards compatibility
1755 * for accessing popular PCI BAR info
1757 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1758 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1759 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1760 #define pci_resource_len(dev,bar) \
1761 ((pci_resource_start((dev), (bar)) == 0 && \
1762 pci_resource_end((dev), (bar)) == \
1763 pci_resource_start((dev), (bar))) ? 0 : \
1765 (pci_resource_end((dev), (bar)) - \
1766 pci_resource_start((dev), (bar)) + 1))
1769 * Similar to the helpers above, these manipulate per-pci_dev
1770 * driver-specific data. They are really just a wrapper around
1771 * the generic device structure functions of these calls.
1773 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1775 return dev_get_drvdata(&pdev->dev);
1778 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1780 dev_set_drvdata(&pdev->dev, data);
1783 static inline const char *pci_name(const struct pci_dev *pdev)
1785 return dev_name(&pdev->dev);
1790 * Some archs don't want to expose struct resource to userland as-is
1791 * in sysfs and /proc
1793 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1794 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1795 const struct resource *rsrc,
1796 resource_size_t *start, resource_size_t *end);
1798 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1799 const struct resource *rsrc, resource_size_t *start,
1800 resource_size_t *end)
1802 *start = rsrc->start;
1805 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1809 * The world is not perfect and supplies us with broken PCI devices.
1810 * For at least a part of these bugs we need a work-around, so both
1811 * generic (drivers/pci/quirks.c) and per-architecture code can define
1812 * fixup hooks to be called for particular buggy devices.
1816 u16 vendor; /* Or PCI_ANY_ID */
1817 u16 device; /* Or PCI_ANY_ID */
1818 u32 class; /* Or PCI_ANY_ID */
1819 unsigned int class_shift; /* should be 0, 8, 16 */
1820 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1823 void (*hook)(struct pci_dev *dev);
1827 enum pci_fixup_pass {
1828 pci_fixup_early, /* Before probing BARs */
1829 pci_fixup_header, /* After reading configuration header */
1830 pci_fixup_final, /* Final phase of device fixups */
1831 pci_fixup_enable, /* pci_enable_device() time */
1832 pci_fixup_resume, /* pci_device_resume() */
1833 pci_fixup_suspend, /* pci_device_suspend() */
1834 pci_fixup_resume_early, /* pci_device_resume_early() */
1835 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1838 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1839 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1840 class_shift, hook) \
1841 __ADDRESSABLE(hook) \
1842 asm(".section " #sec ", \"a\" \n" \
1844 ".short " #vendor ", " #device " \n" \
1845 ".long " #class ", " #class_shift " \n" \
1846 ".long " #hook " - . \n" \
1848 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1849 class_shift, hook) \
1850 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1853 /* Anonymous variables would be nice... */
1854 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1855 class_shift, hook) \
1856 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1857 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1858 = { vendor, device, class, class_shift, hook };
1861 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1862 class_shift, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1864 hook, vendor, device, class, class_shift, hook)
1865 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1866 class_shift, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1868 hook, vendor, device, class, class_shift, hook)
1869 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1870 class_shift, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1872 hook, vendor, device, class, class_shift, hook)
1873 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1874 class_shift, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1876 hook, vendor, device, class, class_shift, hook)
1877 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1878 class_shift, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1880 resume##hook, vendor, device, class, class_shift, hook)
1881 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1882 class_shift, hook) \
1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1884 resume_early##hook, vendor, device, class, class_shift, hook)
1885 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1886 class_shift, hook) \
1887 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1888 suspend##hook, vendor, device, class, class_shift, hook)
1889 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1890 class_shift, hook) \
1891 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1892 suspend_late##hook, vendor, device, class, class_shift, hook)
1894 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1895 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1896 hook, vendor, device, PCI_ANY_ID, 0, hook)
1897 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1898 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1899 hook, vendor, device, PCI_ANY_ID, 0, hook)
1900 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1902 hook, vendor, device, PCI_ANY_ID, 0, hook)
1903 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1904 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1905 hook, vendor, device, PCI_ANY_ID, 0, hook)
1906 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1907 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1908 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1909 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1910 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1911 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1912 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1914 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1915 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1916 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1917 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1919 #ifdef CONFIG_PCI_QUIRKS
1920 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1922 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1923 struct pci_dev *dev) { }
1926 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1927 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1928 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1929 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1930 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1932 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1934 extern int pci_pci_problems;
1935 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1936 #define PCIPCI_TRITON 2
1937 #define PCIPCI_NATOMA 4
1938 #define PCIPCI_VIAETBF 8
1939 #define PCIPCI_VSFX 16
1940 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1941 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1943 extern unsigned long pci_cardbus_io_size;
1944 extern unsigned long pci_cardbus_mem_size;
1945 extern u8 pci_dfl_cache_line_size;
1946 extern u8 pci_cache_line_size;
1948 extern unsigned long pci_hotplug_io_size;
1949 extern unsigned long pci_hotplug_mem_size;
1950 extern unsigned long pci_hotplug_bus_size;
1952 /* Architecture-specific versions may override these (weak) */
1953 void pcibios_disable_device(struct pci_dev *dev);
1954 void pcibios_set_master(struct pci_dev *dev);
1955 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1956 enum pcie_reset_state state);
1957 int pcibios_add_device(struct pci_dev *dev);
1958 void pcibios_release_device(struct pci_dev *dev);
1959 void pcibios_penalize_isa_irq(int irq, int active);
1960 int pcibios_alloc_irq(struct pci_dev *dev);
1961 void pcibios_free_irq(struct pci_dev *dev);
1962 resource_size_t pcibios_default_alignment(void);
1964 #ifdef CONFIG_HIBERNATE_CALLBACKS
1965 extern struct dev_pm_ops pcibios_pm_ops;
1968 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1969 void __init pci_mmcfg_early_init(void);
1970 void __init pci_mmcfg_late_init(void);
1972 static inline void pci_mmcfg_early_init(void) { }
1973 static inline void pci_mmcfg_late_init(void) { }
1976 int pci_ext_cfg_avail(void);
1978 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1979 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1981 #ifdef CONFIG_PCI_IOV
1982 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1983 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1985 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1986 void pci_disable_sriov(struct pci_dev *dev);
1987 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1988 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1989 int pci_num_vf(struct pci_dev *dev);
1990 int pci_vfs_assigned(struct pci_dev *dev);
1991 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1992 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1993 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1994 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1995 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1997 /* Arch may override these (weak) */
1998 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1999 int pcibios_sriov_disable(struct pci_dev *pdev);
2000 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2002 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2006 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2010 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2012 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2016 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2018 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2019 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2020 static inline int pci_vfs_assigned(struct pci_dev *dev)
2022 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2024 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2026 #define pci_sriov_configure_simple NULL
2027 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2029 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2032 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2033 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2034 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2038 * pci_pcie_cap - get the saved PCIe capability offset
2041 * PCIe capability offset is calculated at PCI device initialization
2042 * time and saved in the data structure. This function returns saved
2043 * PCIe capability offset. Using this instead of pci_find_capability()
2044 * reduces unnecessary search in the PCI configuration space. If you
2045 * need to calculate PCIe capability offset from raw device for some
2046 * reasons, please use pci_find_capability() instead.
2048 static inline int pci_pcie_cap(struct pci_dev *dev)
2050 return dev->pcie_cap;
2054 * pci_is_pcie - check if the PCI device is PCI Express capable
2057 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2059 static inline bool pci_is_pcie(struct pci_dev *dev)
2061 return pci_pcie_cap(dev);
2065 * pcie_caps_reg - get the PCIe Capabilities Register
2068 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2070 return dev->pcie_flags_reg;
2074 * pci_pcie_type - get the PCIe device/port type
2077 static inline int pci_pcie_type(const struct pci_dev *dev)
2079 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2082 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2085 if (!pci_is_pcie(dev))
2087 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2089 if (!dev->bus->self)
2091 dev = dev->bus->self;
2096 void pci_request_acs(void);
2097 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2098 bool pci_acs_path_enabled(struct pci_dev *start,
2099 struct pci_dev *end, u16 acs_flags);
2100 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2102 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2103 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2105 /* Large Resource Data Type Tag Item Names */
2106 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2107 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2108 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2110 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2111 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2112 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2114 /* Small Resource Data Type Tag Item Names */
2115 #define PCI_VPD_STIN_END 0x0f /* End */
2117 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2119 #define PCI_VPD_SRDT_TIN_MASK 0x78
2120 #define PCI_VPD_SRDT_LEN_MASK 0x07
2121 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2123 #define PCI_VPD_LRDT_TAG_SIZE 3
2124 #define PCI_VPD_SRDT_TAG_SIZE 1
2126 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2128 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2129 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2130 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2131 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2134 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2135 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2137 * Returns the extracted Large Resource Data Type length.
2139 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2141 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2145 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2146 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2148 * Returns the extracted Large Resource Data Type Tag item.
2150 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2152 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2156 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2157 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2159 * Returns the extracted Small Resource Data Type length.
2161 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2163 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2167 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2168 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2170 * Returns the extracted Small Resource Data Type Tag Item.
2172 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2174 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2178 * pci_vpd_info_field_size - Extracts the information field length
2179 * @lrdt: Pointer to the beginning of an information field header
2181 * Returns the extracted information field length.
2183 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2185 return info_field[2];
2189 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2190 * @buf: Pointer to buffered vpd data
2191 * @off: The offset into the buffer at which to begin the search
2192 * @len: The length of the vpd buffer
2193 * @rdt: The Resource Data Type to search for
2195 * Returns the index where the Resource Data Type was found or
2196 * -ENOENT otherwise.
2198 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2201 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2202 * @buf: Pointer to buffered vpd data
2203 * @off: The offset into the buffer at which to begin the search
2204 * @len: The length of the buffer area, relative to off, in which to search
2205 * @kw: The keyword to search for
2207 * Returns the index where the information field keyword was found or
2208 * -ENOENT otherwise.
2210 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2211 unsigned int len, const char *kw);
2213 /* PCI <-> OF binding helpers */
2217 void pci_set_of_node(struct pci_dev *dev);
2218 void pci_release_of_node(struct pci_dev *dev);
2219 void pci_set_bus_of_node(struct pci_bus *bus);
2220 void pci_release_bus_of_node(struct pci_bus *bus);
2221 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2222 int pci_parse_request_of_pci_ranges(struct device *dev,
2223 struct list_head *resources,
2224 struct resource **bus_range);
2226 /* Arch may override this (weak) */
2227 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2229 #else /* CONFIG_OF */
2230 static inline void pci_set_of_node(struct pci_dev *dev) { }
2231 static inline void pci_release_of_node(struct pci_dev *dev) { }
2232 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2233 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2234 static inline struct irq_domain *
2235 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2236 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2237 struct list_head *resources,
2238 struct resource **bus_range)
2242 #endif /* CONFIG_OF */
2244 static inline struct device_node *
2245 pci_device_to_OF_node(const struct pci_dev *pdev)
2247 return pdev ? pdev->dev.of_node : NULL;
2250 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2252 return bus ? bus->dev.of_node : NULL;
2256 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2259 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2261 static inline struct irq_domain *
2262 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2266 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2268 return pdev->dev.archdata.edev;
2272 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2273 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2274 int pci_for_each_dma_alias(struct pci_dev *pdev,
2275 int (*fn)(struct pci_dev *pdev,
2276 u16 alias, void *data), void *data);
2278 /* Helper functions for operation of device flag */
2279 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2281 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2283 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2285 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2287 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2289 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2293 * pci_ari_enabled - query ARI forwarding status
2296 * Returns true if ARI forwarding is enabled.
2298 static inline bool pci_ari_enabled(struct pci_bus *bus)
2300 return bus->self && bus->self->ari_enabled;
2304 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2305 * @pdev: PCI device to check
2307 * Walk upwards from @pdev and check for each encountered bridge if it's part
2308 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2309 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2311 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2313 struct pci_dev *parent = pdev;
2315 if (pdev->is_thunderbolt)
2318 while ((parent = pci_upstream_bridge(parent)))
2319 if (parent->is_thunderbolt)
2325 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2326 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2329 /* Provide the legacy pci_dma_* API */
2330 #include <linux/pci-dma-compat.h>
2332 #define pci_printk(level, pdev, fmt, arg...) \
2333 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2335 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2336 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2337 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2338 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2339 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2340 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2341 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2342 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2344 #endif /* LINUX_PCI_H */