2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
51 static int ahci_skip_host_reset;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
136 &dev_attr_em_message_supported,
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
144 &dev_attr_ncq_prio_enable,
147 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
149 struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
157 .freeze = ahci_freeze,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
172 .set_lpm = ahci_set_lpm,
173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
177 .transmit_led_message = ahci_transmit_led_message,
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
185 EXPORT_SYMBOL_GPL(ahci_ops);
187 struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
191 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
193 static bool ahci_em_messages __read_mostly = true;
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204 static void ahci_enable_ahci(void __iomem *mmio)
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
217 for (i = 0; i < 5; i++) {
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
237 static int ahci_rpm_get_port(struct ata_port *ap)
239 return pm_runtime_get_sync(ap->dev);
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
249 static void ahci_rpm_put_port(struct ata_port *ap)
251 pm_runtime_put(ap->dev);
254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
261 return sprintf(buf, "%x\n", hpriv->cap);
264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
271 return sprintf(buf, "%x\n", hpriv->cap2);
274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
281 return sprintf(buf, "%x\n", hpriv->version);
284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
332 count = hpriv->em_buf_sz;
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
432 * If inconsistent, config values are fixed up by this function.
434 * If it is not set already this function sets hpriv->start_engine to
440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 hpriv->saved_cap2 = cap2 = 0;
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
516 hpriv->saved_port_map = port_map;
519 if (hpriv->mask_port_map) {
520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
526 /* cross check port_map and cap.n_ports */
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
537 if (map_ports > ahci_nr_ports(cap)) {
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
547 port_map = (1 << ahci_nr_ports(cap)) - 1;
548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
554 /* record values to use during operation */
557 hpriv->version = readl(mmio + HOST_VERSION);
558 hpriv->port_map = port_map;
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
563 if (!hpriv->stop_engine)
564 hpriv->stop_engine = ahci_stop_engine;
566 if (!hpriv->irq_handler)
567 hpriv->irq_handler = ahci_single_level_irq_intr;
569 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
575 * Restore initial config stored by ahci_save_initial_config().
580 static void ahci_restore_initial_config(struct ata_host *host)
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = hpriv->mmio;
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 if (hpriv->saved_cap2)
587 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
594 static const int offset[] = {
595 [SCR_STATUS] = PORT_SCR_STAT,
596 [SCR_CONTROL] = PORT_SCR_CTL,
597 [SCR_ERROR] = PORT_SCR_ERR,
598 [SCR_ACTIVE] = PORT_SCR_ACT,
599 [SCR_NOTIFICATION] = PORT_SCR_NTF,
601 struct ahci_host_priv *hpriv = ap->host->private_data;
603 if (sc_reg < ARRAY_SIZE(offset) &&
604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 return offset[sc_reg];
609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
611 void __iomem *port_mmio = ahci_port_base(link->ap);
612 int offset = ahci_scr_offset(link->ap, sc_reg);
615 *val = readl(port_mmio + offset);
621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
623 void __iomem *port_mmio = ahci_port_base(link->ap);
624 int offset = ahci_scr_offset(link->ap, sc_reg);
627 writel(val, port_mmio + offset);
633 void ahci_start_engine(struct ata_port *ap)
635 void __iomem *port_mmio = ahci_port_base(ap);
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp |= PORT_CMD_START;
641 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD); /* flush */
644 EXPORT_SYMBOL_GPL(ahci_start_engine);
646 int ahci_stop_engine(struct ata_port *ap)
648 void __iomem *port_mmio = ahci_port_base(ap);
649 struct ahci_host_priv *hpriv = ap->host->private_data;
653 * On some controllers, stopping a port's DMA engine while the port
654 * is in ALPM state (partial or slumber) results in failures on
655 * subsequent DMA engine starts. For those controllers, put the
656 * port back in active state before stopping its DMA engine.
658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
665 tmp = readl(port_mmio + PORT_CMD);
667 /* check if the HBA is idle */
668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
671 /* setting HBA to idle */
672 tmp &= ~PORT_CMD_START;
673 writel(tmp, port_mmio + PORT_CMD);
675 /* wait for engine to stop. This could be as long as 500 msec */
676 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
677 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
678 if (tmp & PORT_CMD_LIST_ON)
683 EXPORT_SYMBOL_GPL(ahci_stop_engine);
685 void ahci_start_fis_rx(struct ata_port *ap)
687 void __iomem *port_mmio = ahci_port_base(ap);
688 struct ahci_host_priv *hpriv = ap->host->private_data;
689 struct ahci_port_priv *pp = ap->private_data;
692 /* set FIS registers */
693 if (hpriv->cap & HOST_CAP_64)
694 writel((pp->cmd_slot_dma >> 16) >> 16,
695 port_mmio + PORT_LST_ADDR_HI);
696 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
698 if (hpriv->cap & HOST_CAP_64)
699 writel((pp->rx_fis_dma >> 16) >> 16,
700 port_mmio + PORT_FIS_ADDR_HI);
701 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
703 /* enable FIS reception */
704 tmp = readl(port_mmio + PORT_CMD);
705 tmp |= PORT_CMD_FIS_RX;
706 writel(tmp, port_mmio + PORT_CMD);
709 readl(port_mmio + PORT_CMD);
711 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
713 static int ahci_stop_fis_rx(struct ata_port *ap)
715 void __iomem *port_mmio = ahci_port_base(ap);
718 /* disable FIS reception */
719 tmp = readl(port_mmio + PORT_CMD);
720 tmp &= ~PORT_CMD_FIS_RX;
721 writel(tmp, port_mmio + PORT_CMD);
723 /* wait for completion, spec says 500ms, give it 1000 */
724 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
725 PORT_CMD_FIS_ON, 10, 1000);
726 if (tmp & PORT_CMD_FIS_ON)
732 static void ahci_power_up(struct ata_port *ap)
734 struct ahci_host_priv *hpriv = ap->host->private_data;
735 void __iomem *port_mmio = ahci_port_base(ap);
738 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
741 if (hpriv->cap & HOST_CAP_SSS) {
742 cmd |= PORT_CMD_SPIN_UP;
743 writel(cmd, port_mmio + PORT_CMD);
747 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
750 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
753 struct ata_port *ap = link->ap;
754 struct ahci_host_priv *hpriv = ap->host->private_data;
755 struct ahci_port_priv *pp = ap->private_data;
756 void __iomem *port_mmio = ahci_port_base(ap);
758 if (policy != ATA_LPM_MAX_POWER) {
759 /* wakeup flag only applies to the max power policy */
760 hints &= ~ATA_LPM_WAKE_ONLY;
763 * Disable interrupts on Phy Ready. This keeps us from
764 * getting woken up due to spurious phy ready
767 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
768 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
770 sata_link_scr_lpm(link, policy, false);
773 if (hpriv->cap & HOST_CAP_ALPM) {
774 u32 cmd = readl(port_mmio + PORT_CMD);
776 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
777 if (!(hints & ATA_LPM_WAKE_ONLY))
778 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
779 cmd |= PORT_CMD_ICC_ACTIVE;
781 writel(cmd, port_mmio + PORT_CMD);
782 readl(port_mmio + PORT_CMD);
784 /* wait 10ms to be sure we've come out of LPM state */
787 if (hints & ATA_LPM_WAKE_ONLY)
790 cmd |= PORT_CMD_ALPE;
791 if (policy == ATA_LPM_MIN_POWER)
794 /* write out new cmd value */
795 writel(cmd, port_mmio + PORT_CMD);
799 /* set aggressive device sleep */
800 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
801 (hpriv->cap2 & HOST_CAP2_SADM) &&
802 (link->device->flags & ATA_DFLAG_DEVSLP)) {
803 if (policy == ATA_LPM_MIN_POWER)
804 ahci_set_aggressive_devslp(ap, true);
806 ahci_set_aggressive_devslp(ap, false);
809 if (policy == ATA_LPM_MAX_POWER) {
810 sata_link_scr_lpm(link, policy, false);
812 /* turn PHYRDY IRQ back on */
813 pp->intr_mask |= PORT_IRQ_PHYRDY;
814 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
821 static void ahci_power_down(struct ata_port *ap)
823 struct ahci_host_priv *hpriv = ap->host->private_data;
824 void __iomem *port_mmio = ahci_port_base(ap);
827 if (!(hpriv->cap & HOST_CAP_SSS))
830 /* put device into listen mode, first set PxSCTL.DET to 0 */
831 scontrol = readl(port_mmio + PORT_SCR_CTL);
833 writel(scontrol, port_mmio + PORT_SCR_CTL);
835 /* then set PxCMD.SUD to 0 */
836 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
837 cmd &= ~PORT_CMD_SPIN_UP;
838 writel(cmd, port_mmio + PORT_CMD);
842 static void ahci_start_port(struct ata_port *ap)
844 struct ahci_host_priv *hpriv = ap->host->private_data;
845 struct ahci_port_priv *pp = ap->private_data;
846 struct ata_link *link;
847 struct ahci_em_priv *emp;
851 /* enable FIS reception */
852 ahci_start_fis_rx(ap);
855 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
856 hpriv->start_engine(ap);
859 if (ap->flags & ATA_FLAG_EM) {
860 ata_for_each_link(link, ap, EDGE) {
861 emp = &pp->em_priv[link->pmp];
863 /* EM Transmit bit maybe busy during init */
864 for (i = 0; i < EM_MAX_RETRY; i++) {
865 rc = ap->ops->transmit_led_message(ap,
869 * If busy, give a breather but do not
870 * release EH ownership by using msleep()
871 * instead of ata_msleep(). EM Transmit
872 * bit is busy for the whole host and
873 * releasing ownership will cause other
874 * ports to fail the same way.
884 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
885 ata_for_each_link(link, ap, EDGE)
886 ahci_init_sw_activity(link);
890 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
893 struct ahci_host_priv *hpriv = ap->host->private_data;
896 rc = hpriv->stop_engine(ap);
898 *emsg = "failed to stop engine";
902 /* disable FIS reception */
903 rc = ahci_stop_fis_rx(ap);
905 *emsg = "failed stop FIS RX";
912 int ahci_reset_controller(struct ata_host *host)
914 struct ahci_host_priv *hpriv = host->private_data;
915 void __iomem *mmio = hpriv->mmio;
918 /* we must be in AHCI mode, before using anything
919 * AHCI-specific, such as HOST_RESET.
921 ahci_enable_ahci(mmio);
923 /* global controller reset */
924 if (!ahci_skip_host_reset) {
925 tmp = readl(mmio + HOST_CTL);
926 if ((tmp & HOST_RESET) == 0) {
927 writel(tmp | HOST_RESET, mmio + HOST_CTL);
928 readl(mmio + HOST_CTL); /* flush */
932 * to perform host reset, OS should set HOST_RESET
933 * and poll until this bit is read to be "0".
934 * reset must complete within 1 second, or
935 * the hardware should be considered fried.
937 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
938 HOST_RESET, 10, 1000);
940 if (tmp & HOST_RESET) {
941 dev_err(host->dev, "controller reset failed (0x%x)\n",
946 /* turn on AHCI mode */
947 ahci_enable_ahci(mmio);
949 /* Some registers might be cleared on reset. Restore
952 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
953 ahci_restore_initial_config(host);
955 dev_info(host->dev, "skipping global host reset\n");
959 EXPORT_SYMBOL_GPL(ahci_reset_controller);
961 static void ahci_sw_activity(struct ata_link *link)
963 struct ata_port *ap = link->ap;
964 struct ahci_port_priv *pp = ap->private_data;
965 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
967 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
971 if (!timer_pending(&emp->timer))
972 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
975 static void ahci_sw_activity_blink(unsigned long arg)
977 struct ata_link *link = (struct ata_link *)arg;
978 struct ata_port *ap = link->ap;
979 struct ahci_port_priv *pp = ap->private_data;
980 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
981 unsigned long led_message = emp->led_state;
982 u32 activity_led_state;
985 led_message &= EM_MSG_LED_VALUE;
986 led_message |= ap->port_no | (link->pmp << 8);
988 /* check to see if we've had activity. If so,
989 * toggle state of LED and reset timer. If not,
990 * turn LED to desired idle state.
992 spin_lock_irqsave(ap->lock, flags);
993 if (emp->saved_activity != emp->activity) {
994 emp->saved_activity = emp->activity;
995 /* get the current LED state */
996 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
998 if (activity_led_state)
999 activity_led_state = 0;
1001 activity_led_state = 1;
1003 /* clear old state */
1004 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1007 led_message |= (activity_led_state << 16);
1008 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1010 /* switch to idle */
1011 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1012 if (emp->blink_policy == BLINK_OFF)
1013 led_message |= (1 << 16);
1015 spin_unlock_irqrestore(ap->lock, flags);
1016 ap->ops->transmit_led_message(ap, led_message, 4);
1019 static void ahci_init_sw_activity(struct ata_link *link)
1021 struct ata_port *ap = link->ap;
1022 struct ahci_port_priv *pp = ap->private_data;
1023 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1025 /* init activity stats, setup timer */
1026 emp->saved_activity = emp->activity = 0;
1027 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1029 /* check our blink policy and set flag for link if it's enabled */
1030 if (emp->blink_policy)
1031 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1034 int ahci_reset_em(struct ata_host *host)
1036 struct ahci_host_priv *hpriv = host->private_data;
1037 void __iomem *mmio = hpriv->mmio;
1040 em_ctl = readl(mmio + HOST_EM_CTL);
1041 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1044 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1047 EXPORT_SYMBOL_GPL(ahci_reset_em);
1049 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1052 struct ahci_host_priv *hpriv = ap->host->private_data;
1053 struct ahci_port_priv *pp = ap->private_data;
1054 void __iomem *mmio = hpriv->mmio;
1056 u32 message[] = {0, 0};
1057 unsigned long flags;
1059 struct ahci_em_priv *emp;
1061 /* get the slot number from the message */
1062 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1063 if (pmp < EM_MAX_SLOTS)
1064 emp = &pp->em_priv[pmp];
1068 ahci_rpm_get_port(ap);
1069 spin_lock_irqsave(ap->lock, flags);
1072 * if we are still busy transmitting a previous message,
1075 em_ctl = readl(mmio + HOST_EM_CTL);
1076 if (em_ctl & EM_CTL_TM) {
1077 spin_unlock_irqrestore(ap->lock, flags);
1078 ahci_rpm_put_port(ap);
1082 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1084 * create message header - this is all zero except for
1085 * the message size, which is 4 bytes.
1087 message[0] |= (4 << 8);
1089 /* ignore 0:4 of byte zero, fill in port info yourself */
1090 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1092 /* write message to EM_LOC */
1093 writel(message[0], mmio + hpriv->em_loc);
1094 writel(message[1], mmio + hpriv->em_loc+4);
1097 * tell hardware to transmit the message
1099 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1102 /* save off new led state for port/slot */
1103 emp->led_state = state;
1105 spin_unlock_irqrestore(ap->lock, flags);
1106 ahci_rpm_put_port(ap);
1111 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1113 struct ahci_port_priv *pp = ap->private_data;
1114 struct ata_link *link;
1115 struct ahci_em_priv *emp;
1118 ata_for_each_link(link, ap, EDGE) {
1119 emp = &pp->em_priv[link->pmp];
1120 rc += sprintf(buf, "%lx\n", emp->led_state);
1125 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1130 struct ahci_port_priv *pp = ap->private_data;
1131 struct ahci_em_priv *emp;
1133 if (kstrtouint(buf, 0, &state) < 0)
1136 /* get the slot number from the message */
1137 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1138 if (pmp < EM_MAX_SLOTS) {
1139 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1140 emp = &pp->em_priv[pmp];
1145 /* mask off the activity bits if we are in sw_activity
1146 * mode, user should turn off sw_activity before setting
1147 * activity led through em_message
1149 if (emp->blink_policy)
1150 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1152 return ap->ops->transmit_led_message(ap, state, size);
1155 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1157 struct ata_link *link = dev->link;
1158 struct ata_port *ap = link->ap;
1159 struct ahci_port_priv *pp = ap->private_data;
1160 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1161 u32 port_led_state = emp->led_state;
1163 /* save the desired Activity LED behavior */
1166 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1168 /* set the LED to OFF */
1169 port_led_state &= EM_MSG_LED_VALUE_OFF;
1170 port_led_state |= (ap->port_no | (link->pmp << 8));
1171 ap->ops->transmit_led_message(ap, port_led_state, 4);
1173 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1174 if (val == BLINK_OFF) {
1175 /* set LED to ON for idle */
1176 port_led_state &= EM_MSG_LED_VALUE_OFF;
1177 port_led_state |= (ap->port_no | (link->pmp << 8));
1178 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1179 ap->ops->transmit_led_message(ap, port_led_state, 4);
1182 emp->blink_policy = val;
1186 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1188 struct ata_link *link = dev->link;
1189 struct ata_port *ap = link->ap;
1190 struct ahci_port_priv *pp = ap->private_data;
1191 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1193 /* display the saved value of activity behavior for this
1196 return sprintf(buf, "%d\n", emp->blink_policy);
1199 static void ahci_port_clear_pending_irq(struct ata_port *ap)
1201 struct ahci_host_priv *hpriv = ap->host->private_data;
1202 void __iomem *port_mmio = ahci_port_base(ap);
1206 tmp = readl(port_mmio + PORT_SCR_ERR);
1207 dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
1208 writel(tmp, port_mmio + PORT_SCR_ERR);
1210 /* clear port IRQ */
1211 tmp = readl(port_mmio + PORT_IRQ_STAT);
1212 dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1214 writel(tmp, port_mmio + PORT_IRQ_STAT);
1216 writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
1219 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1220 int port_no, void __iomem *mmio,
1221 void __iomem *port_mmio)
1223 struct ahci_host_priv *hpriv = ap->host->private_data;
1224 const char *emsg = NULL;
1228 /* make sure port is not active */
1229 rc = ahci_deinit_port(ap, &emsg);
1231 dev_warn(dev, "%s (%d)\n", emsg, rc);
1233 ahci_port_clear_pending_irq(ap);
1235 /* mark esata ports */
1236 tmp = readl(port_mmio + PORT_CMD);
1237 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1238 ap->pflags |= ATA_PFLAG_EXTERNAL;
1241 void ahci_init_controller(struct ata_host *host)
1243 struct ahci_host_priv *hpriv = host->private_data;
1244 void __iomem *mmio = hpriv->mmio;
1246 void __iomem *port_mmio;
1249 for (i = 0; i < host->n_ports; i++) {
1250 struct ata_port *ap = host->ports[i];
1252 port_mmio = ahci_port_base(ap);
1253 if (ata_port_is_dummy(ap))
1256 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1259 tmp = readl(mmio + HOST_CTL);
1260 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1261 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1262 tmp = readl(mmio + HOST_CTL);
1263 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1265 EXPORT_SYMBOL_GPL(ahci_init_controller);
1267 static void ahci_dev_config(struct ata_device *dev)
1269 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1271 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1272 dev->max_sectors = 255;
1274 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1278 unsigned int ahci_dev_classify(struct ata_port *ap)
1280 void __iomem *port_mmio = ahci_port_base(ap);
1281 struct ata_taskfile tf;
1284 tmp = readl(port_mmio + PORT_SIG);
1285 tf.lbah = (tmp >> 24) & 0xff;
1286 tf.lbam = (tmp >> 16) & 0xff;
1287 tf.lbal = (tmp >> 8) & 0xff;
1288 tf.nsect = (tmp) & 0xff;
1290 return ata_dev_classify(&tf);
1292 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1294 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1297 dma_addr_t cmd_tbl_dma;
1299 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1301 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1302 pp->cmd_slot[tag].status = 0;
1303 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1304 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1306 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1308 int ahci_kick_engine(struct ata_port *ap)
1310 void __iomem *port_mmio = ahci_port_base(ap);
1311 struct ahci_host_priv *hpriv = ap->host->private_data;
1312 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1317 rc = hpriv->stop_engine(ap);
1322 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1324 busy = status & (ATA_BUSY | ATA_DRQ);
1325 if (!busy && !sata_pmp_attached(ap)) {
1330 if (!(hpriv->cap & HOST_CAP_CLO)) {
1336 tmp = readl(port_mmio + PORT_CMD);
1337 tmp |= PORT_CMD_CLO;
1338 writel(tmp, port_mmio + PORT_CMD);
1341 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1342 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1343 if (tmp & PORT_CMD_CLO)
1346 /* restart engine */
1348 hpriv->start_engine(ap);
1351 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1353 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1354 struct ata_taskfile *tf, int is_cmd, u16 flags,
1355 unsigned long timeout_msec)
1357 const u32 cmd_fis_len = 5; /* five dwords */
1358 struct ahci_port_priv *pp = ap->private_data;
1359 void __iomem *port_mmio = ahci_port_base(ap);
1360 u8 *fis = pp->cmd_tbl;
1363 /* prep the command */
1364 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1365 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1367 /* set port value for softreset of Port Multiplier */
1368 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1369 tmp = readl(port_mmio + PORT_FBS);
1370 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1371 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1372 writel(tmp, port_mmio + PORT_FBS);
1373 pp->fbs_last_dev = pmp;
1377 writel(1, port_mmio + PORT_CMD_ISSUE);
1380 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1381 0x1, 0x1, 1, timeout_msec);
1383 ahci_kick_engine(ap);
1387 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1392 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1393 int pmp, unsigned long deadline,
1394 int (*check_ready)(struct ata_link *link))
1396 struct ata_port *ap = link->ap;
1397 struct ahci_host_priv *hpriv = ap->host->private_data;
1398 struct ahci_port_priv *pp = ap->private_data;
1399 const char *reason = NULL;
1400 unsigned long now, msecs;
1401 struct ata_taskfile tf;
1402 bool fbs_disabled = false;
1407 /* prepare for SRST (AHCI-1.1 10.4.1) */
1408 rc = ahci_kick_engine(ap);
1409 if (rc && rc != -EOPNOTSUPP)
1410 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1413 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1414 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1415 * that is attached to port multiplier.
1417 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1418 ahci_disable_fbs(ap);
1419 fbs_disabled = true;
1422 ata_tf_init(link->device, &tf);
1424 /* issue the first H2D Register FIS */
1427 if (time_after(deadline, now))
1428 msecs = jiffies_to_msecs(deadline - now);
1431 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1432 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1434 reason = "1st FIS failed";
1438 /* spec says at least 5us, but be generous and sleep for 1ms */
1441 /* issue the second H2D Register FIS */
1442 tf.ctl &= ~ATA_SRST;
1443 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1445 /* wait for link to become ready */
1446 rc = ata_wait_after_reset(link, deadline, check_ready);
1447 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1449 * Workaround for cases where link online status can't
1450 * be trusted. Treat device readiness timeout as link
1453 ata_link_info(link, "device not ready, treating as offline\n");
1454 *class = ATA_DEV_NONE;
1456 /* link occupied, -ENODEV too is an error */
1457 reason = "device not ready";
1460 *class = ahci_dev_classify(ap);
1462 /* re-enable FBS if disabled before */
1464 ahci_enable_fbs(ap);
1466 DPRINTK("EXIT, class=%u\n", *class);
1470 ata_link_err(link, "softreset failed (%s)\n", reason);
1474 int ahci_check_ready(struct ata_link *link)
1476 void __iomem *port_mmio = ahci_port_base(link->ap);
1477 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1479 return ata_check_ready(status);
1481 EXPORT_SYMBOL_GPL(ahci_check_ready);
1483 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1484 unsigned long deadline)
1486 int pmp = sata_srst_pmp(link);
1490 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1492 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1494 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1496 void __iomem *port_mmio = ahci_port_base(link->ap);
1497 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1498 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1501 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1502 * which can save timeout delay.
1504 if (irq_status & PORT_IRQ_BAD_PMP)
1507 return ata_check_ready(status);
1510 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1511 unsigned long deadline)
1513 struct ata_port *ap = link->ap;
1514 void __iomem *port_mmio = ahci_port_base(ap);
1515 int pmp = sata_srst_pmp(link);
1521 rc = ahci_do_softreset(link, class, pmp, deadline,
1522 ahci_bad_pmp_check_ready);
1525 * Soft reset fails with IPMS set when PMP is enabled but
1526 * SATA HDD/ODD is connected to SATA port, do soft reset
1530 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1531 if (irq_sts & PORT_IRQ_BAD_PMP) {
1533 "applying PMP SRST workaround "
1535 rc = ahci_do_softreset(link, class, 0, deadline,
1543 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1544 unsigned long deadline, bool *online)
1546 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1547 struct ata_port *ap = link->ap;
1548 struct ahci_port_priv *pp = ap->private_data;
1549 struct ahci_host_priv *hpriv = ap->host->private_data;
1550 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1551 struct ata_taskfile tf;
1556 hpriv->stop_engine(ap);
1558 /* clear D2H reception area to properly wait for D2H FIS */
1559 ata_tf_init(link->device, &tf);
1560 tf.command = ATA_BUSY;
1561 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1563 ahci_port_clear_pending_irq(ap);
1565 rc = sata_link_hardreset(link, timing, deadline, online,
1568 hpriv->start_engine(ap);
1571 *class = ahci_dev_classify(ap);
1573 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1576 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1578 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1579 unsigned long deadline)
1583 return ahci_do_hardreset(link, class, deadline, &online);
1586 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1588 struct ata_port *ap = link->ap;
1589 void __iomem *port_mmio = ahci_port_base(ap);
1592 ata_std_postreset(link, class);
1594 /* Make sure port's ATAPI bit is set appropriately */
1595 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1596 if (*class == ATA_DEV_ATAPI)
1597 new_tmp |= PORT_CMD_ATAPI;
1599 new_tmp &= ~PORT_CMD_ATAPI;
1600 if (new_tmp != tmp) {
1601 writel(new_tmp, port_mmio + PORT_CMD);
1602 readl(port_mmio + PORT_CMD); /* flush */
1606 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1608 struct scatterlist *sg;
1609 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1615 * Next, the S/G list.
1617 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1618 dma_addr_t addr = sg_dma_address(sg);
1619 u32 sg_len = sg_dma_len(sg);
1621 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1622 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1623 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1629 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1631 struct ata_port *ap = qc->ap;
1632 struct ahci_port_priv *pp = ap->private_data;
1634 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1635 return ata_std_qc_defer(qc);
1637 return sata_pmp_qc_defer_cmd_switch(qc);
1640 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1642 struct ata_port *ap = qc->ap;
1643 struct ahci_port_priv *pp = ap->private_data;
1644 int is_atapi = ata_is_atapi(qc->tf.protocol);
1647 const u32 cmd_fis_len = 5; /* five dwords */
1648 unsigned int n_elem;
1651 * Fill in command table information. First, the header,
1652 * a SATA Register - Host to Device command FIS.
1654 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1656 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1658 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1659 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1663 if (qc->flags & ATA_QCFLAG_DMAMAP)
1664 n_elem = ahci_fill_sg(qc, cmd_tbl);
1667 * Fill in command slot information.
1669 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1670 if (qc->tf.flags & ATA_TFLAG_WRITE)
1671 opts |= AHCI_CMD_WRITE;
1673 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1675 ahci_fill_cmd_slot(pp, qc->tag, opts);
1680 static void ahci_fbs_dec_intr(struct ata_port *ap)
1682 struct ahci_port_priv *pp = ap->private_data;
1683 void __iomem *port_mmio = ahci_port_base(ap);
1684 u32 fbs = readl(port_mmio + PORT_FBS);
1688 BUG_ON(!pp->fbs_enabled);
1690 /* time to wait for DEC is not specified by AHCI spec,
1691 * add a retry loop for safety.
1693 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1694 fbs = readl(port_mmio + PORT_FBS);
1695 while ((fbs & PORT_FBS_DEC) && retries--) {
1697 fbs = readl(port_mmio + PORT_FBS);
1700 if (fbs & PORT_FBS_DEC)
1701 dev_err(ap->host->dev, "failed to clear device error\n");
1704 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1706 struct ahci_host_priv *hpriv = ap->host->private_data;
1707 struct ahci_port_priv *pp = ap->private_data;
1708 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1709 struct ata_link *link = NULL;
1710 struct ata_queued_cmd *active_qc;
1711 struct ata_eh_info *active_ehi;
1712 bool fbs_need_dec = false;
1715 /* determine active link with error */
1716 if (pp->fbs_enabled) {
1717 void __iomem *port_mmio = ahci_port_base(ap);
1718 u32 fbs = readl(port_mmio + PORT_FBS);
1719 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1721 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1722 link = &ap->pmp_link[pmp];
1723 fbs_need_dec = true;
1727 ata_for_each_link(link, ap, EDGE)
1728 if (ata_link_active(link))
1734 active_qc = ata_qc_from_tag(ap, link->active_tag);
1735 active_ehi = &link->eh_info;
1737 /* record irq stat */
1738 ata_ehi_clear_desc(host_ehi);
1739 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1741 /* AHCI needs SError cleared; otherwise, it might lock up */
1742 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1743 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1744 host_ehi->serror |= serror;
1746 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1747 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1748 irq_stat &= ~PORT_IRQ_IF_ERR;
1750 if (irq_stat & PORT_IRQ_TF_ERR) {
1751 /* If qc is active, charge it; otherwise, the active
1752 * link. There's no active qc on NCQ errors. It will
1753 * be determined by EH by reading log page 10h.
1756 active_qc->err_mask |= AC_ERR_DEV;
1758 active_ehi->err_mask |= AC_ERR_DEV;
1760 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1761 host_ehi->serror &= ~SERR_INTERNAL;
1764 if (irq_stat & PORT_IRQ_UNK_FIS) {
1765 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1767 active_ehi->err_mask |= AC_ERR_HSM;
1768 active_ehi->action |= ATA_EH_RESET;
1769 ata_ehi_push_desc(active_ehi,
1770 "unknown FIS %08x %08x %08x %08x" ,
1771 unk[0], unk[1], unk[2], unk[3]);
1774 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1775 active_ehi->err_mask |= AC_ERR_HSM;
1776 active_ehi->action |= ATA_EH_RESET;
1777 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1780 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1781 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1782 host_ehi->action |= ATA_EH_RESET;
1783 ata_ehi_push_desc(host_ehi, "host bus error");
1786 if (irq_stat & PORT_IRQ_IF_ERR) {
1788 active_ehi->err_mask |= AC_ERR_DEV;
1790 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1791 host_ehi->action |= ATA_EH_RESET;
1794 ata_ehi_push_desc(host_ehi, "interface fatal error");
1797 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1798 ata_ehi_hotplugged(host_ehi);
1799 ata_ehi_push_desc(host_ehi, "%s",
1800 irq_stat & PORT_IRQ_CONNECT ?
1801 "connection status changed" : "PHY RDY changed");
1804 /* okay, let's hand over to EH */
1806 if (irq_stat & PORT_IRQ_FREEZE)
1807 ata_port_freeze(ap);
1808 else if (fbs_need_dec) {
1809 ata_link_abort(link);
1810 ahci_fbs_dec_intr(ap);
1815 static void ahci_handle_port_interrupt(struct ata_port *ap,
1816 void __iomem *port_mmio, u32 status)
1818 struct ata_eh_info *ehi = &ap->link.eh_info;
1819 struct ahci_port_priv *pp = ap->private_data;
1820 struct ahci_host_priv *hpriv = ap->host->private_data;
1821 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1825 /* ignore BAD_PMP while resetting */
1826 if (unlikely(resetting))
1827 status &= ~PORT_IRQ_BAD_PMP;
1829 if (sata_lpm_ignore_phy_events(&ap->link)) {
1830 status &= ~PORT_IRQ_PHYRDY;
1831 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1834 if (unlikely(status & PORT_IRQ_ERROR)) {
1835 ahci_error_intr(ap, status);
1839 if (status & PORT_IRQ_SDB_FIS) {
1840 /* If SNotification is available, leave notification
1841 * handling to sata_async_notification(). If not,
1842 * emulate it by snooping SDB FIS RX area.
1844 * Snooping FIS RX area is probably cheaper than
1845 * poking SNotification but some constrollers which
1846 * implement SNotification, ICH9 for example, don't
1847 * store AN SDB FIS into receive area.
1849 if (hpriv->cap & HOST_CAP_SNTF)
1850 sata_async_notification(ap);
1852 /* If the 'N' bit in word 0 of the FIS is set,
1853 * we just received asynchronous notification.
1854 * Tell libata about it.
1856 * Lack of SNotification should not appear in
1857 * ahci 1.2, so the workaround is unnecessary
1858 * when FBS is enabled.
1860 if (pp->fbs_enabled)
1863 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1864 u32 f0 = le32_to_cpu(f[0]);
1866 sata_async_notification(ap);
1871 /* pp->active_link is not reliable once FBS is enabled, both
1872 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1873 * NCQ and non-NCQ commands may be in flight at the same time.
1875 if (pp->fbs_enabled) {
1876 if (ap->qc_active) {
1877 qc_active = readl(port_mmio + PORT_SCR_ACT);
1878 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1881 /* pp->active_link is valid iff any command is in flight */
1882 if (ap->qc_active && pp->active_link->sactive)
1883 qc_active = readl(port_mmio + PORT_SCR_ACT);
1885 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1889 rc = ata_qc_complete_multiple(ap, qc_active);
1891 /* while resetting, invalid completions are expected */
1892 if (unlikely(rc < 0 && !resetting)) {
1893 ehi->err_mask |= AC_ERR_HSM;
1894 ehi->action |= ATA_EH_RESET;
1895 ata_port_freeze(ap);
1899 static void ahci_port_intr(struct ata_port *ap)
1901 void __iomem *port_mmio = ahci_port_base(ap);
1904 status = readl(port_mmio + PORT_IRQ_STAT);
1905 writel(status, port_mmio + PORT_IRQ_STAT);
1907 ahci_handle_port_interrupt(ap, port_mmio, status);
1910 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1912 struct ata_port *ap = dev_instance;
1913 void __iomem *port_mmio = ahci_port_base(ap);
1916 status = readl(port_mmio + PORT_IRQ_STAT);
1917 writel(status, port_mmio + PORT_IRQ_STAT);
1919 spin_lock(ap->lock);
1920 ahci_handle_port_interrupt(ap, port_mmio, status);
1921 spin_unlock(ap->lock);
1926 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1928 unsigned int i, handled = 0;
1930 for (i = 0; i < host->n_ports; i++) {
1931 struct ata_port *ap;
1933 if (!(irq_masked & (1 << i)))
1936 ap = host->ports[i];
1940 if (ata_ratelimit())
1942 "interrupt on disabled port %u\n", i);
1950 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1952 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1954 struct ata_host *host = dev_instance;
1955 struct ahci_host_priv *hpriv;
1956 unsigned int rc = 0;
1958 u32 irq_stat, irq_masked;
1960 hpriv = host->private_data;
1963 /* sigh. 0xffffffff is a valid return from h/w */
1964 irq_stat = readl(mmio + HOST_IRQ_STAT);
1968 irq_masked = irq_stat & hpriv->port_map;
1970 spin_lock(&host->lock);
1972 rc = ahci_handle_port_intr(host, irq_masked);
1974 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1975 * it should be cleared after all the port events are cleared;
1976 * otherwise, it will raise a spurious interrupt after each
1977 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1980 * Also, use the unmasked value to clear interrupt as spurious
1981 * pending event on a dummy port might cause screaming IRQ.
1983 writel(irq_stat, mmio + HOST_IRQ_STAT);
1985 spin_unlock(&host->lock);
1987 return IRQ_RETVAL(rc);
1990 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1992 struct ata_port *ap = qc->ap;
1993 void __iomem *port_mmio = ahci_port_base(ap);
1994 struct ahci_port_priv *pp = ap->private_data;
1996 /* Keep track of the currently active link. It will be used
1997 * in completion path to determine whether NCQ phase is in
2000 pp->active_link = qc->dev->link;
2002 if (ata_is_ncq(qc->tf.protocol))
2003 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2005 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2006 u32 fbs = readl(port_mmio + PORT_FBS);
2007 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2008 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2009 writel(fbs, port_mmio + PORT_FBS);
2010 pp->fbs_last_dev = qc->dev->link->pmp;
2013 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2015 ahci_sw_activity(qc->dev->link);
2019 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2021 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2023 struct ahci_port_priv *pp = qc->ap->private_data;
2024 u8 *rx_fis = pp->rx_fis;
2026 if (pp->fbs_enabled)
2027 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2030 * After a successful execution of an ATA PIO data-in command,
2031 * the device doesn't send D2H Reg FIS to update the TF and
2032 * the host should take TF and E_Status from the preceding PIO
2035 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2036 !(qc->flags & ATA_QCFLAG_FAILED)) {
2037 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2038 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2040 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2045 static void ahci_freeze(struct ata_port *ap)
2047 void __iomem *port_mmio = ahci_port_base(ap);
2050 writel(0, port_mmio + PORT_IRQ_MASK);
2053 static void ahci_thaw(struct ata_port *ap)
2055 struct ahci_host_priv *hpriv = ap->host->private_data;
2056 void __iomem *mmio = hpriv->mmio;
2057 void __iomem *port_mmio = ahci_port_base(ap);
2059 struct ahci_port_priv *pp = ap->private_data;
2062 tmp = readl(port_mmio + PORT_IRQ_STAT);
2063 writel(tmp, port_mmio + PORT_IRQ_STAT);
2064 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2066 /* turn IRQ back on */
2067 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2070 void ahci_error_handler(struct ata_port *ap)
2072 struct ahci_host_priv *hpriv = ap->host->private_data;
2074 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2075 /* restart engine */
2076 hpriv->stop_engine(ap);
2077 hpriv->start_engine(ap);
2080 sata_pmp_error_handler(ap);
2082 if (!ata_dev_enabled(ap->link.device))
2083 hpriv->stop_engine(ap);
2085 EXPORT_SYMBOL_GPL(ahci_error_handler);
2087 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2089 struct ata_port *ap = qc->ap;
2091 /* make DMA engine forget about the failed command */
2092 if (qc->flags & ATA_QCFLAG_FAILED)
2093 ahci_kick_engine(ap);
2096 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2098 struct ahci_host_priv *hpriv = ap->host->private_data;
2099 void __iomem *port_mmio = ahci_port_base(ap);
2100 struct ata_device *dev = ap->link.device;
2101 u32 devslp, dm, dito, mdat, deto, dito_conf;
2103 unsigned int err_mask;
2105 devslp = readl(port_mmio + PORT_DEVSLP);
2106 if (!(devslp & PORT_DEVSLP_DSP)) {
2107 dev_info(ap->host->dev, "port does not support device sleep\n");
2111 /* disable device sleep */
2113 if (devslp & PORT_DEVSLP_ADSE) {
2114 writel(devslp & ~PORT_DEVSLP_ADSE,
2115 port_mmio + PORT_DEVSLP);
2116 err_mask = ata_dev_set_feature(dev,
2117 SETFEATURES_SATA_DISABLE,
2119 if (err_mask && err_mask != AC_ERR_DEV)
2120 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2125 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2126 dito = devslp_idle_timeout / (dm + 1);
2130 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2132 /* device sleep was already enabled and same dito */
2133 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2136 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2137 rc = hpriv->stop_engine(ap);
2141 /* Use the nominal value 10 ms if the read MDAT is zero,
2142 * the nominal value of DETO is 20 ms.
2144 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2145 ATA_LOG_DEVSLP_VALID_MASK) {
2146 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2147 ATA_LOG_DEVSLP_MDAT_MASK;
2150 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2158 /* Make dito, mdat, deto bits to 0s */
2159 devslp &= ~GENMASK_ULL(24, 2);
2160 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2161 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2162 (deto << PORT_DEVSLP_DETO_OFFSET) |
2164 writel(devslp, port_mmio + PORT_DEVSLP);
2166 hpriv->start_engine(ap);
2168 /* enable device sleep feature for the drive */
2169 err_mask = ata_dev_set_feature(dev,
2170 SETFEATURES_SATA_ENABLE,
2172 if (err_mask && err_mask != AC_ERR_DEV)
2173 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2176 static void ahci_enable_fbs(struct ata_port *ap)
2178 struct ahci_host_priv *hpriv = ap->host->private_data;
2179 struct ahci_port_priv *pp = ap->private_data;
2180 void __iomem *port_mmio = ahci_port_base(ap);
2184 if (!pp->fbs_supported)
2187 fbs = readl(port_mmio + PORT_FBS);
2188 if (fbs & PORT_FBS_EN) {
2189 pp->fbs_enabled = true;
2190 pp->fbs_last_dev = -1; /* initialization */
2194 rc = hpriv->stop_engine(ap);
2198 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2199 fbs = readl(port_mmio + PORT_FBS);
2200 if (fbs & PORT_FBS_EN) {
2201 dev_info(ap->host->dev, "FBS is enabled\n");
2202 pp->fbs_enabled = true;
2203 pp->fbs_last_dev = -1; /* initialization */
2205 dev_err(ap->host->dev, "Failed to enable FBS\n");
2207 hpriv->start_engine(ap);
2210 static void ahci_disable_fbs(struct ata_port *ap)
2212 struct ahci_host_priv *hpriv = ap->host->private_data;
2213 struct ahci_port_priv *pp = ap->private_data;
2214 void __iomem *port_mmio = ahci_port_base(ap);
2218 if (!pp->fbs_supported)
2221 fbs = readl(port_mmio + PORT_FBS);
2222 if ((fbs & PORT_FBS_EN) == 0) {
2223 pp->fbs_enabled = false;
2227 rc = hpriv->stop_engine(ap);
2231 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2232 fbs = readl(port_mmio + PORT_FBS);
2233 if (fbs & PORT_FBS_EN)
2234 dev_err(ap->host->dev, "Failed to disable FBS\n");
2236 dev_info(ap->host->dev, "FBS is disabled\n");
2237 pp->fbs_enabled = false;
2240 hpriv->start_engine(ap);
2243 static void ahci_pmp_attach(struct ata_port *ap)
2245 void __iomem *port_mmio = ahci_port_base(ap);
2246 struct ahci_port_priv *pp = ap->private_data;
2249 cmd = readl(port_mmio + PORT_CMD);
2250 cmd |= PORT_CMD_PMP;
2251 writel(cmd, port_mmio + PORT_CMD);
2253 ahci_enable_fbs(ap);
2255 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2258 * We must not change the port interrupt mask register if the
2259 * port is marked frozen, the value in pp->intr_mask will be
2260 * restored later when the port is thawed.
2262 * Note that during initialization, the port is marked as
2263 * frozen since the irq handler is not yet registered.
2265 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2266 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2269 static void ahci_pmp_detach(struct ata_port *ap)
2271 void __iomem *port_mmio = ahci_port_base(ap);
2272 struct ahci_port_priv *pp = ap->private_data;
2275 ahci_disable_fbs(ap);
2277 cmd = readl(port_mmio + PORT_CMD);
2278 cmd &= ~PORT_CMD_PMP;
2279 writel(cmd, port_mmio + PORT_CMD);
2281 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2283 /* see comment above in ahci_pmp_attach() */
2284 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2285 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2288 int ahci_port_resume(struct ata_port *ap)
2290 ahci_rpm_get_port(ap);
2293 ahci_start_port(ap);
2295 if (sata_pmp_attached(ap))
2296 ahci_pmp_attach(ap);
2298 ahci_pmp_detach(ap);
2302 EXPORT_SYMBOL_GPL(ahci_port_resume);
2305 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2307 const char *emsg = NULL;
2310 rc = ahci_deinit_port(ap, &emsg);
2312 ahci_power_down(ap);
2314 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2315 ata_port_freeze(ap);
2318 ahci_rpm_put_port(ap);
2323 static int ahci_port_start(struct ata_port *ap)
2325 struct ahci_host_priv *hpriv = ap->host->private_data;
2326 struct device *dev = ap->host->dev;
2327 struct ahci_port_priv *pp;
2330 size_t dma_sz, rx_fis_sz;
2332 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2336 if (ap->host->n_ports > 1) {
2337 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2338 if (!pp->irq_desc) {
2339 devm_kfree(dev, pp);
2342 snprintf(pp->irq_desc, 8,
2343 "%s%d", dev_driver_string(dev), ap->port_no);
2346 /* check FBS capability */
2347 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2348 void __iomem *port_mmio = ahci_port_base(ap);
2349 u32 cmd = readl(port_mmio + PORT_CMD);
2350 if (cmd & PORT_CMD_FBSCP)
2351 pp->fbs_supported = true;
2352 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2353 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2355 pp->fbs_supported = true;
2357 dev_warn(dev, "port %d is not capable of FBS\n",
2361 if (pp->fbs_supported) {
2362 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2363 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2365 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2366 rx_fis_sz = AHCI_RX_FIS_SZ;
2369 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2372 memset(mem, 0, dma_sz);
2375 * First item in chunk of DMA memory: 32-slot command table,
2376 * 32 bytes each in size
2379 pp->cmd_slot_dma = mem_dma;
2381 mem += AHCI_CMD_SLOT_SZ;
2382 mem_dma += AHCI_CMD_SLOT_SZ;
2385 * Second item: Received-FIS area
2388 pp->rx_fis_dma = mem_dma;
2391 mem_dma += rx_fis_sz;
2394 * Third item: data area for storing a single command
2395 * and its scatter-gather table
2398 pp->cmd_tbl_dma = mem_dma;
2401 * Save off initial list of interrupts to be enabled.
2402 * This could be changed later
2404 pp->intr_mask = DEF_PORT_IRQ;
2407 * Switch to per-port locking in case each port has its own MSI vector.
2409 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2410 spin_lock_init(&pp->lock);
2411 ap->lock = &pp->lock;
2414 ap->private_data = pp;
2416 /* engage engines, captain */
2417 return ahci_port_resume(ap);
2420 static void ahci_port_stop(struct ata_port *ap)
2422 const char *emsg = NULL;
2423 struct ahci_host_priv *hpriv = ap->host->private_data;
2424 void __iomem *host_mmio = hpriv->mmio;
2427 /* de-initialize port */
2428 rc = ahci_deinit_port(ap, &emsg);
2430 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2433 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2436 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2439 void ahci_print_info(struct ata_host *host, const char *scc_s)
2441 struct ahci_host_priv *hpriv = host->private_data;
2442 u32 vers, cap, cap2, impl, speed;
2443 const char *speed_s;
2445 vers = hpriv->version;
2448 impl = hpriv->port_map;
2450 speed = (cap >> 20) & 0xf;
2453 else if (speed == 2)
2455 else if (speed == 3)
2461 "AHCI %02x%02x.%02x%02x "
2462 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2465 (vers >> 24) & 0xff,
2466 (vers >> 16) & 0xff,
2470 ((cap >> 8) & 0x1f) + 1,
2484 cap & HOST_CAP_64 ? "64bit " : "",
2485 cap & HOST_CAP_NCQ ? "ncq " : "",
2486 cap & HOST_CAP_SNTF ? "sntf " : "",
2487 cap & HOST_CAP_MPS ? "ilck " : "",
2488 cap & HOST_CAP_SSS ? "stag " : "",
2489 cap & HOST_CAP_ALPM ? "pm " : "",
2490 cap & HOST_CAP_LED ? "led " : "",
2491 cap & HOST_CAP_CLO ? "clo " : "",
2492 cap & HOST_CAP_ONLY ? "only " : "",
2493 cap & HOST_CAP_PMP ? "pmp " : "",
2494 cap & HOST_CAP_FBS ? "fbs " : "",
2495 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2496 cap & HOST_CAP_SSC ? "slum " : "",
2497 cap & HOST_CAP_PART ? "part " : "",
2498 cap & HOST_CAP_CCC ? "ccc " : "",
2499 cap & HOST_CAP_EMS ? "ems " : "",
2500 cap & HOST_CAP_SXS ? "sxs " : "",
2501 cap2 & HOST_CAP2_DESO ? "deso " : "",
2502 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2503 cap2 & HOST_CAP2_SDS ? "sds " : "",
2504 cap2 & HOST_CAP2_APST ? "apst " : "",
2505 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2506 cap2 & HOST_CAP2_BOH ? "boh " : ""
2509 EXPORT_SYMBOL_GPL(ahci_print_info);
2511 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2512 struct ata_port_info *pi)
2515 void __iomem *mmio = hpriv->mmio;
2516 u32 em_loc = readl(mmio + HOST_EM_LOC);
2517 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2519 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2522 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2526 hpriv->em_loc = ((em_loc >> 16) * 4);
2527 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2528 hpriv->em_msg_type = messages;
2529 pi->flags |= ATA_FLAG_EM;
2530 if (!(em_ctl & EM_CTL_ALHD))
2531 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2534 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2536 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2537 struct scsi_host_template *sht)
2539 struct ahci_host_priv *hpriv = host->private_data;
2542 rc = ata_host_start(host);
2546 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2547 * allocated. That is one MSI per port, starting from @irq.
2549 for (i = 0; i < host->n_ports; i++) {
2550 struct ahci_port_priv *pp = host->ports[i]->private_data;
2551 int irq = hpriv->get_irq_vector(host, i);
2553 /* Do not receive interrupts sent by dummy ports */
2559 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2560 0, pp->irq_desc, host->ports[i]);
2564 ata_port_desc(host->ports[i], "irq %d", irq);
2567 return ata_host_register(host, sht);
2571 * ahci_host_activate - start AHCI host, request IRQs and register it
2572 * @host: target ATA host
2573 * @sht: scsi_host_template to use when registering the host
2576 * Inherited from calling layer (may sleep).
2579 * 0 on success, -errno otherwise.
2581 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2583 struct ahci_host_priv *hpriv = host->private_data;
2584 int irq = hpriv->irq;
2587 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2588 if (hpriv->irq_handler)
2590 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2591 if (!hpriv->get_irq_vector) {
2593 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2597 rc = ahci_host_activate_multi_irqs(host, sht);
2599 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2606 EXPORT_SYMBOL_GPL(ahci_host_activate);
2608 MODULE_AUTHOR("Jeff Garzik");
2609 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2610 MODULE_LICENSE("GPL");