1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
12 but just the error reporting functionality.
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs-l2-ecc
26 - description: single bit error interrupt
27 - description: double bit error interrupt
34 additionalProperties: false
39 compatible = "calxeda,hb-sregs-l2-ecc";
40 reg = <0xfff3c200 0x100>;
41 interrupts = <0 71 4>, <0 72 4>;