1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2017 Benjamin Herrenschmidt, IBM Corporation
6 #ifndef _KVM_PPC_BOOK3S_XIVE_H
7 #define _KVM_PPC_BOOK3S_XIVE_H
10 #include "book3s_xics.h"
13 * The XIVE Interrupt source numbers are within the range 0 to
14 * KVMPPC_XICS_NR_IRQS.
16 #define KVMPPC_XIVE_FIRST_IRQ 0
17 #define KVMPPC_XIVE_NR_IRQS KVMPPC_XICS_NR_IRQS
20 * State for one guest irq source.
22 * For each guest source we allocate a HW interrupt in the XIVE
23 * which we use for all SW triggers. It will be unused for
24 * pass-through but it's easier to keep around as the same
25 * guest interrupt can alternatively be emulated or pass-through
26 * if a physical device is hot unplugged and replaced with an
29 * This state structure is very similar to the XICS one with
30 * additional XIVE specific tracking.
32 struct kvmppc_xive_irq_state {
33 bool valid; /* Interrupt entry is valid */
35 u32 number; /* Guest IRQ number */
36 u32 ipi_number; /* XIVE IPI HW number */
37 struct xive_irq_data ipi_data; /* XIVE IPI associated data */
38 u32 pt_number; /* XIVE Pass-through number if any */
39 struct xive_irq_data *pt_data; /* XIVE Pass-through associated data */
41 /* Targetting as set by guest */
42 u8 guest_priority; /* Guest set priority */
43 u8 saved_priority; /* Saved priority when masking */
45 /* Actual targetting */
46 u32 act_server; /* Actual server */
47 u8 act_priority; /* Actual priority */
49 /* Various state bits */
50 bool in_eoi; /* Synchronize with H_EOI */
51 bool old_p; /* P bit state when masking */
52 bool old_q; /* Q bit state when masking */
53 bool lsi; /* level-sensitive interrupt */
54 bool asserted; /* Only for emulated LSI: current state */
56 /* Saved for migration state */
63 u32 eisn; /* Guest Effective IRQ number */
66 /* Select the "right" interrupt (IPI vs. passthrough) */
67 static inline void kvmppc_xive_select_irq(struct kvmppc_xive_irq_state *state,
69 struct xive_irq_data **out_xd)
71 if (state->pt_number) {
73 *out_hw_irq = state->pt_number;
75 *out_xd = state->pt_data;
78 *out_hw_irq = state->ipi_number;
80 *out_xd = &state->ipi_data;
85 * This corresponds to an "ICS" in XICS terminology, we use it
86 * as a mean to break up source information into multiple structures.
88 struct kvmppc_xive_src_block {
91 struct kvmppc_xive_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
96 struct kvmppc_xive_ops {
97 int (*reset_mapped)(struct kvm *kvm, unsigned long guest_irq);
100 #define KVMPPC_XIVE_FLAG_SINGLE_ESCALATION 0x1
101 #define KVMPPC_XIVE_FLAG_SAVE_RESTORE 0x2
105 struct kvm_device *dev;
106 struct dentry *dentry;
108 /* VP block associated with the VM */
111 /* Blocks of sources */
112 struct kvmppc_xive_src_block *src_blocks[KVMPPC_XICS_MAX_ICS_ID + 1];
116 * For state save, we lazily scan the queues on the first interrupt
117 * being migrated. We don't have a clean way to reset that flags
118 * so we keep track of the number of valid sources and how many of
119 * them were migrated so we can reset when all of them have been
126 * Some irqs are delayed on restore until the source is created,
127 * keep track here of how many of them
131 /* Which queues (priorities) are in use by the guest */
141 /* Number of entries in the VP block */
144 struct kvmppc_xive_ops *ops;
145 struct address_space *mapping;
146 struct mutex mapping_lock;
150 #define KVMPPC_XIVE_Q_COUNT 8
152 struct kvmppc_xive_vcpu {
153 struct kvmppc_xive *xive;
154 struct kvm_vcpu *vcpu;
157 /* Server number. This is the HW CPU ID from a guest perspective */
161 * HW VP corresponding to this VCPU. This is the base of the VP
162 * block plus the server number.
168 /* IPI used for sending ... IPIs */
170 struct xive_irq_data vp_ipi_data;
172 /* Local emulation state */
173 uint8_t cppr; /* guest CPPR */
174 uint8_t hw_cppr;/* Hardware CPPR */
178 /* Each VP has 8 queues though we only provision some */
179 struct xive_q queues[KVMPPC_XIVE_Q_COUNT];
180 u32 esc_virq[KVMPPC_XIVE_Q_COUNT];
181 char *esc_virq_names[KVMPPC_XIVE_Q_COUNT];
183 /* Stash a delayed irq on restore from migration (see set_icp) */
199 static inline struct kvm_vcpu *kvmppc_xive_find_server(struct kvm *kvm, u32 nr)
201 struct kvm_vcpu *vcpu = NULL;
204 kvm_for_each_vcpu(i, vcpu, kvm) {
205 if (vcpu->arch.xive_vcpu && nr == vcpu->arch.xive_vcpu->server_num)
211 static inline struct kvmppc_xive_src_block *kvmppc_xive_find_source(struct kvmppc_xive *xive,
212 u32 irq, u16 *source)
214 u32 bid = irq >> KVMPPC_XICS_ICS_SHIFT;
215 u16 src = irq & KVMPPC_XICS_SRC_MASK;
219 if (bid > KVMPPC_XICS_MAX_ICS_ID)
221 return xive->src_blocks[bid];
225 * When the XIVE resources are allocated at the HW level, the VP
226 * structures describing the vCPUs of a guest are distributed among
227 * the chips to optimize the PowerBUS usage. For best performance, the
228 * guest vCPUs can be pinned to match the VP structure distribution.
230 * Currently, the VP identifiers are deduced from the vCPU id using
231 * the kvmppc_pack_vcpu_id() routine which is not incorrect but not
232 * optimal either. It VSMT is used, the result is not continuous and
233 * the constraints on HW resources described above can not be met.
235 static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server)
237 return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
240 static inline bool kvmppc_xive_vp_in_use(struct kvm *kvm, u32 vp_id)
242 struct kvm_vcpu *vcpu = NULL;
245 kvm_for_each_vcpu(i, vcpu, kvm) {
246 if (vcpu->arch.xive_vcpu && vp_id == vcpu->arch.xive_vcpu->vp_id)
253 * Mapping between guest priorities and host priorities
256 * Guest request for 0...6 are honored. Guest request for anything
257 * higher results in a priority of 6 being applied.
259 * Similar mapping is done for CPPR values
261 static inline u8 xive_prio_from_guest(u8 prio)
263 if (prio == 0xff || prio < 6)
268 static inline u8 xive_prio_to_guest(u8 prio)
273 static inline u32 __xive_read_eq(__be32 *qpage, u32 msk, u32 *idx, u32 *toggle)
279 cur = be32_to_cpup(qpage + *idx);
280 if ((cur >> 31) == *toggle)
282 *idx = (*idx + 1) & msk;
285 return cur & 0x7fffffff;
289 * Common Xive routines for XICS-over-XIVE and XIVE native
291 void kvmppc_xive_disable_vcpu_interrupts(struct kvm_vcpu *vcpu);
292 int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu);
293 void kvmppc_xive_debug_show_sources(struct seq_file *m,
294 struct kvmppc_xive_src_block *sb);
295 struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
296 struct kvmppc_xive *xive, int irq);
297 void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
298 int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
299 int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
300 bool single_escalation);
301 struct kvmppc_xive *kvmppc_xive_get_device(struct kvm *kvm, u32 type);
302 void xive_cleanup_single_escalation(struct kvm_vcpu *vcpu, int irq);
303 int kvmppc_xive_compute_vp_id(struct kvmppc_xive *xive, u32 cpu, u32 *vp);
304 int kvmppc_xive_set_nr_servers(struct kvmppc_xive *xive, u64 addr);
305 bool kvmppc_xive_check_save_restore(struct kvm_vcpu *vcpu);
307 static inline bool kvmppc_xive_has_single_escalation(struct kvmppc_xive *xive)
309 return xive->flags & KVMPPC_XIVE_FLAG_SINGLE_ESCALATION;
312 #endif /* CONFIG_KVM_XICS */
313 #endif /* _KVM_PPC_BOOK3S_XICS_H */