1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <asm/processor.h>
3 #include <asm/ppc_asm.h>
5 #include <asm/asm-offsets.h>
6 #include <asm/cputable.h>
7 #include <asm/thread_info.h>
9 #include <asm/ptrace.h>
10 #include <asm/export.h>
11 #include <asm/asm-compat.h>
14 * Load state from memory into VMX registers including VSCR.
15 * Assumes the caller has enabled VMX in the MSR.
17 _GLOBAL(load_vr_state)
23 EXPORT_SYMBOL(load_vr_state)
26 * Store VMX state into memory, including VSCR.
27 * Assumes the caller has enabled VMX in the MSR.
29 _GLOBAL(store_vr_state)
35 EXPORT_SYMBOL(store_vr_state)
38 * Disable VMX for the task which had it previously,
39 * and save its vector registers in its thread_struct.
40 * Enables the VMX for use in the kernel on return.
41 * On SMP we know the VMX is free, since we give it up every
42 * switch (ie, no lazy save of the vector registers).
44 * Note that on 32-bit this can only use registers that will be
45 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
47 _GLOBAL(load_up_altivec)
48 mfmsr r5 /* grab the current MSR */
50 MTMSRD(r5) /* enable use of AltiVec now */
54 * While userspace in general ignores VRSAVE, glibc uses it as a boolean
55 * to optimise userspace context save/restore. Whenever we take an
56 * altivec unavailable exception we must set VRSAVE to something non
57 * zero. Set it to all 1s. See also the programming note in the ISA.
65 /* enable use of VMX after return */
67 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
70 ld r4,PACACURRENT(r13)
71 addi r5,r4,THREAD /* Get THREAD */
72 oris r12,r12,MSR_VEC@h
75 /* Don't care if r4 overflows, this is desired behaviour */
76 lbz r4,THREAD_LOAD_VEC(r5)
78 stb r4,THREAD_LOAD_VEC(r5)
79 addi r6,r5,THREAD_VRSTATE
82 stw r4,THREAD_USED_VR(r5)
86 /* restore registers and return */
91 * Save the vector registers to its thread_struct
94 addi r3,r3,THREAD /* want THREAD of task */
95 PPC_LL r7,THREAD_VRSAVEAREA(r3)
99 addi r7,r3,THREAD_VRSTATE
100 2: SAVE_32VRS(0,r4,r7)
109 #error This asm code isn't ready for 32-bit kernels
113 * load_up_vsx(unused, unused, tsk)
114 * Disable VSX for the task which had it previously,
115 * and save its vector registers in its thread_struct.
116 * Reuse the fp and vsx saves, but first check to see if they have
117 * been saved already.
120 /* Load FP and VSX registers if they haven't been done yet */
122 beql+ load_up_fpu /* skip if already loaded */
123 andis. r5,r12,MSR_VEC@h
124 beql+ load_up_altivec /* skip if already loaded */
126 ld r4,PACACURRENT(r13)
127 addi r4,r4,THREAD /* Get THREAD */
129 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
130 /* enable use of VSX after return */
131 oris r12,r12,MSR_VSX@h
133 b fast_exception_return
135 #endif /* CONFIG_VSX */
139 * The routines below are in assembler so we can closely control the
140 * usage of floating-point registers. These routines must be called
141 * with preempt disabled.
148 .long 0x3f800000 /* 1.0 in single-precision FP */
150 .long 0x3f000000 /* 0.5 in single-precision FP */
152 #define LDCONST(fr, name) \
161 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
163 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
165 #define LDCONST(fr, name) \
171 * Internal routine to enable floating point and set FPSCR to 0.
172 * Don't call it from C; it doesn't use the normal calling convention.
204 * Vector add, floating point.
221 * Vector subtract, floating point.
238 * Vector multiply and add, floating point.
250 fmadds fr0,fr0,fr2,fr1
258 * Vector negative multiply and subtract, floating point.
270 fnmsubs fr0,fr0,fr2,fr1
278 * Vector reciprocal estimate. We just compute 1.0/x.
279 * r3 -> destination, r4 -> source.
296 * Vector reciprocal square-root estimate, floating point.
297 * We use the frsqrte instruction for the initial estimate followed
298 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
299 * r3 -> destination, r4 -> source.
314 frsqrte fr1,fr0 /* r = frsqrte(s) */
315 fmuls fr3,fr1,fr0 /* r * s */
316 fmuls fr2,fr1,fr5 /* r * 0.5 */
317 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
318 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
319 fmuls fr3,fr1,fr0 /* r * s */
320 fmuls fr2,fr1,fr5 /* r * 0.5 */
321 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
322 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */