3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/export.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/reboot.h>
19 #include <linux/delay.h>
20 #include <linux/initrd.h>
21 #include <linux/seq_file.h>
22 #include <linux/ioport.h>
23 #include <linux/console.h>
24 #include <linux/utsname.h>
25 #include <linux/tty.h>
26 #include <linux/root_dev.h>
27 #include <linux/notifier.h>
28 #include <linux/cpu.h>
29 #include <linux/unistd.h>
30 #include <linux/serial.h>
31 #include <linux/serial_8250.h>
32 #include <linux/bootmem.h>
33 #include <linux/pci.h>
34 #include <linux/lockdep.h>
35 #include <linux/memblock.h>
36 #include <linux/memory.h>
37 #include <linux/nmi.h>
39 #include <asm/debugfs.h>
41 #include <asm/kdump.h>
43 #include <asm/processor.h>
44 #include <asm/pgtable.h>
47 #include <asm/machdep.h>
50 #include <asm/cputable.h>
51 #include <asm/dt_cpu_ftrs.h>
52 #include <asm/sections.h>
53 #include <asm/btext.h>
54 #include <asm/nvram.h>
55 #include <asm/setup.h>
57 #include <asm/iommu.h>
58 #include <asm/serial.h>
59 #include <asm/cache.h>
62 #include <asm/firmware.h>
65 #include <asm/kexec.h>
66 #include <asm/code-patching.h>
67 #include <asm/livepatch.h>
69 #include <asm/cputhreads.h>
70 #include <asm/hw_irq.h>
71 #include <asm/feature-fixups.h>
76 #define DBG(fmt...) udbg_printf(fmt)
81 int spinning_secondaries;
84 struct ppc64_caches ppc64_caches = {
94 EXPORT_SYMBOL_GPL(ppc64_caches);
96 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
97 void __init setup_tlb_core_data(void)
101 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
103 for_each_possible_cpu(cpu) {
104 int first = cpu_first_thread_sibling(cpu);
107 * If we boot via kdump on a non-primary thread,
108 * make sure we point at the thread that actually
111 if (cpu_first_thread_sibling(boot_cpuid) == first)
114 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
117 * If we have threads, we need either tlbsrx.
118 * or e6500 tablewalk mode, or else TLB handlers
119 * will be racy and could produce duplicate entries.
120 * Should we panic instead?
122 WARN_ONCE(smt_enabled_at_boot >= 2 &&
123 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
124 book3e_htw_mode != PPC_HTW_E6500,
125 "%s: unsupported MMU configuration\n", __func__);
132 static char *smt_enabled_cmdline;
134 /* Look for ibm,smt-enabled OF option */
135 void __init check_smt_enabled(void)
137 struct device_node *dn;
138 const char *smt_option;
140 /* Default to enabling all threads */
141 smt_enabled_at_boot = threads_per_core;
143 /* Allow the command line to overrule the OF option */
144 if (smt_enabled_cmdline) {
145 if (!strcmp(smt_enabled_cmdline, "on"))
146 smt_enabled_at_boot = threads_per_core;
147 else if (!strcmp(smt_enabled_cmdline, "off"))
148 smt_enabled_at_boot = 0;
153 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
155 smt_enabled_at_boot =
156 min(threads_per_core, smt);
159 dn = of_find_node_by_path("/options");
161 smt_option = of_get_property(dn, "ibm,smt-enabled",
165 if (!strcmp(smt_option, "on"))
166 smt_enabled_at_boot = threads_per_core;
167 else if (!strcmp(smt_option, "off"))
168 smt_enabled_at_boot = 0;
176 /* Look for smt-enabled= cmdline option */
177 static int __init early_smt_enabled(char *p)
179 smt_enabled_cmdline = p;
182 early_param("smt-enabled", early_smt_enabled);
184 #endif /* CONFIG_SMP */
186 /** Fix up paca fields required for the boot cpu */
187 static void __init fixup_boot_paca(void)
189 /* The boot cpu is started */
190 get_paca()->cpu_start = 1;
191 /* Allow percpu accesses to work until we setup percpu data */
192 get_paca()->data_offset = 0;
193 /* Mark interrupts disabled in PACA */
194 irq_soft_mask_set(IRQS_DISABLED);
197 static void __init configure_exceptions(void)
200 * Setup the trampolines from the lowmem exception vectors
201 * to the kdump kernel when not using a relocatable kernel.
203 setup_kdump_trampoline();
205 /* Under a PAPR hypervisor, we need hypercalls */
206 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
207 /* Enable AIL if possible */
208 pseries_enable_reloc_on_exc();
211 * Tell the hypervisor that we want our exceptions to
212 * be taken in little endian mode.
214 * We don't call this for big endian as our calling convention
215 * makes us always enter in BE, and the call may fail under
216 * some circumstances with kdump.
218 #ifdef __LITTLE_ENDIAN__
219 pseries_little_endian_exceptions();
222 /* Set endian mode using OPAL */
223 if (firmware_has_feature(FW_FEATURE_OPAL))
224 opal_configure_cores();
226 /* AIL on native is done in cpu_ready_for_interrupts() */
230 static void cpu_ready_for_interrupts(void)
233 * Enable AIL if supported, and we are in hypervisor mode. This
234 * is called once for every processor.
236 * If we are not in hypervisor mode the job is done once for
237 * the whole partition in configure_exceptions().
239 if (cpu_has_feature(CPU_FTR_HVMODE) &&
240 cpu_has_feature(CPU_FTR_ARCH_207S)) {
241 unsigned long lpcr = mfspr(SPRN_LPCR);
242 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
246 * Set HFSCR:TM based on CPU features:
247 * In the special case of TM no suspend (P9N DD2.1), Linux is
248 * told TM is off via the dt-ftrs but told to (partially) use
249 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
250 * will be off from dt-ftrs but we need to turn it on for the
253 if (cpu_has_feature(CPU_FTR_HVMODE)) {
254 if (cpu_has_feature(CPU_FTR_TM_COMP))
255 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
257 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
260 /* Set IR and DR in PACA MSR */
261 get_paca()->kernel_msr = MSR_KERNEL;
264 unsigned long spr_default_dscr = 0;
266 void __init record_spr_defaults(void)
268 if (early_cpu_has_feature(CPU_FTR_DSCR))
269 spr_default_dscr = mfspr(SPRN_DSCR);
273 * Early initialization entry point. This is called by head.S
274 * with MMU translation disabled. We rely on the "feature" of
275 * the CPU that ignores the top 2 bits of the address in real
276 * mode so we can access kernel globals normally provided we
277 * only toy with things in the RMO region. From here, we do
278 * some early parsing of the device-tree to setup out MEMBLOCK
279 * data structures, and allocate & initialize the hash table
280 * and segment tables so we can start running with translation
283 * It is this function which will call the probe() callback of
284 * the various platform types and copy the matching one to the
285 * global ppc_md structure. Your platform can eventually do
286 * some very early initializations from the probe() routine, but
287 * this is not recommended, be very careful as, for example, the
288 * device-tree is not accessible via normal means at this point.
291 void __init early_setup(unsigned long dt_ptr)
293 static __initdata struct paca_struct boot_paca;
295 /* -------- printk is _NOT_ safe to use here ! ------- */
297 /* Try new device tree based feature discovery ... */
298 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
299 /* Otherwise use the old style CPU table */
300 identify_cpu(0, mfspr(SPRN_PVR));
302 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
303 initialise_paca(&boot_paca, 0);
304 setup_paca(&boot_paca);
307 /* -------- printk is now safe to use ------- */
309 /* Enable early debugging if any specified (see udbg.h) */
312 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
315 * Do early initialization using the flattened device
316 * tree, such as retrieving the physical memory map or
317 * calculating/retrieving the hash table size.
319 early_init_devtree(__va(dt_ptr));
321 /* Now we know the logical id of our boot cpu, setup the paca. */
322 if (boot_cpuid != 0) {
323 /* Poison paca_ptrs[0] again if it's not the boot cpu */
324 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
326 setup_paca(paca_ptrs[boot_cpuid]);
330 * Configure exception handlers. This include setting up trampolines
331 * if needed, setting exception endian mode, etc...
333 configure_exceptions();
335 /* Apply all the dynamic patching */
336 apply_feature_fixups();
337 setup_feature_keys();
339 /* Initialize the hash table or TLB handling */
343 * After firmware and early platform setup code has set things up,
344 * we note the SPR values for configurable control/performance
345 * registers, and use those as initial defaults.
347 record_spr_defaults();
350 * At this point, we can let interrupts switch to virtual mode
351 * (the MMU has been setup), so adjust the MSR in the PACA to
352 * have IR and DR set and enable AIL if it exists
354 cpu_ready_for_interrupts();
357 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
358 * will only actually get enabled on the boot cpu much later once
359 * ftrace itself has been initialized.
361 this_cpu_enable_ftrace();
363 DBG(" <- early_setup()\n");
365 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
367 * This needs to be done *last* (after the above DBG() even)
369 * Right after we return from this function, we turn on the MMU
370 * which means the real-mode access trick that btext does will
371 * no longer work, it needs to switch to using a real MMU
372 * mapping. This call will ensure that it does
375 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
379 void early_setup_secondary(void)
381 /* Mark interrupts disabled in PACA */
382 irq_soft_mask_set(IRQS_DISABLED);
384 /* Initialize the hash table or TLB handling */
385 early_init_mmu_secondary();
388 * At this point, we can let interrupts switch to virtual mode
389 * (the MMU has been setup), so adjust the MSR in the PACA to
390 * have IR and DR set.
392 cpu_ready_for_interrupts();
395 #endif /* CONFIG_SMP */
397 void panic_smp_self_stop(void)
405 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
406 static bool use_spinloop(void)
408 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
410 * See comments in head_64.S -- not all platforms insert
411 * secondaries at __secondary_hold and wait at the spin
414 if (firmware_has_feature(FW_FEATURE_OPAL))
420 * When book3e boots from kexec, the ePAPR spin table does
423 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
426 void smp_release_cpus(void)
434 DBG(" -> smp_release_cpus()\n");
436 /* All secondary cpus are spinning on a common spinloop, release them
437 * all now so they can start to spin on their individual paca
438 * spinloops. For non SMP kernels, the secondary cpus never get out
439 * of the common spinloop.
442 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
444 *ptr = ppc_function_entry(generic_secondary_smp_init);
446 /* And wait a bit for them to catch up */
447 for (i = 0; i < 100000; i++) {
450 if (spinning_secondaries == 0)
454 DBG("spinning_secondaries = %d\n", spinning_secondaries);
456 DBG(" <- smp_release_cpus()\n");
458 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
461 * Initialize some remaining members of the ppc64_caches and systemcfg
463 * (at least until we get rid of them completely). This is mostly some
464 * cache informations about the CPU that will be used by cache flush
465 * routines and/or provided to userland
468 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
473 info->line_size = lsize;
474 info->block_size = bsize;
475 info->log_block_size = __ilog2(bsize);
477 info->blocks_per_page = PAGE_SIZE / bsize;
479 info->blocks_per_page = 0;
482 info->assoc = 0xffff;
484 info->assoc = size / (sets * lsize);
487 static bool __init parse_cache_info(struct device_node *np,
489 struct ppc_cache_info *info)
491 static const char *ipropnames[] __initdata = {
494 "i-cache-block-size",
497 static const char *dpropnames[] __initdata = {
500 "d-cache-block-size",
503 const char **propnames = icache ? ipropnames : dpropnames;
504 const __be32 *sizep, *lsizep, *bsizep, *setsp;
505 u32 size, lsize, bsize, sets;
510 lsize = bsize = cur_cpu_spec->dcache_bsize;
511 sizep = of_get_property(np, propnames[0], NULL);
513 size = be32_to_cpu(*sizep);
514 setsp = of_get_property(np, propnames[1], NULL);
516 sets = be32_to_cpu(*setsp);
517 bsizep = of_get_property(np, propnames[2], NULL);
518 lsizep = of_get_property(np, propnames[3], NULL);
524 lsize = be32_to_cpu(*lsizep);
526 bsize = be32_to_cpu(*bsizep);
527 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
531 * OF is weird .. it represents fully associative caches
532 * as "1 way" which doesn't make much sense and doesn't
533 * leave room for direct mapped. We'll assume that 0
534 * in OF means direct mapped for that reason.
541 init_cache_info(info, size, lsize, bsize, sets);
546 void __init initialize_cache_info(void)
548 struct device_node *cpu = NULL, *l2, *l3 = NULL;
551 DBG(" -> initialize_cache_info()\n");
554 * All shipping POWER8 machines have a firmware bug that
555 * puts incorrect information in the device-tree. This will
556 * be (hopefully) fixed for future chips but for now hard
557 * code the values if we are running on one of these
559 pvr = PVR_VER(mfspr(SPRN_PVR));
560 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
561 pvr == PVR_POWER8NVL) {
562 /* size lsize blk sets */
563 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
564 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
565 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
566 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
568 cpu = of_find_node_by_type(NULL, "cpu");
571 * We're assuming *all* of the CPUs have the same
572 * d-cache and i-cache sizes... -Peter
575 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
576 DBG("Argh, can't find dcache properties !\n");
578 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
579 DBG("Argh, can't find icache properties !\n");
582 * Try to find the L2 and L3 if any. Assume they are
583 * unified and use the D-side properties.
585 l2 = of_find_next_cache_node(cpu);
588 parse_cache_info(l2, false, &ppc64_caches.l2);
589 l3 = of_find_next_cache_node(l2);
593 parse_cache_info(l3, false, &ppc64_caches.l3);
598 /* For use by binfmt_elf */
599 dcache_bsize = ppc64_caches.l1d.block_size;
600 icache_bsize = ppc64_caches.l1i.block_size;
602 cur_cpu_spec->dcache_bsize = dcache_bsize;
603 cur_cpu_spec->icache_bsize = icache_bsize;
605 DBG(" <- initialize_cache_info()\n");
609 * This returns the limit below which memory accesses to the linear
610 * mapping are guarnateed not to cause an architectural exception (e.g.,
611 * TLB or SLB miss fault).
613 * This is used to allocate PACAs and various interrupt stacks that
614 * that are accessed early in interrupt handlers that must not cause
615 * re-entrant interrupts.
617 __init u64 ppc64_bolted_size(void)
619 #ifdef CONFIG_PPC_BOOK3E
620 /* Freescale BookE bolts the entire linear mapping */
621 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
622 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
623 return linear_map_top;
624 /* Other BookE, we assume the first GB is bolted */
627 /* BookS radix, does not take faults on linear mapping */
628 if (early_radix_enabled())
631 /* BookS hash, the first segment is bolted */
632 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
633 return 1UL << SID_SHIFT_1T;
634 return 1UL << SID_SHIFT;
638 static void *__init alloc_stack(unsigned long limit, int cpu)
642 pa = memblock_alloc_base_nid(THREAD_SIZE, THREAD_SIZE, limit,
643 early_cpu_to_node(cpu), MEMBLOCK_NONE);
645 pa = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
647 panic("cannot allocate stacks");
653 void __init irqstack_early_init(void)
655 u64 limit = ppc64_bolted_size();
659 * Interrupt stacks must be in the first segment since we
660 * cannot afford to take SLB misses on them. They are not
661 * accessed in realmode.
663 for_each_possible_cpu(i) {
664 softirq_ctx[i] = alloc_stack(limit, i);
665 hardirq_ctx[i] = alloc_stack(limit, i);
669 #ifdef CONFIG_PPC_BOOK3E
670 void __init exc_lvl_early_init(void)
674 for_each_possible_cpu(i) {
677 sp = alloc_stack(ULONG_MAX, i);
679 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
681 sp = alloc_stack(ULONG_MAX, i);
683 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
685 sp = alloc_stack(ULONG_MAX, i);
686 mcheckirq_ctx[i] = sp;
687 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
690 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
691 patch_exception(0x040, exc_debug_debug_book3e);
696 * Emergency stacks are used for a range of things, from asynchronous
697 * NMIs (system reset, machine check) to synchronous, process context.
698 * We set preempt_count to zero, even though that isn't necessarily correct. To
699 * get the right value we'd need to copy it from the previous thread_info, but
700 * doing that might fault causing more problems.
701 * TODO: what to do with accounting?
703 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
707 ti->preempt_count = 0;
710 klp_init_thread_info(ti);
714 * Stack space used when we detect a bad kernel stack pointer, and
715 * early in SMP boots before relocation is enabled. Exclusive emergency
716 * stack for machine checks.
718 void __init emergency_stack_init(void)
724 * Emergency stacks must be under 256MB, we cannot afford to take
725 * SLB misses on them. The ABI also requires them to be 128-byte
728 * Since we use these as temporary stacks during secondary CPU
729 * bringup, machine check, system reset, and HMI, we need to get
730 * at them in real mode. This means they must also be within the RMO
733 * The IRQ stacks allocated elsewhere in this file are zeroed and
734 * initialized in kernel/irq.c. These are initialized here in order
735 * to have emergency stacks available as early as possible.
737 limit = min(ppc64_bolted_size(), ppc64_rma_size);
739 for_each_possible_cpu(i) {
740 struct thread_info *ti;
742 ti = alloc_stack(limit, i);
743 memset(ti, 0, THREAD_SIZE);
744 emerg_stack_init_thread_info(ti, i);
745 paca_ptrs[i]->emergency_sp = (void *)ti + THREAD_SIZE;
747 #ifdef CONFIG_PPC_BOOK3S_64
748 /* emergency stack for NMI exception handling. */
749 ti = alloc_stack(limit, i);
750 memset(ti, 0, THREAD_SIZE);
751 emerg_stack_init_thread_info(ti, i);
752 paca_ptrs[i]->nmi_emergency_sp = (void *)ti + THREAD_SIZE;
754 /* emergency stack for machine check exception handling. */
755 ti = alloc_stack(limit, i);
756 memset(ti, 0, THREAD_SIZE);
757 emerg_stack_init_thread_info(ti, i);
758 paca_ptrs[i]->mc_emergency_sp = (void *)ti + THREAD_SIZE;
764 #define PCPU_DYN_SIZE ()
766 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
768 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
769 __pa(MAX_DMA_ADDRESS));
772 static void __init pcpu_fc_free(void *ptr, size_t size)
774 free_bootmem(__pa(ptr), size);
777 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
779 if (early_cpu_to_node(from) == early_cpu_to_node(to))
780 return LOCAL_DISTANCE;
782 return REMOTE_DISTANCE;
785 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
786 EXPORT_SYMBOL(__per_cpu_offset);
788 void __init setup_per_cpu_areas(void)
790 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
797 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
798 * to group units. For larger mappings, use 1M atom which
799 * should be large enough to contain a number of units.
801 if (mmu_linear_psize == MMU_PAGE_4K)
802 atom_size = PAGE_SIZE;
806 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
807 pcpu_fc_alloc, pcpu_fc_free);
809 panic("cannot initialize percpu area (err=%d)", rc);
811 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
812 for_each_possible_cpu(cpu) {
813 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
814 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
819 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
820 unsigned long memory_block_size_bytes(void)
822 if (ppc_md.memory_block_size)
823 return ppc_md.memory_block_size();
825 return MIN_MEMORY_BLOCK_SIZE;
829 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
830 struct ppc_pci_io ppc_pci_io;
831 EXPORT_SYMBOL(ppc_pci_io);
834 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
835 u64 hw_nmi_get_sample_period(int watchdog_thresh)
837 return ppc_proc_freq * watchdog_thresh;
842 * The perf based hardlockup detector breaks PMU event based branches, so
843 * disable it by default. Book3S has a soft-nmi hardlockup detector based
844 * on the decrementer interrupt, so it does not suffer from this problem.
846 * It is likely to get false positives in VM guests, so disable it there
849 static int __init disable_hardlockup_detector(void)
851 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
852 hardlockup_detector_disable();
854 if (firmware_has_feature(FW_FEATURE_LPAR))
855 hardlockup_detector_disable();
860 early_initcall(disable_hardlockup_detector);
862 #ifdef CONFIG_PPC_BOOK3S_64
863 static enum l1d_flush_type enabled_flush_types;
864 static void *l1d_flush_fallback_area;
865 static bool no_rfi_flush;
866 static bool no_entry_flush;
867 static bool no_uaccess_flush;
871 DEFINE_STATIC_KEY_FALSE(uaccess_flush_key);
872 EXPORT_SYMBOL(uaccess_flush_key);
874 static int __init handle_no_rfi_flush(char *p)
876 pr_info("rfi-flush: disabled on command line.");
880 early_param("no_rfi_flush", handle_no_rfi_flush);
882 static int __init handle_no_entry_flush(char *p)
884 pr_info("entry-flush: disabled on command line.");
885 no_entry_flush = true;
888 early_param("no_entry_flush", handle_no_entry_flush);
890 static int __init handle_no_uaccess_flush(char *p)
892 pr_info("uaccess-flush: disabled on command line.");
893 no_uaccess_flush = true;
896 early_param("no_uaccess_flush", handle_no_uaccess_flush);
899 * The RFI flush is not KPTI, but because users will see doco that says to use
900 * nopti we hijack that option here to also disable the RFI flush.
902 static int __init handle_no_pti(char *p)
904 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
905 handle_no_rfi_flush(NULL);
908 early_param("nopti", handle_no_pti);
910 static void do_nothing(void *unused)
913 * We don't need to do the flush explicitly, just enter+exit kernel is
914 * sufficient, the RFI exit handlers will do the right thing.
918 void rfi_flush_enable(bool enable)
921 do_rfi_flush_fixups(enabled_flush_types);
922 on_each_cpu(do_nothing, NULL, 1);
924 do_rfi_flush_fixups(L1D_FLUSH_NONE);
929 void entry_flush_enable(bool enable)
932 do_entry_flush_fixups(enabled_flush_types);
933 on_each_cpu(do_nothing, NULL, 1);
935 do_entry_flush_fixups(L1D_FLUSH_NONE);
938 entry_flush = enable;
941 void uaccess_flush_enable(bool enable)
944 do_uaccess_flush_fixups(enabled_flush_types);
945 static_branch_enable(&uaccess_flush_key);
946 on_each_cpu(do_nothing, NULL, 1);
948 static_branch_disable(&uaccess_flush_key);
949 do_uaccess_flush_fixups(L1D_FLUSH_NONE);
952 uaccess_flush = enable;
955 static void __ref init_fallback_flush(void)
960 /* Only allocate the fallback flush area once (at boot time). */
961 if (l1d_flush_fallback_area)
964 l1d_size = ppc64_caches.l1d.size;
967 * If there is no d-cache-size property in the device tree, l1d_size
968 * could be zero. That leads to the loop in the asm wrapping around to
969 * 2^64-1, and then walking off the end of the fallback area and
970 * eventually causing a page fault which is fatal. Just default to
971 * something vaguely sane.
974 l1d_size = (64 * 1024);
976 limit = min(ppc64_bolted_size(), ppc64_rma_size);
979 * Align to L1d size, and size it at 2x L1d size, to catch possible
980 * hardware prefetch runoff. We don't have a recipe for load patterns to
981 * reliably avoid the prefetcher.
983 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
984 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
986 for_each_possible_cpu(cpu) {
987 struct paca_struct *paca = paca_ptrs[cpu];
988 paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
989 paca->l1d_flush_size = l1d_size;
993 void setup_rfi_flush(enum l1d_flush_type types, bool enable)
995 if (types & L1D_FLUSH_FALLBACK) {
996 pr_info("rfi-flush: fallback displacement flush available\n");
997 init_fallback_flush();
1000 if (types & L1D_FLUSH_ORI)
1001 pr_info("rfi-flush: ori type flush available\n");
1003 if (types & L1D_FLUSH_MTTRIG)
1004 pr_info("rfi-flush: mttrig type flush available\n");
1006 enabled_flush_types = types;
1008 if (!cpu_mitigations_off() && !no_rfi_flush)
1009 rfi_flush_enable(enable);
1012 void setup_entry_flush(bool enable)
1014 if (cpu_mitigations_off())
1017 if (!no_entry_flush)
1018 entry_flush_enable(enable);
1021 void setup_uaccess_flush(bool enable)
1023 if (cpu_mitigations_off())
1026 if (!no_uaccess_flush)
1027 uaccess_flush_enable(enable);
1030 #ifdef CONFIG_DEBUG_FS
1031 static int rfi_flush_set(void *data, u64 val)
1042 /* Only do anything if we're changing state */
1043 if (enable != rfi_flush)
1044 rfi_flush_enable(enable);
1049 static int rfi_flush_get(void *data, u64 *val)
1051 *val = rfi_flush ? 1 : 0;
1055 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
1057 static int entry_flush_set(void *data, u64 val)
1068 /* Only do anything if we're changing state */
1069 if (enable != entry_flush)
1070 entry_flush_enable(enable);
1075 static int entry_flush_get(void *data, u64 *val)
1077 *val = entry_flush ? 1 : 0;
1081 DEFINE_SIMPLE_ATTRIBUTE(fops_entry_flush, entry_flush_get, entry_flush_set, "%llu\n");
1083 static int uaccess_flush_set(void *data, u64 val)
1094 /* Only do anything if we're changing state */
1095 if (enable != uaccess_flush)
1096 uaccess_flush_enable(enable);
1101 static int uaccess_flush_get(void *data, u64 *val)
1103 *val = uaccess_flush ? 1 : 0;
1107 DEFINE_SIMPLE_ATTRIBUTE(fops_uaccess_flush, uaccess_flush_get, uaccess_flush_set, "%llu\n");
1109 static __init int rfi_flush_debugfs_init(void)
1111 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
1112 debugfs_create_file("entry_flush", 0600, powerpc_debugfs_root, NULL, &fops_entry_flush);
1113 debugfs_create_file("uaccess_flush", 0600, powerpc_debugfs_root, NULL, &fops_uaccess_flush);
1116 device_initcall(rfi_flush_debugfs_init);
1118 #endif /* CONFIG_PPC_BOOK3S_64 */