2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
45 #include <linux/pkeys.h>
47 #include <asm/pgtable.h>
49 #include <asm/processor.h>
52 #include <asm/machdep.h>
54 #include <asm/runlatch.h>
55 #include <asm/syscalls.h>
56 #include <asm/switch_to.h>
58 #include <asm/debug.h>
60 #include <asm/firmware.h>
61 #include <asm/hw_irq.h>
63 #include <asm/code-patching.h>
65 #include <asm/livepatch.h>
66 #include <asm/cpu_has_feature.h>
67 #include <asm/asm-prototypes.h>
69 #include <linux/kprobes.h>
70 #include <linux/kdebug.h>
72 /* Transactional Memory debug */
74 #define TM_DEBUG(x...) printk(KERN_INFO x)
76 #define TM_DEBUG(x...) do { } while(0)
79 extern unsigned long _get_SP(void);
81 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
83 * Are we running in "Suspend disabled" mode? If so we have to block any
84 * sigreturn that would get us into suspended state, and we also warn in some
85 * other paths that we should never reach with suspend disabled.
87 bool tm_suspend_disabled __ro_after_init = false;
89 static void check_if_tm_restore_required(struct task_struct *tsk)
92 * If we are saving the current thread's registers, and the
93 * thread is in a transactional state, set the TIF_RESTORE_TM
94 * bit so that we know to restore the registers before
95 * returning to userspace.
97 if (tsk == current && tsk->thread.regs &&
98 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
99 !test_thread_flag(TIF_RESTORE_TM)) {
100 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
101 set_thread_flag(TIF_RESTORE_TM);
106 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
107 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
109 bool strict_msr_control;
110 EXPORT_SYMBOL(strict_msr_control);
112 static int __init enable_strict_msr_control(char *str)
114 strict_msr_control = true;
115 pr_info("Enabling strict facility control\n");
119 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
121 unsigned long msr_check_and_set(unsigned long bits)
123 unsigned long oldmsr = mfmsr();
124 unsigned long newmsr;
126 newmsr = oldmsr | bits;
129 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
133 if (oldmsr != newmsr)
138 EXPORT_SYMBOL_GPL(msr_check_and_set);
140 void __msr_check_and_clear(unsigned long bits)
142 unsigned long oldmsr = mfmsr();
143 unsigned long newmsr;
145 newmsr = oldmsr & ~bits;
148 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
152 if (oldmsr != newmsr)
155 EXPORT_SYMBOL(__msr_check_and_clear);
157 #ifdef CONFIG_PPC_FPU
158 static void __giveup_fpu(struct task_struct *tsk)
163 msr = tsk->thread.regs->msr;
164 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
166 if (cpu_has_feature(CPU_FTR_VSX))
169 tsk->thread.regs->msr = msr;
172 void giveup_fpu(struct task_struct *tsk)
174 check_if_tm_restore_required(tsk);
176 msr_check_and_set(MSR_FP);
178 msr_check_and_clear(MSR_FP);
180 EXPORT_SYMBOL(giveup_fpu);
183 * Make sure the floating-point register state in the
184 * the thread_struct is up to date for task tsk.
186 void flush_fp_to_thread(struct task_struct *tsk)
188 if (tsk->thread.regs) {
190 * We need to disable preemption here because if we didn't,
191 * another process could get scheduled after the regs->msr
192 * test but before we have finished saving the FP registers
193 * to the thread_struct. That process could take over the
194 * FPU, and then when we get scheduled again we would store
195 * bogus values for the remaining FP registers.
198 if (tsk->thread.regs->msr & MSR_FP) {
200 * This should only ever be called for current or
201 * for a stopped child process. Since we save away
202 * the FP register state on context switch,
203 * there is something wrong if a stopped child appears
204 * to still have its FP state in the CPU registers.
206 BUG_ON(tsk != current);
212 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
214 void enable_kernel_fp(void)
216 unsigned long cpumsr;
218 WARN_ON(preemptible());
220 cpumsr = msr_check_and_set(MSR_FP);
222 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
223 check_if_tm_restore_required(current);
225 * If a thread has already been reclaimed then the
226 * checkpointed registers are on the CPU but have definitely
227 * been saved by the reclaim code. Don't need to and *cannot*
228 * giveup as this would save to the 'live' structure not the
229 * checkpointed structure.
231 if (!MSR_TM_ACTIVE(cpumsr) &&
232 MSR_TM_ACTIVE(current->thread.regs->msr))
234 __giveup_fpu(current);
237 EXPORT_SYMBOL(enable_kernel_fp);
239 static int restore_fp(struct task_struct *tsk)
241 if (tsk->thread.load_fp) {
242 load_fp_state(¤t->thread.fp_state);
243 current->thread.load_fp++;
249 static int restore_fp(struct task_struct *tsk) { return 0; }
250 #endif /* CONFIG_PPC_FPU */
252 #ifdef CONFIG_ALTIVEC
253 #define loadvec(thr) ((thr).load_vec)
255 static void __giveup_altivec(struct task_struct *tsk)
260 msr = tsk->thread.regs->msr;
263 if (cpu_has_feature(CPU_FTR_VSX))
266 tsk->thread.regs->msr = msr;
269 void giveup_altivec(struct task_struct *tsk)
271 check_if_tm_restore_required(tsk);
273 msr_check_and_set(MSR_VEC);
274 __giveup_altivec(tsk);
275 msr_check_and_clear(MSR_VEC);
277 EXPORT_SYMBOL(giveup_altivec);
279 void enable_kernel_altivec(void)
281 unsigned long cpumsr;
283 WARN_ON(preemptible());
285 cpumsr = msr_check_and_set(MSR_VEC);
287 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
288 check_if_tm_restore_required(current);
290 * If a thread has already been reclaimed then the
291 * checkpointed registers are on the CPU but have definitely
292 * been saved by the reclaim code. Don't need to and *cannot*
293 * giveup as this would save to the 'live' structure not the
294 * checkpointed structure.
296 if (!MSR_TM_ACTIVE(cpumsr) &&
297 MSR_TM_ACTIVE(current->thread.regs->msr))
299 __giveup_altivec(current);
302 EXPORT_SYMBOL(enable_kernel_altivec);
305 * Make sure the VMX/Altivec register state in the
306 * the thread_struct is up to date for task tsk.
308 void flush_altivec_to_thread(struct task_struct *tsk)
310 if (tsk->thread.regs) {
312 if (tsk->thread.regs->msr & MSR_VEC) {
313 BUG_ON(tsk != current);
319 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
321 static int restore_altivec(struct task_struct *tsk)
323 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
324 load_vr_state(&tsk->thread.vr_state);
325 tsk->thread.used_vr = 1;
326 tsk->thread.load_vec++;
333 #define loadvec(thr) 0
334 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
335 #endif /* CONFIG_ALTIVEC */
338 static void __giveup_vsx(struct task_struct *tsk)
340 unsigned long msr = tsk->thread.regs->msr;
343 * We should never be ssetting MSR_VSX without also setting
346 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
348 /* __giveup_fpu will clear MSR_VSX */
352 __giveup_altivec(tsk);
355 static void giveup_vsx(struct task_struct *tsk)
357 check_if_tm_restore_required(tsk);
359 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
361 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
364 void enable_kernel_vsx(void)
366 unsigned long cpumsr;
368 WARN_ON(preemptible());
370 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
372 if (current->thread.regs &&
373 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
374 check_if_tm_restore_required(current);
376 * If a thread has already been reclaimed then the
377 * checkpointed registers are on the CPU but have definitely
378 * been saved by the reclaim code. Don't need to and *cannot*
379 * giveup as this would save to the 'live' structure not the
380 * checkpointed structure.
382 if (!MSR_TM_ACTIVE(cpumsr) &&
383 MSR_TM_ACTIVE(current->thread.regs->msr))
385 __giveup_vsx(current);
388 EXPORT_SYMBOL(enable_kernel_vsx);
390 void flush_vsx_to_thread(struct task_struct *tsk)
392 if (tsk->thread.regs) {
394 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
395 BUG_ON(tsk != current);
401 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
403 static int restore_vsx(struct task_struct *tsk)
405 if (cpu_has_feature(CPU_FTR_VSX)) {
406 tsk->thread.used_vsr = 1;
413 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
414 #endif /* CONFIG_VSX */
417 void giveup_spe(struct task_struct *tsk)
419 check_if_tm_restore_required(tsk);
421 msr_check_and_set(MSR_SPE);
423 msr_check_and_clear(MSR_SPE);
425 EXPORT_SYMBOL(giveup_spe);
427 void enable_kernel_spe(void)
429 WARN_ON(preemptible());
431 msr_check_and_set(MSR_SPE);
433 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
434 check_if_tm_restore_required(current);
435 __giveup_spe(current);
438 EXPORT_SYMBOL(enable_kernel_spe);
440 void flush_spe_to_thread(struct task_struct *tsk)
442 if (tsk->thread.regs) {
444 if (tsk->thread.regs->msr & MSR_SPE) {
445 BUG_ON(tsk != current);
446 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
452 #endif /* CONFIG_SPE */
454 static unsigned long msr_all_available;
456 static int __init init_msr_all_available(void)
458 #ifdef CONFIG_PPC_FPU
459 msr_all_available |= MSR_FP;
461 #ifdef CONFIG_ALTIVEC
462 if (cpu_has_feature(CPU_FTR_ALTIVEC))
463 msr_all_available |= MSR_VEC;
466 if (cpu_has_feature(CPU_FTR_VSX))
467 msr_all_available |= MSR_VSX;
470 if (cpu_has_feature(CPU_FTR_SPE))
471 msr_all_available |= MSR_SPE;
476 early_initcall(init_msr_all_available);
478 void giveup_all(struct task_struct *tsk)
480 unsigned long usermsr;
482 if (!tsk->thread.regs)
485 check_if_tm_restore_required(tsk);
487 usermsr = tsk->thread.regs->msr;
489 if ((usermsr & msr_all_available) == 0)
492 msr_check_and_set(msr_all_available);
494 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
496 #ifdef CONFIG_PPC_FPU
497 if (usermsr & MSR_FP)
500 #ifdef CONFIG_ALTIVEC
501 if (usermsr & MSR_VEC)
502 __giveup_altivec(tsk);
505 if (usermsr & MSR_SPE)
509 msr_check_and_clear(msr_all_available);
511 EXPORT_SYMBOL(giveup_all);
513 void restore_math(struct pt_regs *regs)
517 if (!MSR_TM_ACTIVE(regs->msr) &&
518 !current->thread.load_fp && !loadvec(current->thread))
522 msr_check_and_set(msr_all_available);
525 * Only reload if the bit is not set in the user MSR, the bit BEING set
526 * indicates that the registers are hot
528 if ((!(msr & MSR_FP)) && restore_fp(current))
529 msr |= MSR_FP | current->thread.fpexc_mode;
531 if ((!(msr & MSR_VEC)) && restore_altivec(current))
534 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
535 restore_vsx(current)) {
539 msr_check_and_clear(msr_all_available);
544 static void save_all(struct task_struct *tsk)
546 unsigned long usermsr;
548 if (!tsk->thread.regs)
551 usermsr = tsk->thread.regs->msr;
553 if ((usermsr & msr_all_available) == 0)
556 msr_check_and_set(msr_all_available);
558 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
560 if (usermsr & MSR_FP)
563 if (usermsr & MSR_VEC)
566 if (usermsr & MSR_SPE)
569 msr_check_and_clear(msr_all_available);
570 thread_pkey_regs_save(&tsk->thread);
573 void flush_all_to_thread(struct task_struct *tsk)
575 if (tsk->thread.regs) {
577 BUG_ON(tsk != current);
579 if (tsk->thread.regs->msr & MSR_SPE)
580 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
587 EXPORT_SYMBOL(flush_all_to_thread);
589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
590 void do_send_trap(struct pt_regs *regs, unsigned long address,
591 unsigned long error_code, int breakpt)
593 current->thread.trap_nr = TRAP_HWBKPT;
594 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
595 11, SIGSEGV) == NOTIFY_STOP)
598 /* Deliver the signal to userspace */
599 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
600 (void __user *)address);
602 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
603 void do_break (struct pt_regs *regs, unsigned long address,
604 unsigned long error_code)
608 current->thread.trap_nr = TRAP_HWBKPT;
609 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
610 11, SIGSEGV) == NOTIFY_STOP)
613 if (debugger_break_match(regs))
616 /* Clear the breakpoint */
617 hw_breakpoint_disable();
619 /* Deliver the signal to userspace */
620 clear_siginfo(&info);
621 info.si_signo = SIGTRAP;
623 info.si_code = TRAP_HWBKPT;
624 info.si_addr = (void __user *)address;
625 force_sig_info(SIGTRAP, &info, current);
627 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
629 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
631 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
633 * Set the debug registers back to their default "safe" values.
635 static void set_debug_reg_defaults(struct thread_struct *thread)
637 thread->debug.iac1 = thread->debug.iac2 = 0;
638 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
639 thread->debug.iac3 = thread->debug.iac4 = 0;
641 thread->debug.dac1 = thread->debug.dac2 = 0;
642 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
643 thread->debug.dvc1 = thread->debug.dvc2 = 0;
645 thread->debug.dbcr0 = 0;
648 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
650 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
651 DBCR1_IAC3US | DBCR1_IAC4US;
653 * Force Data Address Compare User/Supervisor bits to be User-only
654 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
656 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
658 thread->debug.dbcr1 = 0;
662 static void prime_debug_regs(struct debug_reg *debug)
665 * We could have inherited MSR_DE from userspace, since
666 * it doesn't get cleared on exception entry. Make sure
667 * MSR_DE is clear before we enable any debug events.
669 mtmsr(mfmsr() & ~MSR_DE);
671 mtspr(SPRN_IAC1, debug->iac1);
672 mtspr(SPRN_IAC2, debug->iac2);
673 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
674 mtspr(SPRN_IAC3, debug->iac3);
675 mtspr(SPRN_IAC4, debug->iac4);
677 mtspr(SPRN_DAC1, debug->dac1);
678 mtspr(SPRN_DAC2, debug->dac2);
679 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
680 mtspr(SPRN_DVC1, debug->dvc1);
681 mtspr(SPRN_DVC2, debug->dvc2);
683 mtspr(SPRN_DBCR0, debug->dbcr0);
684 mtspr(SPRN_DBCR1, debug->dbcr1);
686 mtspr(SPRN_DBCR2, debug->dbcr2);
690 * Unless neither the old or new thread are making use of the
691 * debug registers, set the debug registers from the values
692 * stored in the new thread.
694 void switch_booke_debug_regs(struct debug_reg *new_debug)
696 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
697 || (new_debug->dbcr0 & DBCR0_IDM))
698 prime_debug_regs(new_debug);
700 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
701 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
702 #ifndef CONFIG_HAVE_HW_BREAKPOINT
703 static void set_breakpoint(struct arch_hw_breakpoint *brk)
706 __set_breakpoint(brk);
710 static void set_debug_reg_defaults(struct thread_struct *thread)
712 thread->hw_brk.address = 0;
713 thread->hw_brk.type = 0;
714 if (ppc_breakpoint_available())
715 set_breakpoint(&thread->hw_brk);
717 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
718 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
720 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
721 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
723 mtspr(SPRN_DAC1, dabr);
724 #ifdef CONFIG_PPC_47x
729 #elif defined(CONFIG_PPC_BOOK3S)
730 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
732 mtspr(SPRN_DABR, dabr);
733 if (cpu_has_feature(CPU_FTR_DABRX))
734 mtspr(SPRN_DABRX, dabrx);
737 #elif defined(CONFIG_PPC_8xx)
738 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
740 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
741 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
742 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
744 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
746 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
748 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
751 mtspr(SPRN_LCTRL2, 0);
752 mtspr(SPRN_CMPE, addr);
753 mtspr(SPRN_CMPF, addr + 4);
754 mtspr(SPRN_LCTRL1, lctrl1);
755 mtspr(SPRN_LCTRL2, lctrl2);
760 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
766 static inline int set_dabr(struct arch_hw_breakpoint *brk)
768 unsigned long dabr, dabrx;
770 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
771 dabrx = ((brk->type >> 3) & 0x7);
774 return ppc_md.set_dabr(dabr, dabrx);
776 return __set_dabr(dabr, dabrx);
779 static inline int set_dawr(struct arch_hw_breakpoint *brk)
781 unsigned long dawr, dawrx, mrd;
785 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
786 << (63 - 58); //* read/write bits */
787 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
788 << (63 - 59); //* translate */
789 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
790 >> 3; //* PRIM bits */
791 /* dawr length is stored in field MDR bits 48:53. Matches range in
792 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
794 brk->len is in bytes.
795 This aligns up to double word size, shifts and does the bias.
797 mrd = ((brk->len + 7) >> 3) - 1;
798 dawrx |= (mrd & 0x3f) << (63 - 53);
801 return ppc_md.set_dawr(dawr, dawrx);
802 mtspr(SPRN_DAWR, dawr);
803 mtspr(SPRN_DAWRX, dawrx);
807 void __set_breakpoint(struct arch_hw_breakpoint *brk)
809 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk));
811 if (cpu_has_feature(CPU_FTR_DAWR))
814 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
818 // Shouldn't happen due to higher level checks
822 /* Check if we have DAWR or DABR hardware */
823 bool ppc_breakpoint_available(void)
825 if (cpu_has_feature(CPU_FTR_DAWR))
826 return true; /* POWER8 DAWR */
827 if (cpu_has_feature(CPU_FTR_ARCH_207S))
828 return false; /* POWER9 with DAWR disabled */
829 /* DABR: Everything but POWER8 and POWER9 */
832 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
834 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
835 struct arch_hw_breakpoint *b)
837 if (a->address != b->address)
839 if (a->type != b->type)
841 if (a->len != b->len)
846 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
848 static inline bool tm_enabled(struct task_struct *tsk)
850 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
853 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
856 * Use the current MSR TM suspended bit to track if we have
857 * checkpointed state outstanding.
858 * On signal delivery, we'd normally reclaim the checkpointed
859 * state to obtain stack pointer (see:get_tm_stackpointer()).
860 * This will then directly return to userspace without going
861 * through __switch_to(). However, if the stack frame is bad,
862 * we need to exit this thread which calls __switch_to() which
863 * will again attempt to reclaim the already saved tm state.
864 * Hence we need to check that we've not already reclaimed
866 * We do this using the current MSR, rather tracking it in
867 * some specific thread_struct bit, as it has the additional
868 * benefit of checking for a potential TM bad thing exception.
870 if (!MSR_TM_SUSPENDED(mfmsr()))
873 giveup_all(container_of(thr, struct task_struct, thread));
875 tm_reclaim(thr, cause);
878 * If we are in a transaction and FP is off then we can't have
879 * used FP inside that transaction. Hence the checkpointed
880 * state is the same as the live state. We need to copy the
881 * live state to the checkpointed state so that when the
882 * transaction is restored, the checkpointed state is correct
883 * and the aborted transaction sees the correct state. We use
884 * ckpt_regs.msr here as that's what tm_reclaim will use to
885 * determine if it's going to write the checkpointed state or
886 * not. So either this will write the checkpointed registers,
887 * or reclaim will. Similarly for VMX.
889 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
890 memcpy(&thr->ckfp_state, &thr->fp_state,
891 sizeof(struct thread_fp_state));
892 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
893 memcpy(&thr->ckvr_state, &thr->vr_state,
894 sizeof(struct thread_vr_state));
897 void tm_reclaim_current(uint8_t cause)
900 tm_reclaim_thread(¤t->thread, cause);
903 static inline void tm_reclaim_task(struct task_struct *tsk)
905 /* We have to work out if we're switching from/to a task that's in the
906 * middle of a transaction.
908 * In switching we need to maintain a 2nd register state as
909 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
910 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
913 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
915 struct thread_struct *thr = &tsk->thread;
920 if (!MSR_TM_ACTIVE(thr->regs->msr))
921 goto out_and_saveregs;
923 WARN_ON(tm_suspend_disabled);
925 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
926 "ccr=%lx, msr=%lx, trap=%lx)\n",
927 tsk->pid, thr->regs->nip,
928 thr->regs->ccr, thr->regs->msr,
931 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
933 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
937 /* Always save the regs here, even if a transaction's not active.
938 * This context-switches a thread's TM info SPRs. We do it here to
939 * be consistent with the restore path (in recheckpoint) which
940 * cannot happen later in _switch().
945 extern void __tm_recheckpoint(struct thread_struct *thread);
947 void tm_recheckpoint(struct thread_struct *thread)
951 if (!(thread->regs->msr & MSR_TM))
954 /* We really can't be interrupted here as the TEXASR registers can't
955 * change and later in the trecheckpoint code, we have a userspace R1.
956 * So let's hard disable over this region.
958 local_irq_save(flags);
961 /* The TM SPRs are restored here, so that TEXASR.FS can be set
962 * before the trecheckpoint and no explosion occurs.
964 tm_restore_sprs(thread);
966 __tm_recheckpoint(thread);
968 local_irq_restore(flags);
971 static inline void tm_recheckpoint_new_task(struct task_struct *new)
973 if (!cpu_has_feature(CPU_FTR_TM))
976 /* Recheckpoint the registers of the thread we're about to switch to.
978 * If the task was using FP, we non-lazily reload both the original and
979 * the speculative FP register states. This is because the kernel
980 * doesn't see if/when a TM rollback occurs, so if we take an FP
981 * unavailable later, we are unable to determine which set of FP regs
982 * need to be restored.
984 if (!tm_enabled(new))
987 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
988 tm_restore_sprs(&new->thread);
991 /* Recheckpoint to restore original checkpointed register state. */
992 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
993 new->pid, new->thread.regs->msr);
995 tm_recheckpoint(&new->thread);
998 * The checkpointed state has been restored but the live state has
999 * not, ensure all the math functionality is turned off to trigger
1000 * restore_math() to reload.
1002 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1004 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1005 "(kernel msr 0x%lx)\n",
1009 static inline void __switch_to_tm(struct task_struct *prev,
1010 struct task_struct *new)
1012 if (cpu_has_feature(CPU_FTR_TM)) {
1013 if (tm_enabled(prev) || tm_enabled(new))
1016 if (tm_enabled(prev)) {
1017 prev->thread.load_tm++;
1018 tm_reclaim_task(prev);
1019 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1020 prev->thread.regs->msr &= ~MSR_TM;
1023 tm_recheckpoint_new_task(new);
1028 * This is called if we are on the way out to userspace and the
1029 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1030 * FP and/or vector state and does so if necessary.
1031 * If userspace is inside a transaction (whether active or
1032 * suspended) and FP/VMX/VSX instructions have ever been enabled
1033 * inside that transaction, then we have to keep them enabled
1034 * and keep the FP/VMX/VSX state loaded while ever the transaction
1035 * continues. The reason is that if we didn't, and subsequently
1036 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1037 * we don't know whether it's the same transaction, and thus we
1038 * don't know which of the checkpointed state and the transactional
1041 void restore_tm_state(struct pt_regs *regs)
1043 unsigned long msr_diff;
1046 * This is the only moment we should clear TIF_RESTORE_TM as
1047 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1048 * again, anything else could lead to an incorrect ckpt_msr being
1049 * saved and therefore incorrect signal contexts.
1051 clear_thread_flag(TIF_RESTORE_TM);
1052 if (!MSR_TM_ACTIVE(regs->msr))
1055 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1056 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1058 /* Ensure that restore_math() will restore */
1059 if (msr_diff & MSR_FP)
1060 current->thread.load_fp = 1;
1061 #ifdef CONFIG_ALTIVEC
1062 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1063 current->thread.load_vec = 1;
1067 regs->msr |= msr_diff;
1071 #define tm_recheckpoint_new_task(new)
1072 #define __switch_to_tm(prev, new)
1073 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1075 static inline void save_sprs(struct thread_struct *t)
1077 #ifdef CONFIG_ALTIVEC
1078 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1079 t->vrsave = mfspr(SPRN_VRSAVE);
1081 #ifdef CONFIG_PPC_BOOK3S_64
1082 if (cpu_has_feature(CPU_FTR_DSCR))
1083 t->dscr = mfspr(SPRN_DSCR);
1085 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1086 t->bescr = mfspr(SPRN_BESCR);
1087 t->ebbhr = mfspr(SPRN_EBBHR);
1088 t->ebbrr = mfspr(SPRN_EBBRR);
1090 t->fscr = mfspr(SPRN_FSCR);
1093 * Note that the TAR is not available for use in the kernel.
1094 * (To provide this, the TAR should be backed up/restored on
1095 * exception entry/exit instead, and be in pt_regs. FIXME,
1096 * this should be in pt_regs anyway (for debug).)
1098 t->tar = mfspr(SPRN_TAR);
1102 thread_pkey_regs_save(t);
1105 static inline void restore_sprs(struct thread_struct *old_thread,
1106 struct thread_struct *new_thread)
1108 #ifdef CONFIG_ALTIVEC
1109 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1110 old_thread->vrsave != new_thread->vrsave)
1111 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1113 #ifdef CONFIG_PPC_BOOK3S_64
1114 if (cpu_has_feature(CPU_FTR_DSCR)) {
1115 u64 dscr = get_paca()->dscr_default;
1116 if (new_thread->dscr_inherit)
1117 dscr = new_thread->dscr;
1119 if (old_thread->dscr != dscr)
1120 mtspr(SPRN_DSCR, dscr);
1123 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1124 if (old_thread->bescr != new_thread->bescr)
1125 mtspr(SPRN_BESCR, new_thread->bescr);
1126 if (old_thread->ebbhr != new_thread->ebbhr)
1127 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1128 if (old_thread->ebbrr != new_thread->ebbrr)
1129 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1131 if (old_thread->fscr != new_thread->fscr)
1132 mtspr(SPRN_FSCR, new_thread->fscr);
1134 if (old_thread->tar != new_thread->tar)
1135 mtspr(SPRN_TAR, new_thread->tar);
1138 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1139 old_thread->tidr != new_thread->tidr)
1140 mtspr(SPRN_TIDR, new_thread->tidr);
1143 thread_pkey_regs_restore(new_thread, old_thread);
1146 #ifdef CONFIG_PPC_BOOK3S_64
1148 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1151 struct task_struct *__switch_to(struct task_struct *prev,
1152 struct task_struct *new)
1154 struct thread_struct *new_thread, *old_thread;
1155 struct task_struct *last;
1156 #ifdef CONFIG_PPC_BOOK3S_64
1157 struct ppc64_tlb_batch *batch;
1160 new_thread = &new->thread;
1161 old_thread = ¤t->thread;
1163 WARN_ON(!irqs_disabled());
1165 #ifdef CONFIG_PPC_BOOK3S_64
1166 batch = this_cpu_ptr(&ppc64_tlb_batch);
1167 if (batch->active) {
1168 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1170 __flush_tlb_pending(batch);
1173 #endif /* CONFIG_PPC_BOOK3S_64 */
1175 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1176 switch_booke_debug_regs(&new->thread.debug);
1179 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1182 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1183 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk)))
1184 __set_breakpoint(&new->thread.hw_brk);
1185 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1189 * We need to save SPRs before treclaim/trecheckpoint as these will
1190 * change a number of them.
1192 save_sprs(&prev->thread);
1194 /* Save FPU, Altivec, VSX and SPE state */
1197 __switch_to_tm(prev, new);
1199 if (!radix_enabled()) {
1201 * We can't take a PMU exception inside _switch() since there
1202 * is a window where the kernel stack SLB and the kernel stack
1203 * are out of sync. Hard disable here.
1209 * Call restore_sprs() before calling _switch(). If we move it after
1210 * _switch() then we miss out on calling it for new tasks. The reason
1211 * for this is we manually create a stack frame for new tasks that
1212 * directly returns through ret_from_fork() or
1213 * ret_from_kernel_thread(). See copy_thread() for details.
1215 restore_sprs(old_thread, new_thread);
1217 last = _switch(old_thread, new_thread);
1219 #ifdef CONFIG_PPC_BOOK3S_64
1220 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1221 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1222 batch = this_cpu_ptr(&ppc64_tlb_batch);
1226 if (current_thread_info()->task->thread.regs) {
1227 restore_math(current_thread_info()->task->thread.regs);
1230 * The copy-paste buffer can only store into foreign real
1231 * addresses, so unprivileged processes can not see the
1232 * data or use it in any way unless they have foreign real
1233 * mappings. If the new process has the foreign real address
1234 * mappings, we must issue a cp_abort to clear any state and
1235 * prevent snooping, corruption or a covert channel.
1237 if (current_thread_info()->task->thread.used_vas)
1238 asm volatile(PPC_CP_ABORT);
1240 #endif /* CONFIG_PPC_BOOK3S_64 */
1245 static int instructions_to_print = 16;
1247 static void show_instructions(struct pt_regs *regs)
1250 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1253 printk("Instruction dump:");
1255 for (i = 0; i < instructions_to_print; i++) {
1261 #if !defined(CONFIG_BOOKE)
1262 /* If executing with the IMMU off, adjust pc rather
1263 * than print XXXXXXXX.
1265 if (!(regs->msr & MSR_IR))
1266 pc = (unsigned long)phys_to_virt(pc);
1269 if (!__kernel_text_address(pc) ||
1270 probe_kernel_address((unsigned int __user *)pc, instr)) {
1271 pr_cont("XXXXXXXX ");
1273 if (regs->nip == pc)
1274 pr_cont("<%08x> ", instr);
1276 pr_cont("%08x ", instr);
1285 void show_user_instructions(struct pt_regs *regs)
1290 pc = regs->nip - (instructions_to_print * 3 / 4 * sizeof(int));
1293 * Make sure the NIP points at userspace, not kernel text/data or
1296 if (!__access_ok(pc, instructions_to_print * sizeof(int), USER_DS)) {
1297 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1298 current->comm, current->pid);
1302 pr_info("%s[%d]: code: ", current->comm, current->pid);
1304 for (i = 0; i < instructions_to_print; i++) {
1307 if (!(i % 8) && (i > 0)) {
1309 pr_info("%s[%d]: code: ", current->comm, current->pid);
1312 if (probe_kernel_address((unsigned int __user *)pc, instr)) {
1313 pr_cont("XXXXXXXX ");
1315 if (regs->nip == pc)
1316 pr_cont("<%08x> ", instr);
1318 pr_cont("%08x ", instr);
1332 static struct regbit msr_bits[] = {
1333 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1355 #ifndef CONFIG_BOOKE
1362 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1366 for (; bits->bit; ++bits)
1367 if (val & bits->bit) {
1368 pr_cont("%s%s", s, bits->name);
1373 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1374 static struct regbit msr_tm_bits[] = {
1381 static void print_tm_bits(unsigned long val)
1384 * This only prints something if at least one of the TM bit is set.
1385 * Inside the TM[], the output means:
1386 * E: Enabled (bit 32)
1387 * S: Suspended (bit 33)
1388 * T: Transactional (bit 34)
1390 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1392 print_bits(val, msr_tm_bits, "");
1397 static void print_tm_bits(unsigned long val) {}
1400 static void print_msr_bits(unsigned long val)
1403 print_bits(val, msr_bits, ",");
1409 #define REG "%016lx"
1410 #define REGS_PER_LINE 4
1411 #define LAST_VOLATILE 13
1414 #define REGS_PER_LINE 8
1415 #define LAST_VOLATILE 12
1418 void show_regs(struct pt_regs * regs)
1422 show_regs_print_info(KERN_DEFAULT);
1424 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1425 regs->nip, regs->link, regs->ctr);
1426 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1427 regs, regs->trap, print_tainted(), init_utsname()->release);
1428 printk("MSR: "REG" ", regs->msr);
1429 print_msr_bits(regs->msr);
1430 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1432 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1433 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1434 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1435 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1436 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1438 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1441 pr_cont("IRQMASK: %lx ", regs->softe);
1443 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1444 if (MSR_TM_ACTIVE(regs->msr))
1445 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1448 for (i = 0; i < 32; i++) {
1449 if ((i % REGS_PER_LINE) == 0)
1450 pr_cont("\nGPR%02d: ", i);
1451 pr_cont(REG " ", regs->gpr[i]);
1452 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1456 #ifdef CONFIG_KALLSYMS
1458 * Lookup NIP late so we have the best change of getting the
1459 * above info out without failing
1461 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1462 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1464 show_stack(current, (unsigned long *) regs->gpr[1]);
1465 if (!user_mode(regs))
1466 show_instructions(regs);
1469 void flush_thread(void)
1471 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1472 flush_ptrace_hw_breakpoint(current);
1473 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1474 set_debug_reg_defaults(¤t->thread);
1475 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1478 int set_thread_uses_vas(void)
1480 #ifdef CONFIG_PPC_BOOK3S_64
1481 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1484 current->thread.used_vas = 1;
1487 * Even a process that has no foreign real address mapping can use
1488 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1489 * to clear any pending COPY and prevent a covert channel.
1491 * __switch_to() will issue CP_ABORT on future context switches.
1493 asm volatile(PPC_CP_ABORT);
1495 #endif /* CONFIG_PPC_BOOK3S_64 */
1501 * Assign a TIDR (thread ID) for task @t and set it in the thread
1502 * structure. For now, we only support setting TIDR for 'current' task.
1504 * Since the TID value is a truncated form of it PID, it is possible
1505 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1506 * that 2 threads share the same TID and are waiting, one of the following
1507 * cases will happen:
1509 * 1. The correct thread is running, the wrong thread is not
1510 * In this situation, the correct thread is woken and proceeds to pass it's
1513 * 2. Neither threads are running
1514 * In this situation, neither thread will be woken. When scheduled, the waiting
1515 * threads will execute either a wait, which will return immediately, followed
1516 * by a condition check, which will pass for the correct thread and fail
1517 * for the wrong thread, or they will execute the condition check immediately.
1519 * 3. The wrong thread is running, the correct thread is not
1520 * The wrong thread will be woken, but will fail it's condition check and
1521 * re-execute wait. The correct thread, when scheduled, will execute either
1522 * it's condition check (which will pass), or wait, which returns immediately
1523 * when called the first time after the thread is scheduled, followed by it's
1524 * condition check (which will pass).
1526 * 4. Both threads are running
1527 * Both threads will be woken. The wrong thread will fail it's condition check
1528 * and execute another wait, while the correct thread will pass it's condition
1531 * @t: the task to set the thread ID for
1533 int set_thread_tidr(struct task_struct *t)
1535 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1544 t->thread.tidr = (u16)task_pid_nr(t);
1545 mtspr(SPRN_TIDR, t->thread.tidr);
1549 EXPORT_SYMBOL_GPL(set_thread_tidr);
1551 #endif /* CONFIG_PPC64 */
1554 release_thread(struct task_struct *t)
1559 * this gets called so that we can store coprocessor state into memory and
1560 * copy the current task into the new thread.
1562 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1564 flush_all_to_thread(src);
1566 * Flush TM state out so we can copy it. __switch_to_tm() does this
1567 * flush but it removes the checkpointed state from the current CPU and
1568 * transitions the CPU out of TM mode. Hence we need to call
1569 * tm_recheckpoint_new_task() (on the same task) to restore the
1570 * checkpointed state back and the TM mode.
1572 * Can't pass dst because it isn't ready. Doesn't matter, passing
1573 * dst is only important for __switch_to()
1575 __switch_to_tm(src, src);
1579 clear_task_ebb(dst);
1584 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1586 #ifdef CONFIG_PPC_BOOK3S_64
1587 unsigned long sp_vsid;
1588 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1590 if (radix_enabled())
1593 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1594 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1595 << SLB_VSID_SHIFT_1T;
1597 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1599 sp_vsid |= SLB_VSID_KERNEL | llp;
1600 p->thread.ksp_vsid = sp_vsid;
1609 * Copy architecture-specific thread state
1611 int copy_thread(unsigned long clone_flags, unsigned long usp,
1612 unsigned long kthread_arg, struct task_struct *p)
1614 struct pt_regs *childregs, *kregs;
1615 extern void ret_from_fork(void);
1616 extern void ret_from_kernel_thread(void);
1618 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1619 struct thread_info *ti = task_thread_info(p);
1621 klp_init_thread_info(ti);
1623 /* Copy registers */
1624 sp -= sizeof(struct pt_regs);
1625 childregs = (struct pt_regs *) sp;
1626 if (unlikely(p->flags & PF_KTHREAD)) {
1628 memset(childregs, 0, sizeof(struct pt_regs));
1629 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1632 childregs->gpr[14] = ppc_function_entry((void *)usp);
1634 clear_tsk_thread_flag(p, TIF_32BIT);
1635 childregs->softe = IRQS_ENABLED;
1637 childregs->gpr[15] = kthread_arg;
1638 p->thread.regs = NULL; /* no user register state */
1639 ti->flags |= _TIF_RESTOREALL;
1640 f = ret_from_kernel_thread;
1643 struct pt_regs *regs = current_pt_regs();
1644 CHECK_FULL_REGS(regs);
1647 childregs->gpr[1] = usp;
1648 p->thread.regs = childregs;
1649 childregs->gpr[3] = 0; /* Result from fork() */
1650 if (clone_flags & CLONE_SETTLS) {
1652 if (!is_32bit_task())
1653 childregs->gpr[13] = childregs->gpr[6];
1656 childregs->gpr[2] = childregs->gpr[6];
1661 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1662 sp -= STACK_FRAME_OVERHEAD;
1665 * The way this works is that at some point in the future
1666 * some task will call _switch to switch to the new task.
1667 * That will pop off the stack frame created below and start
1668 * the new task running at ret_from_fork. The new task will
1669 * do some house keeping and then return from the fork or clone
1670 * system call, using the stack frame created above.
1672 ((unsigned long *)sp)[0] = 0;
1673 sp -= sizeof(struct pt_regs);
1674 kregs = (struct pt_regs *) sp;
1675 sp -= STACK_FRAME_OVERHEAD;
1678 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1679 _ALIGN_UP(sizeof(struct thread_info), 16);
1681 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1682 p->thread.ptrace_bps[0] = NULL;
1685 p->thread.fp_save_area = NULL;
1686 #ifdef CONFIG_ALTIVEC
1687 p->thread.vr_save_area = NULL;
1690 setup_ksp_vsid(p, sp);
1693 if (cpu_has_feature(CPU_FTR_DSCR)) {
1694 p->thread.dscr_inherit = current->thread.dscr_inherit;
1695 p->thread.dscr = mfspr(SPRN_DSCR);
1697 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1698 p->thread.ppr = INIT_PPR;
1702 kregs->nip = ppc_function_entry(f);
1707 * Set up a thread for executing a new program
1709 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1712 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1716 * If we exec out of a kernel thread then thread.regs will not be
1719 if (!current->thread.regs) {
1720 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1721 current->thread.regs = regs - 1;
1724 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1726 * Clear any transactional state, we're exec()ing. The cause is
1727 * not important as there will never be a recheckpoint so it's not
1730 if (MSR_TM_SUSPENDED(mfmsr()))
1731 tm_reclaim_current(0);
1734 memset(®s->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
1742 * We have just cleared all the nonvolatile GPRs, so make
1743 * FULL_REGS(regs) return true. This is necessary to allow
1744 * ptrace to examine the thread immediately after exec.
1751 regs->msr = MSR_USER;
1753 if (!is_32bit_task()) {
1754 unsigned long entry;
1756 if (is_elf2_task()) {
1757 /* Look ma, no function descriptors! */
1762 * The latest iteration of the ABI requires that when
1763 * calling a function (at its global entry point),
1764 * the caller must ensure r12 holds the entry point
1765 * address (so that the function can quickly
1766 * establish addressability).
1768 regs->gpr[12] = start;
1769 /* Make sure that's restored on entry to userspace. */
1770 set_thread_flag(TIF_RESTOREALL);
1774 /* start is a relocated pointer to the function
1775 * descriptor for the elf _start routine. The first
1776 * entry in the function descriptor is the entry
1777 * address of _start and the second entry is the TOC
1778 * value we need to use.
1780 __get_user(entry, (unsigned long __user *)start);
1781 __get_user(toc, (unsigned long __user *)start+1);
1783 /* Check whether the e_entry function descriptor entries
1784 * need to be relocated before we can use them.
1786 if (load_addr != 0) {
1793 regs->msr = MSR_USER64;
1797 regs->msr = MSR_USER32;
1801 current->thread.used_vsr = 0;
1803 current->thread.load_fp = 0;
1804 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1805 current->thread.fp_save_area = NULL;
1806 #ifdef CONFIG_ALTIVEC
1807 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1808 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1809 current->thread.vr_save_area = NULL;
1810 current->thread.vrsave = 0;
1811 current->thread.used_vr = 0;
1812 current->thread.load_vec = 0;
1813 #endif /* CONFIG_ALTIVEC */
1815 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1816 current->thread.acc = 0;
1817 current->thread.spefscr = 0;
1818 current->thread.used_spe = 0;
1819 #endif /* CONFIG_SPE */
1820 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1821 current->thread.tm_tfhar = 0;
1822 current->thread.tm_texasr = 0;
1823 current->thread.tm_tfiar = 0;
1824 current->thread.load_tm = 0;
1825 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1827 thread_pkey_regs_init(¤t->thread);
1829 EXPORT_SYMBOL(start_thread);
1831 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1832 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1834 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1836 struct pt_regs *regs = tsk->thread.regs;
1838 /* This is a bit hairy. If we are an SPE enabled processor
1839 * (have embedded fp) we store the IEEE exception enable flags in
1840 * fpexc_mode. fpexc_mode is also used for setting FP exception
1841 * mode (asyn, precise, disabled) for 'Classic' FP. */
1842 if (val & PR_FP_EXC_SW_ENABLE) {
1844 if (cpu_has_feature(CPU_FTR_SPE)) {
1846 * When the sticky exception bits are set
1847 * directly by userspace, it must call prctl
1848 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1849 * in the existing prctl settings) or
1850 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1851 * the bits being set). <fenv.h> functions
1852 * saving and restoring the whole
1853 * floating-point environment need to do so
1854 * anyway to restore the prctl settings from
1855 * the saved environment.
1857 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1858 tsk->thread.fpexc_mode = val &
1859 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1869 /* on a CONFIG_SPE this does not hurt us. The bits that
1870 * __pack_fe01 use do not overlap with bits used for
1871 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1872 * on CONFIG_SPE implementations are reserved so writing to
1873 * them does not change anything */
1874 if (val > PR_FP_EXC_PRECISE)
1876 tsk->thread.fpexc_mode = __pack_fe01(val);
1877 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1878 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1879 | tsk->thread.fpexc_mode;
1883 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1887 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1889 if (cpu_has_feature(CPU_FTR_SPE)) {
1891 * When the sticky exception bits are set
1892 * directly by userspace, it must call prctl
1893 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1894 * in the existing prctl settings) or
1895 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1896 * the bits being set). <fenv.h> functions
1897 * saving and restoring the whole
1898 * floating-point environment need to do so
1899 * anyway to restore the prctl settings from
1900 * the saved environment.
1902 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1903 val = tsk->thread.fpexc_mode;
1910 val = __unpack_fe01(tsk->thread.fpexc_mode);
1911 return put_user(val, (unsigned int __user *) adr);
1914 int set_endian(struct task_struct *tsk, unsigned int val)
1916 struct pt_regs *regs = tsk->thread.regs;
1918 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1919 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1925 if (val == PR_ENDIAN_BIG)
1926 regs->msr &= ~MSR_LE;
1927 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1928 regs->msr |= MSR_LE;
1935 int get_endian(struct task_struct *tsk, unsigned long adr)
1937 struct pt_regs *regs = tsk->thread.regs;
1940 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1941 !cpu_has_feature(CPU_FTR_REAL_LE))
1947 if (regs->msr & MSR_LE) {
1948 if (cpu_has_feature(CPU_FTR_REAL_LE))
1949 val = PR_ENDIAN_LITTLE;
1951 val = PR_ENDIAN_PPC_LITTLE;
1953 val = PR_ENDIAN_BIG;
1955 return put_user(val, (unsigned int __user *)adr);
1958 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1960 tsk->thread.align_ctl = val;
1964 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1966 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1969 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1970 unsigned long nbytes)
1972 unsigned long stack_page;
1973 unsigned long cpu = task_cpu(p);
1976 * Avoid crashing if the stack has overflowed and corrupted
1977 * task_cpu(p), which is in the thread_info struct.
1979 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1980 stack_page = (unsigned long) hardirq_ctx[cpu];
1981 if (sp >= stack_page + sizeof(struct thread_struct)
1982 && sp <= stack_page + THREAD_SIZE - nbytes)
1985 stack_page = (unsigned long) softirq_ctx[cpu];
1986 if (sp >= stack_page + sizeof(struct thread_struct)
1987 && sp <= stack_page + THREAD_SIZE - nbytes)
1993 int validate_sp(unsigned long sp, struct task_struct *p,
1994 unsigned long nbytes)
1996 unsigned long stack_page = (unsigned long)task_stack_page(p);
1998 if (sp >= stack_page + sizeof(struct thread_struct)
1999 && sp <= stack_page + THREAD_SIZE - nbytes)
2002 return valid_irq_stack(sp, p, nbytes);
2005 EXPORT_SYMBOL(validate_sp);
2007 unsigned long get_wchan(struct task_struct *p)
2009 unsigned long ip, sp;
2012 if (!p || p == current || p->state == TASK_RUNNING)
2016 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2020 sp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
2021 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2022 p->state == TASK_RUNNING)
2025 ip = READ_ONCE_NOCHECK(((unsigned long *)sp)[STACK_FRAME_LR_SAVE]);
2026 if (!in_sched_functions(ip))
2029 } while (count++ < 16);
2033 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2035 void show_stack(struct task_struct *tsk, unsigned long *stack)
2037 unsigned long sp, ip, lr, newsp;
2040 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2041 int curr_frame = current->curr_ret_stack;
2042 extern void return_to_handler(void);
2043 unsigned long rth = (unsigned long)return_to_handler;
2046 sp = (unsigned long) stack;
2051 sp = current_stack_pointer();
2053 sp = tsk->thread.ksp;
2057 printk("Call Trace:\n");
2059 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2062 stack = (unsigned long *) sp;
2064 ip = stack[STACK_FRAME_LR_SAVE];
2065 if (!firstframe || ip != lr) {
2066 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2067 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2068 if ((ip == rth) && curr_frame >= 0) {
2070 (void *)current->ret_stack[curr_frame].ret);
2075 pr_cont(" (unreliable)");
2081 * See if this is an exception frame.
2082 * We look for the "regshere" marker in the current frame.
2084 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2085 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2086 struct pt_regs *regs = (struct pt_regs *)
2087 (sp + STACK_FRAME_OVERHEAD);
2089 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2090 regs->trap, (void *)regs->nip, (void *)lr);
2095 } while (count++ < kstack_depth_to_print);
2099 /* Called with hard IRQs off */
2100 void notrace __ppc64_runlatch_on(void)
2102 struct thread_info *ti = current_thread_info();
2104 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2106 * Least significant bit (RUN) is the only writable bit of
2107 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2108 * earliest ISA where this is the case, but it's convenient.
2110 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2115 * Some architectures (e.g., Cell) have writable fields other
2116 * than RUN, so do the read-modify-write.
2118 ctrl = mfspr(SPRN_CTRLF);
2119 ctrl |= CTRL_RUNLATCH;
2120 mtspr(SPRN_CTRLT, ctrl);
2123 ti->local_flags |= _TLF_RUNLATCH;
2126 /* Called with hard IRQs off */
2127 void notrace __ppc64_runlatch_off(void)
2129 struct thread_info *ti = current_thread_info();
2131 ti->local_flags &= ~_TLF_RUNLATCH;
2133 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2134 mtspr(SPRN_CTRLT, 0);
2138 ctrl = mfspr(SPRN_CTRLF);
2139 ctrl &= ~CTRL_RUNLATCH;
2140 mtspr(SPRN_CTRLT, ctrl);
2143 #endif /* CONFIG_PPC64 */
2145 unsigned long arch_align_stack(unsigned long sp)
2147 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2148 sp -= get_random_int() & ~PAGE_MASK;
2152 static inline unsigned long brk_rnd(void)
2154 unsigned long rnd = 0;
2156 /* 8MB for 32bit, 1GB for 64bit */
2157 if (is_32bit_task())
2158 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2160 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2162 return rnd << PAGE_SHIFT;
2165 unsigned long arch_randomize_brk(struct mm_struct *mm)
2167 unsigned long base = mm->brk;
2170 #ifdef CONFIG_PPC_BOOK3S_64
2172 * If we are using 1TB segments and we are allowed to randomise
2173 * the heap, we can put it above 1TB so it is backed by a 1TB
2174 * segment. Otherwise the heap will be in the bottom 1TB
2175 * which always uses 256MB segments and this may result in a
2176 * performance penalty. We don't need to worry about radix. For
2177 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2179 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2180 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2183 ret = PAGE_ALIGN(base + brk_rnd());