2 * Linux performance counter support for MIPS.
4 * Copyright (C) 2010 MIPS Technologies, Inc.
5 * Copyright (C) 2011 Cavium Networks, Inc.
6 * Author: Deng-Cheng Zhu
8 * This code is based on the implementation for ARM, which is in turn
9 * based on the sparc64 perf event code and the x86 code. Performance
10 * counter access is based on the MIPS Oprofile code. And the callchain
11 * support references the code of MIPS stacktrace.c.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/cpumask.h>
19 #include <linux/interrupt.h>
20 #include <linux/smp.h>
21 #include <linux/kernel.h>
22 #include <linux/perf_event.h>
23 #include <linux/uaccess.h>
26 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
28 #include <asm/time.h> /* For perf_irq */
30 #define MIPS_MAX_HWEVENTS 4
31 #define MIPS_TCS_PER_COUNTER 2
32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
34 struct cpu_hw_events {
35 /* Array of events on this cpu. */
36 struct perf_event *events[MIPS_MAX_HWEVENTS];
39 * Set the bit (indexed by the counter number) when the counter
40 * is used for an event.
42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
45 * Software copy of the control register for each performance counter.
46 * MIPS CPUs vary in performance counters. They use this differently,
47 * and even may not use it.
49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 /* The description of MIPS performance events. */
56 struct mips_perf_event {
57 unsigned int event_id;
59 * MIPS performance counters are indexed starting from 0.
60 * CNTR_EVEN indicates the indexes of the counters to be used are
63 unsigned int cntr_mask;
64 #define CNTR_EVEN 0x55555555
65 #define CNTR_ODD 0xaaaaaaaa
66 #define CNTR_ALL 0xffffffff
74 static struct mips_perf_event raw_event;
75 static DEFINE_MUTEX(raw_event_mutex);
77 #define C(x) PERF_COUNT_HW_CACHE_##x
85 u64 (*read_counter)(unsigned int idx);
86 void (*write_counter)(unsigned int idx, u64 val);
87 const struct mips_perf_event *(*map_raw_event)(u64 config);
88 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
89 const struct mips_perf_event (*cache_event_map)
90 [PERF_COUNT_HW_CACHE_MAX]
91 [PERF_COUNT_HW_CACHE_OP_MAX]
92 [PERF_COUNT_HW_CACHE_RESULT_MAX];
93 unsigned int num_counters;
96 static struct mips_pmu mipspmu;
98 #define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
100 #define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
102 #ifdef CONFIG_CPU_BMIPS5000
103 #define M_PERFCTL_MT_EN(filter) 0
104 #else /* !CONFIG_CPU_BMIPS5000 */
105 #define M_PERFCTL_MT_EN(filter) (filter)
106 #endif /* CONFIG_CPU_BMIPS5000 */
108 #define M_TC_EN_ALL M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
109 #define M_TC_EN_VPE M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
110 #define M_TC_EN_TC M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
112 #define M_PERFCTL_COUNT_EVENT_WHENEVER (MIPS_PERFCTRL_EXL | \
118 #ifdef CONFIG_MIPS_MT_SMP
119 #define M_PERFCTL_CONFIG_MASK 0x3fff801f
121 #define M_PERFCTL_CONFIG_MASK 0x1f
125 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
126 static DEFINE_RWLOCK(pmuint_rwlock);
128 #if defined(CONFIG_CPU_BMIPS5000)
129 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
130 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
132 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
133 0 : cpu_vpe_id(¤t_cpu_data))
136 /* Copied from op_model_mipsxx.c */
137 static unsigned int vpe_shift(void)
139 if (num_possible_cpus() > 1)
145 static unsigned int counters_total_to_per_cpu(unsigned int counters)
147 return counters >> vpe_shift();
150 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
153 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
155 static void resume_local_counters(void);
156 static void pause_local_counters(void);
157 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
158 static int mipsxx_pmu_handle_shared_irq(void);
160 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
167 static u64 mipsxx_pmu_read_counter(unsigned int idx)
169 idx = mipsxx_pmu_swizzle_perf_idx(idx);
174 * The counters are unsigned, we must cast to truncate
177 return (u32)read_c0_perfcntr0();
179 return (u32)read_c0_perfcntr1();
181 return (u32)read_c0_perfcntr2();
183 return (u32)read_c0_perfcntr3();
185 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
190 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
192 idx = mipsxx_pmu_swizzle_perf_idx(idx);
196 return read_c0_perfcntr0_64();
198 return read_c0_perfcntr1_64();
200 return read_c0_perfcntr2_64();
202 return read_c0_perfcntr3_64();
204 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
209 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
211 idx = mipsxx_pmu_swizzle_perf_idx(idx);
215 write_c0_perfcntr0(val);
218 write_c0_perfcntr1(val);
221 write_c0_perfcntr2(val);
224 write_c0_perfcntr3(val);
229 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
231 idx = mipsxx_pmu_swizzle_perf_idx(idx);
235 write_c0_perfcntr0_64(val);
238 write_c0_perfcntr1_64(val);
241 write_c0_perfcntr2_64(val);
244 write_c0_perfcntr3_64(val);
249 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
251 idx = mipsxx_pmu_swizzle_perf_idx(idx);
255 return read_c0_perfctrl0();
257 return read_c0_perfctrl1();
259 return read_c0_perfctrl2();
261 return read_c0_perfctrl3();
263 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
268 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
270 idx = mipsxx_pmu_swizzle_perf_idx(idx);
274 write_c0_perfctrl0(val);
277 write_c0_perfctrl1(val);
280 write_c0_perfctrl2(val);
283 write_c0_perfctrl3(val);
288 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
289 struct hw_perf_event *hwc)
294 * We only need to care the counter mask. The range has been
295 * checked definitely.
297 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
299 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
301 * Note that some MIPS perf events can be counted by both
302 * even and odd counters, wheresas many other are only by
303 * even _or_ odd counters. This introduces an issue that
304 * when the former kind of event takes the counter the
305 * latter kind of event wants to use, then the "counter
306 * allocation" for the latter event will fail. In fact if
307 * they can be dynamically swapped, they both feel happy.
308 * But here we leave this issue alone for now.
310 if (test_bit(i, &cntr_mask) &&
311 !test_and_set_bit(i, cpuc->used_mask))
318 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
320 struct perf_event *event = container_of(evt, struct perf_event, hw);
321 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
322 unsigned int range = evt->event_base >> 24;
324 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
326 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
327 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
328 /* Make sure interrupt enabled. */
331 if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
332 /* enable the counter for the calling thread */
333 cpuc->saved_ctrl[idx] |=
334 (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
335 } else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) {
336 /* The counter is processor wide. Set it up to count all TCs. */
337 pr_debug("Enabling perf counter for all TCs\n");
338 cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
340 unsigned int cpu, ctrl;
343 * Set up the counter for a particular CPU when event->cpu is
344 * a valid CPU number. Otherwise set up the counter for the CPU
345 * scheduling this thread.
347 cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
349 ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
351 cpuc->saved_ctrl[idx] |= ctrl;
352 pr_debug("Enabling perf counter for CPU%d\n", cpu);
355 * We do not actually let the counter run. Leave it until start().
359 static void mipsxx_pmu_disable_event(int idx)
361 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
364 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
366 local_irq_save(flags);
367 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
368 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
369 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
370 local_irq_restore(flags);
373 static int mipspmu_event_set_period(struct perf_event *event,
374 struct hw_perf_event *hwc,
377 u64 left = local64_read(&hwc->period_left);
378 u64 period = hwc->sample_period;
381 if (unlikely((left + period) & (1ULL << 63))) {
382 /* left underflowed by more than period. */
384 local64_set(&hwc->period_left, left);
385 hwc->last_period = period;
387 } else if (unlikely((left + period) <= period)) {
388 /* left underflowed by less than period. */
390 local64_set(&hwc->period_left, left);
391 hwc->last_period = period;
395 if (left > mipspmu.max_period) {
396 left = mipspmu.max_period;
397 local64_set(&hwc->period_left, left);
400 local64_set(&hwc->prev_count, mipspmu.overflow - left);
402 mipspmu.write_counter(idx, mipspmu.overflow - left);
404 perf_event_update_userpage(event);
409 static void mipspmu_event_update(struct perf_event *event,
410 struct hw_perf_event *hwc,
413 u64 prev_raw_count, new_raw_count;
417 prev_raw_count = local64_read(&hwc->prev_count);
418 new_raw_count = mipspmu.read_counter(idx);
420 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
421 new_raw_count) != prev_raw_count)
424 delta = new_raw_count - prev_raw_count;
426 local64_add(delta, &event->count);
427 local64_sub(delta, &hwc->period_left);
430 static void mipspmu_start(struct perf_event *event, int flags)
432 struct hw_perf_event *hwc = &event->hw;
434 if (flags & PERF_EF_RELOAD)
435 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
439 /* Set the period for the event. */
440 mipspmu_event_set_period(event, hwc, hwc->idx);
442 /* Enable the event. */
443 mipsxx_pmu_enable_event(hwc, hwc->idx);
446 static void mipspmu_stop(struct perf_event *event, int flags)
448 struct hw_perf_event *hwc = &event->hw;
450 if (!(hwc->state & PERF_HES_STOPPED)) {
451 /* We are working on a local event. */
452 mipsxx_pmu_disable_event(hwc->idx);
454 mipspmu_event_update(event, hwc, hwc->idx);
455 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
459 static int mipspmu_add(struct perf_event *event, int flags)
461 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
462 struct hw_perf_event *hwc = &event->hw;
466 perf_pmu_disable(event->pmu);
468 /* To look for a free counter for this event. */
469 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
476 * If there is an event in the counter we are going to use then
477 * make sure it is disabled.
480 mipsxx_pmu_disable_event(idx);
481 cpuc->events[idx] = event;
483 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
484 if (flags & PERF_EF_START)
485 mipspmu_start(event, PERF_EF_RELOAD);
487 /* Propagate our changes to the userspace mapping. */
488 perf_event_update_userpage(event);
491 perf_pmu_enable(event->pmu);
495 static void mipspmu_del(struct perf_event *event, int flags)
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 struct hw_perf_event *hwc = &event->hw;
501 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
503 mipspmu_stop(event, PERF_EF_UPDATE);
504 cpuc->events[idx] = NULL;
505 clear_bit(idx, cpuc->used_mask);
507 perf_event_update_userpage(event);
510 static void mipspmu_read(struct perf_event *event)
512 struct hw_perf_event *hwc = &event->hw;
514 /* Don't read disabled counters! */
518 mipspmu_event_update(event, hwc, hwc->idx);
521 static void mipspmu_enable(struct pmu *pmu)
523 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
524 write_unlock(&pmuint_rwlock);
526 resume_local_counters();
530 * MIPS performance counters can be per-TC. The control registers can
531 * not be directly accessed across CPUs. Hence if we want to do global
532 * control, we need cross CPU calls. on_each_cpu() can help us, but we
533 * can not make sure this function is called with interrupts enabled. So
534 * here we pause local counters and then grab a rwlock and leave the
535 * counters on other CPUs alone. If any counter interrupt raises while
536 * we own the write lock, simply pause local counters on that CPU and
537 * spin in the handler. Also we know we won't be switched to another
538 * CPU after pausing local counters and before grabbing the lock.
540 static void mipspmu_disable(struct pmu *pmu)
542 pause_local_counters();
543 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
544 write_lock(&pmuint_rwlock);
548 static atomic_t active_events = ATOMIC_INIT(0);
549 static DEFINE_MUTEX(pmu_reserve_mutex);
550 static int (*save_perf_irq)(void);
552 static int mipspmu_get_irq(void)
556 if (mipspmu.irq >= 0) {
557 /* Request my own irq handler. */
558 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
559 IRQF_PERCPU | IRQF_NOBALANCING |
560 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
562 "mips_perf_pmu", &mipspmu);
564 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
567 } else if (cp0_perfcount_irq < 0) {
569 * We are sharing the irq number with the timer interrupt.
571 save_perf_irq = perf_irq;
572 perf_irq = mipsxx_pmu_handle_shared_irq;
575 pr_warn("The platform hasn't properly defined its interrupt controller\n");
582 static void mipspmu_free_irq(void)
584 if (mipspmu.irq >= 0)
585 free_irq(mipspmu.irq, &mipspmu);
586 else if (cp0_perfcount_irq < 0)
587 perf_irq = save_perf_irq;
591 * mipsxx/rm9000/loongson2 have different performance counters, they have
592 * specific low-level init routines.
594 static void reset_counters(void *arg);
595 static int __hw_perf_event_init(struct perf_event *event);
597 static void hw_perf_event_destroy(struct perf_event *event)
599 if (atomic_dec_and_mutex_lock(&active_events,
600 &pmu_reserve_mutex)) {
602 * We must not call the destroy function with interrupts
605 on_each_cpu(reset_counters,
606 (void *)(long)mipspmu.num_counters, 1);
608 mutex_unlock(&pmu_reserve_mutex);
612 static int mipspmu_event_init(struct perf_event *event)
616 /* does not support taken branch sampling */
617 if (has_branch_stack(event))
620 switch (event->attr.type) {
622 case PERF_TYPE_HARDWARE:
623 case PERF_TYPE_HW_CACHE:
630 if (event->cpu >= 0 && !cpu_online(event->cpu))
633 if (!atomic_inc_not_zero(&active_events)) {
634 mutex_lock(&pmu_reserve_mutex);
635 if (atomic_read(&active_events) == 0)
636 err = mipspmu_get_irq();
639 atomic_inc(&active_events);
640 mutex_unlock(&pmu_reserve_mutex);
646 return __hw_perf_event_init(event);
649 static struct pmu pmu = {
650 .pmu_enable = mipspmu_enable,
651 .pmu_disable = mipspmu_disable,
652 .event_init = mipspmu_event_init,
655 .start = mipspmu_start,
656 .stop = mipspmu_stop,
657 .read = mipspmu_read,
660 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
663 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
666 #ifdef CONFIG_MIPS_MT_SMP
667 if (num_possible_cpus() > 1)
668 return ((unsigned int)pev->range << 24) |
669 (pev->cntr_mask & 0xffff00) |
670 (pev->event_id & 0xff);
672 #endif /* CONFIG_MIPS_MT_SMP */
673 return ((pev->cntr_mask & 0xffff00) |
674 (pev->event_id & 0xff));
677 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
680 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
681 return ERR_PTR(-EOPNOTSUPP);
682 return &(*mipspmu.general_event_map)[idx];
685 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
687 unsigned int cache_type, cache_op, cache_result;
688 const struct mips_perf_event *pev;
690 cache_type = (config >> 0) & 0xff;
691 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
692 return ERR_PTR(-EINVAL);
694 cache_op = (config >> 8) & 0xff;
695 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
696 return ERR_PTR(-EINVAL);
698 cache_result = (config >> 16) & 0xff;
699 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
700 return ERR_PTR(-EINVAL);
702 pev = &((*mipspmu.cache_event_map)
707 if (pev->cntr_mask == 0)
708 return ERR_PTR(-EOPNOTSUPP);
714 static int validate_group(struct perf_event *event)
716 struct perf_event *sibling, *leader = event->group_leader;
717 struct cpu_hw_events fake_cpuc;
719 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
724 for_each_sibling_event(sibling, leader) {
725 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
729 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
735 /* This is needed by specific irq handlers in perf_event_*.c */
736 static void handle_associated_event(struct cpu_hw_events *cpuc,
737 int idx, struct perf_sample_data *data,
738 struct pt_regs *regs)
740 struct perf_event *event = cpuc->events[idx];
741 struct hw_perf_event *hwc = &event->hw;
743 mipspmu_event_update(event, hwc, idx);
744 data->period = event->hw.last_period;
745 if (!mipspmu_event_set_period(event, hwc, idx))
748 if (perf_event_overflow(event, data, regs))
749 mipsxx_pmu_disable_event(idx);
753 static int __n_counters(void)
757 if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
759 if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
761 if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
767 static int n_counters(void)
771 switch (current_cpu_type()) {
783 counters = __n_counters();
789 static void reset_counters(void *arg)
791 int counters = (int)(long)arg;
794 mipsxx_pmu_write_control(3, 0);
795 mipspmu.write_counter(3, 0);
797 mipsxx_pmu_write_control(2, 0);
798 mipspmu.write_counter(2, 0);
800 mipsxx_pmu_write_control(1, 0);
801 mipspmu.write_counter(1, 0);
803 mipsxx_pmu_write_control(0, 0);
804 mipspmu.write_counter(0, 0);
808 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
809 static const struct mips_perf_event mipsxxcore_event_map
810 [PERF_COUNT_HW_MAX] = {
811 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
812 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
813 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
814 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
817 /* 74K/proAptiv core has different branch event code. */
818 static const struct mips_perf_event mipsxxcore_event_map2
819 [PERF_COUNT_HW_MAX] = {
820 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
821 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
822 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
823 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
826 static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
827 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },
828 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },
829 /* These only count dcache, not icache */
830 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },
831 [PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },
832 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
833 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },
836 static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
837 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
838 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
839 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
840 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
843 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
844 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
845 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
846 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
847 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
848 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
849 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
850 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
853 static const struct mips_perf_event bmips5000_event_map
854 [PERF_COUNT_HW_MAX] = {
855 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
856 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
857 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
860 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
861 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
862 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
863 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
864 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
865 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
866 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
869 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
870 static const struct mips_perf_event mipsxxcore_cache_map
871 [PERF_COUNT_HW_CACHE_MAX]
872 [PERF_COUNT_HW_CACHE_OP_MAX]
873 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
876 * Like some other architectures (e.g. ARM), the performance
877 * counters don't differentiate between read and write
878 * accesses/misses, so this isn't strictly correct, but it's the
879 * best we can do. Writes and reads get combined.
882 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
883 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
886 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
887 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
892 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
893 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
896 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
897 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
900 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
902 * Note that MIPS has only "hit" events countable for
903 * the prefetch operation.
909 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
910 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
913 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
914 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
919 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
920 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
923 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
924 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
929 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
930 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
933 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
934 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
938 /* Using the same code for *HW_BRANCH* */
940 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
941 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
944 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
945 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
950 /* 74K/proAptiv core has completely different cache event map. */
951 static const struct mips_perf_event mipsxxcore_cache_map2
952 [PERF_COUNT_HW_CACHE_MAX]
953 [PERF_COUNT_HW_CACHE_OP_MAX]
954 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
957 * Like some other architectures (e.g. ARM), the performance
958 * counters don't differentiate between read and write
959 * accesses/misses, so this isn't strictly correct, but it's the
960 * best we can do. Writes and reads get combined.
963 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
964 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
967 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
968 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
973 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
974 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
977 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
978 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
981 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
983 * Note that MIPS has only "hit" events countable for
984 * the prefetch operation.
990 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
991 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
994 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
995 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
999 * 74K core does not have specific DTLB events. proAptiv core has
1000 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
1001 * not included here. One can use raw events if really needed.
1005 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1006 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1009 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1010 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1014 /* Using the same code for *HW_BRANCH* */
1016 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1017 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1020 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1021 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1026 static const struct mips_perf_event i6x00_cache_map
1027 [PERF_COUNT_HW_CACHE_MAX]
1028 [PERF_COUNT_HW_CACHE_OP_MAX]
1029 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1032 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1033 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1036 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1037 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1042 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1043 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1047 /* Can't distinguish read & write */
1049 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1050 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1053 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1054 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1058 /* Conditional branches / mispredicted */
1060 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1061 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1066 static const struct mips_perf_event loongson3_cache_map
1067 [PERF_COUNT_HW_CACHE_MAX]
1068 [PERF_COUNT_HW_CACHE_OP_MAX]
1069 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1072 * Like some other architectures (e.g. ARM), the performance
1073 * counters don't differentiate between read and write
1074 * accesses/misses, so this isn't strictly correct, but it's the
1075 * best we can do. Writes and reads get combined.
1078 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1081 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1086 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1089 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1094 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1097 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1102 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1105 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1109 /* Using the same code for *HW_BRANCH* */
1111 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1112 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1115 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1116 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1122 static const struct mips_perf_event bmips5000_cache_map
1123 [PERF_COUNT_HW_CACHE_MAX]
1124 [PERF_COUNT_HW_CACHE_OP_MAX]
1125 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1128 * Like some other architectures (e.g. ARM), the performance
1129 * counters don't differentiate between read and write
1130 * accesses/misses, so this isn't strictly correct, but it's the
1131 * best we can do. Writes and reads get combined.
1134 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1135 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1138 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1139 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1144 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1145 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1148 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1149 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1151 [C(OP_PREFETCH)] = {
1152 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1154 * Note that MIPS has only "hit" events countable for
1155 * the prefetch operation.
1161 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1162 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1165 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1166 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1170 /* Using the same code for *HW_BRANCH* */
1172 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1175 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1181 static const struct mips_perf_event octeon_cache_map
1182 [PERF_COUNT_HW_CACHE_MAX]
1183 [PERF_COUNT_HW_CACHE_OP_MAX]
1184 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1187 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1188 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1191 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1196 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1198 [C(OP_PREFETCH)] = {
1199 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1204 * Only general DTLB misses are counted use the same event for
1208 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1211 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1216 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1221 static const struct mips_perf_event xlp_cache_map
1222 [PERF_COUNT_HW_CACHE_MAX]
1223 [PERF_COUNT_HW_CACHE_OP_MAX]
1224 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1227 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1228 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1231 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1232 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1237 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1238 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1243 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1244 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1247 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1248 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1253 * Only general DTLB misses are counted use the same event for
1257 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1260 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1265 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1268 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1273 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1278 static int __hw_perf_event_init(struct perf_event *event)
1280 struct perf_event_attr *attr = &event->attr;
1281 struct hw_perf_event *hwc = &event->hw;
1282 const struct mips_perf_event *pev;
1285 /* Returning MIPS event descriptor for generic perf event. */
1286 if (PERF_TYPE_HARDWARE == event->attr.type) {
1287 if (event->attr.config >= PERF_COUNT_HW_MAX)
1289 pev = mipspmu_map_general_event(event->attr.config);
1290 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1291 pev = mipspmu_map_cache_event(event->attr.config);
1292 } else if (PERF_TYPE_RAW == event->attr.type) {
1293 /* We are working on the global raw event. */
1294 mutex_lock(&raw_event_mutex);
1295 pev = mipspmu.map_raw_event(event->attr.config);
1297 /* The event type is not (yet) supported. */
1302 if (PERF_TYPE_RAW == event->attr.type)
1303 mutex_unlock(&raw_event_mutex);
1304 return PTR_ERR(pev);
1308 * We allow max flexibility on how each individual counter shared
1309 * by the single CPU operates (the mode exclusion and the range).
1311 hwc->config_base = MIPS_PERFCTRL_IE;
1313 hwc->event_base = mipspmu_perf_event_encode(pev);
1314 if (PERF_TYPE_RAW == event->attr.type)
1315 mutex_unlock(&raw_event_mutex);
1317 if (!attr->exclude_user)
1318 hwc->config_base |= MIPS_PERFCTRL_U;
1319 if (!attr->exclude_kernel) {
1320 hwc->config_base |= MIPS_PERFCTRL_K;
1321 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1322 hwc->config_base |= MIPS_PERFCTRL_EXL;
1324 if (!attr->exclude_hv)
1325 hwc->config_base |= MIPS_PERFCTRL_S;
1327 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1329 * The event can belong to another cpu. We do not assign a local
1330 * counter for it for now.
1335 if (!hwc->sample_period) {
1336 hwc->sample_period = mipspmu.max_period;
1337 hwc->last_period = hwc->sample_period;
1338 local64_set(&hwc->period_left, hwc->sample_period);
1342 if (event->group_leader != event)
1343 err = validate_group(event);
1345 event->destroy = hw_perf_event_destroy;
1348 event->destroy(event);
1353 static void pause_local_counters(void)
1355 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1356 int ctr = mipspmu.num_counters;
1357 unsigned long flags;
1359 local_irq_save(flags);
1362 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1363 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1364 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1366 local_irq_restore(flags);
1369 static void resume_local_counters(void)
1371 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1372 int ctr = mipspmu.num_counters;
1376 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1380 static int mipsxx_pmu_handle_shared_irq(void)
1382 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1383 struct perf_sample_data data;
1384 unsigned int counters = mipspmu.num_counters;
1386 int handled = IRQ_NONE;
1387 struct pt_regs *regs;
1389 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1392 * First we pause the local counters, so that when we are locked
1393 * here, the counters are all paused. When it gets locked due to
1394 * perf_disable(), the timer interrupt handler will be delayed.
1396 * See also mipsxx_pmu_start().
1398 pause_local_counters();
1399 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1400 read_lock(&pmuint_rwlock);
1403 regs = get_irq_regs();
1405 perf_sample_data_init(&data, 0, 0);
1408 #define HANDLE_COUNTER(n) \
1410 if (test_bit(n, cpuc->used_mask)) { \
1411 counter = mipspmu.read_counter(n); \
1412 if (counter & mipspmu.overflow) { \
1413 handle_associated_event(cpuc, n, &data, regs); \
1414 handled = IRQ_HANDLED; \
1423 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1424 read_unlock(&pmuint_rwlock);
1426 resume_local_counters();
1429 * Do all the work for the pending perf events. We can do this
1430 * in here because the performance counter interrupt is a regular
1431 * interrupt, not NMI.
1433 if (handled == IRQ_HANDLED)
1439 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1441 return mipsxx_pmu_handle_shared_irq();
1445 #define IS_BOTH_COUNTERS_24K_EVENT(b) \
1446 ((b) == 0 || (b) == 1 || (b) == 11)
1449 #define IS_BOTH_COUNTERS_34K_EVENT(b) \
1450 ((b) == 0 || (b) == 1 || (b) == 11)
1451 #ifdef CONFIG_MIPS_MT_SMP
1452 #define IS_RANGE_P_34K_EVENT(r, b) \
1453 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1454 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1455 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1456 ((b) >= 64 && (b) <= 67))
1457 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1461 #define IS_BOTH_COUNTERS_74K_EVENT(b) \
1462 ((b) == 0 || (b) == 1)
1465 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
1466 ((b) == 0 || (b) == 1)
1468 #define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1469 ((b) == 0 || (b) == 1)
1472 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1473 ((b) == 0 || (b) == 1 || (b) == 11)
1474 #ifdef CONFIG_MIPS_MT_SMP
1475 #define IS_RANGE_P_1004K_EVENT(r, b) \
1476 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1477 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1478 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1479 (r) == 188 || (b) == 61 || (b) == 62 || \
1480 ((b) >= 64 && (b) <= 67))
1481 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1485 #define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
1486 ((b) == 0 || (b) == 1 || (b) == 11)
1487 #ifdef CONFIG_MIPS_MT_SMP
1488 /* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1489 #define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
1490 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1491 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
1492 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
1493 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
1494 ((b) >= 64 && (b) <= 67))
1495 #define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
1499 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
1500 ((b) == 0 || (b) == 1)
1504 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1505 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1506 * indicate the even/odd bank selector. So, for example, when user wants to take
1507 * the Event Num of 15 for odd counters (by referring to the user manual), then
1508 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1511 * Some newer cores have even more events, in which case the user can use raw
1512 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1513 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1515 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1517 /* currently most cores have 7-bit event numbers */
1518 unsigned int raw_id = config & 0xff;
1519 unsigned int base_id = raw_id & 0x7f;
1521 switch (current_cpu_type()) {
1523 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1524 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1526 raw_event.cntr_mask =
1527 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1528 #ifdef CONFIG_MIPS_MT_SMP
1530 * This is actually doing nothing. Non-multithreading
1531 * CPUs will not check and calculate the range.
1533 raw_event.range = P;
1537 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1538 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1540 raw_event.cntr_mask =
1541 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1542 #ifdef CONFIG_MIPS_MT_SMP
1543 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1544 raw_event.range = P;
1545 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1546 raw_event.range = V;
1548 raw_event.range = T;
1553 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1554 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1556 raw_event.cntr_mask =
1557 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1558 #ifdef CONFIG_MIPS_MT_SMP
1559 raw_event.range = P;
1563 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1564 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1566 raw_event.cntr_mask =
1567 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1568 #ifdef CONFIG_MIPS_MT_SMP
1569 raw_event.range = P;
1574 /* 8-bit event numbers */
1575 raw_id = config & 0x1ff;
1576 base_id = raw_id & 0xff;
1577 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1578 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1580 raw_event.cntr_mask =
1581 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1582 #ifdef CONFIG_MIPS_MT_SMP
1583 raw_event.range = P;
1588 /* 8-bit event numbers */
1589 base_id = config & 0xff;
1590 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1593 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1594 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1596 raw_event.cntr_mask =
1597 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1598 #ifdef CONFIG_MIPS_MT_SMP
1599 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1600 raw_event.range = P;
1601 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1602 raw_event.range = V;
1604 raw_event.range = T;
1607 case CPU_INTERAPTIV:
1608 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1609 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1611 raw_event.cntr_mask =
1612 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1613 #ifdef CONFIG_MIPS_MT_SMP
1614 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1615 raw_event.range = P;
1616 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1617 raw_event.range = V;
1619 raw_event.range = T;
1623 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1624 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1626 raw_event.cntr_mask =
1627 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1630 raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1634 raw_event.event_id = base_id;
1639 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1641 unsigned int raw_id = config & 0xff;
1642 unsigned int base_id = raw_id & 0x7f;
1645 raw_event.cntr_mask = CNTR_ALL;
1646 raw_event.event_id = base_id;
1648 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1650 return ERR_PTR(-EOPNOTSUPP);
1653 return ERR_PTR(-EOPNOTSUPP);
1664 return ERR_PTR(-EOPNOTSUPP);
1672 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1674 unsigned int raw_id = config & 0xff;
1676 /* Only 1-63 are defined */
1677 if ((raw_id < 0x01) || (raw_id > 0x3f))
1678 return ERR_PTR(-EOPNOTSUPP);
1680 raw_event.cntr_mask = CNTR_ALL;
1681 raw_event.event_id = raw_id;
1687 init_hw_perf_events(void)
1692 pr_info("Performance counters: ");
1694 counters = n_counters();
1695 if (counters == 0) {
1696 pr_cont("No available PMU.\n");
1700 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1701 if (!cpu_has_mipsmt_pertccounters)
1702 counters = counters_total_to_per_cpu(counters);
1705 if (get_c0_perfcount_int)
1706 irq = get_c0_perfcount_int();
1707 else if (cp0_perfcount_irq >= 0)
1708 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1712 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1714 switch (current_cpu_type()) {
1716 mipspmu.name = "mips/24K";
1717 mipspmu.general_event_map = &mipsxxcore_event_map;
1718 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1721 mipspmu.name = "mips/34K";
1722 mipspmu.general_event_map = &mipsxxcore_event_map;
1723 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1726 mipspmu.name = "mips/74K";
1727 mipspmu.general_event_map = &mipsxxcore_event_map2;
1728 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1731 mipspmu.name = "mips/proAptiv";
1732 mipspmu.general_event_map = &mipsxxcore_event_map2;
1733 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1736 mipspmu.name = "mips/P5600";
1737 mipspmu.general_event_map = &mipsxxcore_event_map2;
1738 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1741 mipspmu.name = "mips/P6600";
1742 mipspmu.general_event_map = &mipsxxcore_event_map2;
1743 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1746 mipspmu.name = "mips/I6400";
1747 mipspmu.general_event_map = &i6x00_event_map;
1748 mipspmu.cache_event_map = &i6x00_cache_map;
1751 mipspmu.name = "mips/I6500";
1752 mipspmu.general_event_map = &i6x00_event_map;
1753 mipspmu.cache_event_map = &i6x00_cache_map;
1756 mipspmu.name = "mips/1004K";
1757 mipspmu.general_event_map = &mipsxxcore_event_map;
1758 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1761 mipspmu.name = "mips/1074K";
1762 mipspmu.general_event_map = &mipsxxcore_event_map;
1763 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1765 case CPU_INTERAPTIV:
1766 mipspmu.name = "mips/interAptiv";
1767 mipspmu.general_event_map = &mipsxxcore_event_map;
1768 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1771 mipspmu.name = "mips/loongson1";
1772 mipspmu.general_event_map = &mipsxxcore_event_map;
1773 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1776 mipspmu.name = "mips/loongson3";
1777 mipspmu.general_event_map = &loongson3_event_map;
1778 mipspmu.cache_event_map = &loongson3_cache_map;
1780 case CPU_CAVIUM_OCTEON:
1781 case CPU_CAVIUM_OCTEON_PLUS:
1782 case CPU_CAVIUM_OCTEON2:
1783 mipspmu.name = "octeon";
1784 mipspmu.general_event_map = &octeon_event_map;
1785 mipspmu.cache_event_map = &octeon_cache_map;
1786 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1789 mipspmu.name = "BMIPS5000";
1790 mipspmu.general_event_map = &bmips5000_event_map;
1791 mipspmu.cache_event_map = &bmips5000_cache_map;
1794 mipspmu.name = "xlp";
1795 mipspmu.general_event_map = &xlp_event_map;
1796 mipspmu.cache_event_map = &xlp_cache_map;
1797 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1800 pr_cont("Either hardware does not support performance "
1801 "counters, or not yet implemented.\n");
1805 mipspmu.num_counters = counters;
1808 if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
1809 mipspmu.max_period = (1ULL << 63) - 1;
1810 mipspmu.valid_count = (1ULL << 63) - 1;
1811 mipspmu.overflow = 1ULL << 63;
1812 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1813 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1816 mipspmu.max_period = (1ULL << 31) - 1;
1817 mipspmu.valid_count = (1ULL << 31) - 1;
1818 mipspmu.overflow = 1ULL << 31;
1819 mipspmu.read_counter = mipsxx_pmu_read_counter;
1820 mipspmu.write_counter = mipsxx_pmu_write_counter;
1824 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1826 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1827 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1828 irq < 0 ? " (share with timer interrupt)" : "");
1830 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1834 early_initcall(init_hw_perf_events);