2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 #include "../../../drivers/pci/pci.h"
47 /* hose_spinlock protects accesses to the the phb_bitmap. */
48 static DEFINE_SPINLOCK(hose_spinlock);
51 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
52 #define MAX_PHBS 0x10000
55 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
56 * Accesses to this bitmap should be protected by hose_spinlock.
58 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
60 /* ISA Memory physical address */
61 resource_size_t isa_mem_base;
62 EXPORT_SYMBOL(isa_mem_base);
65 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
67 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
69 pci_dma_ops = dma_ops;
72 const struct dma_map_ops *get_pci_dma_ops(void)
76 EXPORT_SYMBOL(get_pci_dma_ops);
78 static int get_phb_number(struct device_node *dn)
84 * Try fixed PHB numbering first, by checking archs and reading
85 * the respective device-tree properties. Firstly, try reading
86 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
87 * (only present in powernv OPAL environment), then try device-tree
88 * alias and as the last try to use lower bits of "reg" property.
90 ret = of_get_pci_domain_nr(dn);
96 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
99 ret = of_alias_get_id(dn, "pci");
107 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
112 phb_id = (int)(prop & (MAX_PHBS - 1));
114 spin_lock(&hose_spinlock);
116 /* We need to be sure to not use the same PHB number twice. */
117 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
120 /* If everything fails then fallback to dynamic PHB numbering. */
121 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
122 BUG_ON(phb_id >= MAX_PHBS);
123 set_bit(phb_id, phb_bitmap);
126 spin_unlock(&hose_spinlock);
131 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
133 struct pci_controller *phb;
135 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
139 phb->global_number = get_phb_number(dev);
141 spin_lock(&hose_spinlock);
142 list_add_tail(&phb->list_node, &hose_list);
143 spin_unlock(&hose_spinlock);
146 phb->is_dynamic = slab_is_available();
149 int nid = of_node_to_nid(dev);
151 if (nid < 0 || !node_online(nid))
154 PHB_SET_NODE(phb, nid);
159 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
161 void pcibios_free_controller(struct pci_controller *phb)
163 spin_lock(&hose_spinlock);
165 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
166 if (phb->global_number < MAX_PHBS)
167 clear_bit(phb->global_number, phb_bitmap);
169 list_del(&phb->list_node);
170 spin_unlock(&hose_spinlock);
175 EXPORT_SYMBOL_GPL(pcibios_free_controller);
178 * This function is used to call pcibios_free_controller()
179 * in a deferred manner: a callback from the PCI subsystem.
181 * _*DO NOT*_ call pcibios_free_controller() explicitly if
182 * this is used (or it may access an invalid *phb pointer).
184 * The callback occurs when all references to the root bus
185 * are dropped (e.g., child buses/devices and their users).
187 * It's called as .release_fn() of 'struct pci_host_bridge'
188 * which is associated with the 'struct pci_controller.bus'
189 * (root bus) - it expects .release_data to hold a pointer
190 * to 'struct pci_controller'.
192 * In order to use it, register .release_fn()/release_data
195 * pci_set_host_bridge_release(bridge,
196 * pcibios_free_controller_deferred
199 * e.g. in the pcibios_root_bridge_prepare() callback from
200 * pci_create_root_bus().
202 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
204 struct pci_controller *phb = (struct pci_controller *)
205 bridge->release_data;
207 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
209 pcibios_free_controller(phb);
211 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
214 * The function is used to return the minimal alignment
215 * for memory or I/O windows of the associated P2P bridge.
216 * By default, 4KiB alignment for I/O windows and 1MiB for
219 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
222 struct pci_controller *phb = pci_bus_to_host(bus);
224 if (phb->controller_ops.window_alignment)
225 return phb->controller_ops.window_alignment(bus, type);
228 * PCI core will figure out the default
229 * alignment: 4KiB for I/O and 1MiB for
235 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
237 struct pci_controller *hose = pci_bus_to_host(bus);
239 if (hose->controller_ops.setup_bridge)
240 hose->controller_ops.setup_bridge(bus, type);
243 void pcibios_reset_secondary_bus(struct pci_dev *dev)
245 struct pci_controller *phb = pci_bus_to_host(dev->bus);
247 if (phb->controller_ops.reset_secondary_bus) {
248 phb->controller_ops.reset_secondary_bus(dev);
252 pci_reset_secondary_bus(dev);
255 resource_size_t pcibios_default_alignment(void)
257 if (ppc_md.pcibios_default_alignment)
258 return ppc_md.pcibios_default_alignment();
263 #ifdef CONFIG_PCI_IOV
264 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
266 if (ppc_md.pcibios_iov_resource_alignment)
267 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
269 return pci_iov_resource_size(pdev, resno);
272 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
274 if (ppc_md.pcibios_sriov_enable)
275 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
280 int pcibios_sriov_disable(struct pci_dev *pdev)
282 if (ppc_md.pcibios_sriov_disable)
283 return ppc_md.pcibios_sriov_disable(pdev);
288 #endif /* CONFIG_PCI_IOV */
290 void pcibios_bus_add_device(struct pci_dev *pdev)
292 if (ppc_md.pcibios_bus_add_device)
293 ppc_md.pcibios_bus_add_device(pdev);
296 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
299 return hose->pci_io_size;
301 return resource_size(&hose->io_resource);
305 int pcibios_vaddr_is_ioport(void __iomem *address)
308 struct pci_controller *hose;
309 resource_size_t size;
311 spin_lock(&hose_spinlock);
312 list_for_each_entry(hose, &hose_list, list_node) {
313 size = pcibios_io_size(hose);
314 if (address >= hose->io_base_virt &&
315 address < (hose->io_base_virt + size)) {
320 spin_unlock(&hose_spinlock);
324 unsigned long pci_address_to_pio(phys_addr_t address)
326 struct pci_controller *hose;
327 resource_size_t size;
328 unsigned long ret = ~0;
330 spin_lock(&hose_spinlock);
331 list_for_each_entry(hose, &hose_list, list_node) {
332 size = pcibios_io_size(hose);
333 if (address >= hose->io_base_phys &&
334 address < (hose->io_base_phys + size)) {
336 (unsigned long)hose->io_base_virt - _IO_BASE;
337 ret = base + (address - hose->io_base_phys);
341 spin_unlock(&hose_spinlock);
345 EXPORT_SYMBOL_GPL(pci_address_to_pio);
348 * Return the domain number for this bus.
350 int pci_domain_nr(struct pci_bus *bus)
352 struct pci_controller *hose = pci_bus_to_host(bus);
354 return hose->global_number;
356 EXPORT_SYMBOL(pci_domain_nr);
358 /* This routine is meant to be used early during boot, when the
359 * PCI bus numbers have not yet been assigned, and you need to
360 * issue PCI config cycles to an OF device.
361 * It could also be used to "fix" RTAS config cycles if you want
362 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
365 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
368 struct pci_controller *hose, *tmp;
369 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
370 if (hose->dn == node)
378 * Reads the interrupt pin to determine if interrupt is use by card.
379 * If the interrupt is used, then gets the interrupt line from the
380 * openfirmware and sets it in the pci_dev and pci_config line.
382 static int pci_read_irq_line(struct pci_dev *pci_dev)
386 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
388 /* Try to get a mapping from the device-tree */
389 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
393 /* If that fails, lets fallback to what is in the config
394 * space and map that through the default controller. We
395 * also set the type to level low since that's what PCI
396 * interrupts are. If your platform does differently, then
397 * either provide a proper interrupt tree or don't use this
400 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
404 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
405 line == 0xff || line == 0) {
408 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
411 virq = irq_create_mapping(NULL, line);
413 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
417 pr_debug(" Failed to map !\n");
421 pr_debug(" Mapped to linux irq %d\n", virq);
429 * Platform support for /proc/bus/pci/X/Y mmap()s.
432 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
434 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
435 resource_size_t ioaddr = pci_resource_start(pdev, bar);
440 /* Convert to an offset within this PCI controller */
441 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
443 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
448 * This one is used by /dev/mem and fbdev who have no clue about the
449 * PCI device, it tries to find the PCI device first and calls the
452 pgprot_t pci_phys_mem_access_prot(struct file *file,
457 struct pci_dev *pdev = NULL;
458 struct resource *found = NULL;
459 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
462 if (page_is_ram(pfn))
465 prot = pgprot_noncached(prot);
466 for_each_pci_dev(pdev) {
467 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
468 struct resource *rp = &pdev->resource[i];
469 int flags = rp->flags;
471 /* Active and same type? */
472 if ((flags & IORESOURCE_MEM) == 0)
474 /* In the range of this resource? */
475 if (offset < (rp->start & PAGE_MASK) ||
485 if (found->flags & IORESOURCE_PREFETCH)
486 prot = pgprot_noncached_wc(prot);
490 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
491 (unsigned long long)offset, pgprot_val(prot));
496 /* This provides legacy IO read access on a bus */
497 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
499 unsigned long offset;
500 struct pci_controller *hose = pci_bus_to_host(bus);
501 struct resource *rp = &hose->io_resource;
504 /* Check if port can be supported by that bus. We only check
505 * the ranges of the PHB though, not the bus itself as the rules
506 * for forwarding legacy cycles down bridges are not our problem
507 * here. So if the host bridge supports it, we do it.
509 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
512 if (!(rp->flags & IORESOURCE_IO))
514 if (offset < rp->start || (offset + size) > rp->end)
516 addr = hose->io_base_virt + port;
520 *((u8 *)val) = in_8(addr);
525 *((u16 *)val) = in_le16(addr);
530 *((u32 *)val) = in_le32(addr);
536 /* This provides legacy IO write access on a bus */
537 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
539 unsigned long offset;
540 struct pci_controller *hose = pci_bus_to_host(bus);
541 struct resource *rp = &hose->io_resource;
544 /* Check if port can be supported by that bus. We only check
545 * the ranges of the PHB though, not the bus itself as the rules
546 * for forwarding legacy cycles down bridges are not our problem
547 * here. So if the host bridge supports it, we do it.
549 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
552 if (!(rp->flags & IORESOURCE_IO))
554 if (offset < rp->start || (offset + size) > rp->end)
556 addr = hose->io_base_virt + port;
558 /* WARNING: The generic code is idiotic. It gets passed a pointer
559 * to what can be a 1, 2 or 4 byte quantity and always reads that
560 * as a u32, which means that we have to correct the location of
561 * the data read within those 32 bits for size 1 and 2
565 out_8(addr, val >> 24);
570 out_le16(addr, val >> 16);
581 /* This provides legacy IO or memory mmap access on a bus */
582 int pci_mmap_legacy_page_range(struct pci_bus *bus,
583 struct vm_area_struct *vma,
584 enum pci_mmap_state mmap_state)
586 struct pci_controller *hose = pci_bus_to_host(bus);
587 resource_size_t offset =
588 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
589 resource_size_t size = vma->vm_end - vma->vm_start;
592 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
593 pci_domain_nr(bus), bus->number,
594 mmap_state == pci_mmap_mem ? "MEM" : "IO",
595 (unsigned long long)offset,
596 (unsigned long long)(offset + size - 1));
598 if (mmap_state == pci_mmap_mem) {
601 * Because X is lame and can fail starting if it gets an error trying
602 * to mmap legacy_mem (instead of just moving on without legacy memory
603 * access) we fake it here by giving it anonymous memory, effectively
604 * behaving just like /dev/zero
606 if ((offset + size) > hose->isa_mem_size) {
608 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
609 current->comm, current->pid, pci_domain_nr(bus), bus->number);
610 if (vma->vm_flags & VM_SHARED)
611 return shmem_zero_setup(vma);
614 offset += hose->isa_mem_phys;
616 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
617 unsigned long roffset = offset + io_offset;
618 rp = &hose->io_resource;
619 if (!(rp->flags & IORESOURCE_IO))
621 if (roffset < rp->start || (roffset + size) > rp->end)
623 offset += hose->io_base_phys;
625 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
627 vma->vm_pgoff = offset >> PAGE_SHIFT;
628 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
629 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
630 vma->vm_end - vma->vm_start,
634 void pci_resource_to_user(const struct pci_dev *dev, int bar,
635 const struct resource *rsrc,
636 resource_size_t *start, resource_size_t *end)
638 struct pci_bus_region region;
640 if (rsrc->flags & IORESOURCE_IO) {
641 pcibios_resource_to_bus(dev->bus, ®ion,
642 (struct resource *) rsrc);
643 *start = region.start;
648 /* We pass a CPU physical address to userland for MMIO instead of a
649 * BAR value because X is lame and expects to be able to use that
650 * to pass to /dev/mem!
652 * That means we may have 64-bit values where some apps only expect
653 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
655 *start = rsrc->start;
660 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
661 * @hose: newly allocated pci_controller to be setup
662 * @dev: device node of the host bridge
663 * @primary: set if primary bus (32 bits only, soon to be deprecated)
665 * This function will parse the "ranges" property of a PCI host bridge device
666 * node and setup the resource mapping of a pci controller based on its
669 * Life would be boring if it wasn't for a few issues that we have to deal
672 * - We can only cope with one IO space range and up to 3 Memory space
673 * ranges. However, some machines (thanks Apple !) tend to split their
674 * space into lots of small contiguous ranges. So we have to coalesce.
676 * - Some busses have IO space not starting at 0, which causes trouble with
677 * the way we do our IO resource renumbering. The code somewhat deals with
678 * it for 64 bits but I would expect problems on 32 bits.
680 * - Some 32 bits platforms such as 4xx can have physical space larger than
681 * 32 bits so we need to use 64 bits values for the parsing
683 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
684 struct device_node *dev, int primary)
687 struct resource *res;
688 struct of_pci_range range;
689 struct of_pci_range_parser parser;
691 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
692 dev, primary ? "(primary)" : "");
694 /* Check for ranges property */
695 if (of_pci_range_parser_init(&parser, dev))
699 for_each_of_pci_range(&parser, &range) {
700 /* If we failed translation or got a zero-sized region
701 * (some FW try to feed us with non sensical zero sized regions
702 * such as power3 which look like some kind of attempt at exposing
703 * the VGA memory hole)
705 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
708 /* Act based on address space type */
710 switch (range.flags & IORESOURCE_TYPE_BITS) {
713 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
714 range.cpu_addr, range.cpu_addr + range.size - 1,
717 /* We support only one IO range */
718 if (hose->pci_io_size) {
720 " \\--> Skipped (too many) !\n");
724 /* On 32 bits, limit I/O space to 16MB */
725 if (range.size > 0x01000000)
726 range.size = 0x01000000;
728 /* 32 bits needs to map IOs here */
729 hose->io_base_virt = ioremap(range.cpu_addr,
732 /* Expect trouble if pci_addr is not 0 */
735 (unsigned long)hose->io_base_virt;
736 #endif /* CONFIG_PPC32 */
737 /* pci_io_size and io_base_phys always represent IO
738 * space starting at 0 so we factor in pci_addr
740 hose->pci_io_size = range.pci_addr + range.size;
741 hose->io_base_phys = range.cpu_addr - range.pci_addr;
744 res = &hose->io_resource;
745 range.cpu_addr = range.pci_addr;
749 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
750 range.cpu_addr, range.cpu_addr + range.size - 1,
752 (range.pci_space & 0x40000000) ?
755 /* We support only 3 memory ranges */
758 " \\--> Skipped (too many) !\n");
761 /* Handles ISA memory hole space here */
762 if (range.pci_addr == 0) {
763 if (primary || isa_mem_base == 0)
764 isa_mem_base = range.cpu_addr;
765 hose->isa_mem_phys = range.cpu_addr;
766 hose->isa_mem_size = range.size;
770 hose->mem_offset[memno] = range.cpu_addr -
772 res = &hose->mem_resources[memno++];
776 res->name = dev->full_name;
777 res->flags = range.flags;
778 res->start = range.cpu_addr;
779 res->end = range.cpu_addr + range.size - 1;
780 res->parent = res->child = res->sibling = NULL;
785 /* Decide whether to display the domain number in /proc */
786 int pci_proc_domain(struct pci_bus *bus)
788 struct pci_controller *hose = pci_bus_to_host(bus);
790 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
792 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
793 return hose->global_number != 0;
797 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
799 if (ppc_md.pcibios_root_bridge_prepare)
800 return ppc_md.pcibios_root_bridge_prepare(bridge);
805 /* This header fixup will do the resource fixup for all devices as they are
806 * probed, but not for bridge ranges
808 static void pcibios_fixup_resources(struct pci_dev *dev)
810 struct pci_controller *hose = pci_bus_to_host(dev->bus);
814 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
822 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
823 struct resource *res = dev->resource + i;
824 struct pci_bus_region reg;
828 /* If we're going to re-assign everything, we mark all resources
829 * as unset (and 0-base them). In addition, we mark BARs starting
830 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
831 * since in that case, we don't want to re-assign anything
833 pcibios_resource_to_bus(dev->bus, ®, res);
834 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
835 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
836 /* Only print message if not re-assigning */
837 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
838 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
839 pci_name(dev), i, res);
840 res->end -= res->start;
842 res->flags |= IORESOURCE_UNSET;
846 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
849 /* Call machine specific resource fixup */
850 if (ppc_md.pcibios_fixup_resources)
851 ppc_md.pcibios_fixup_resources(dev);
853 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
855 /* This function tries to figure out if a bridge resource has been initialized
856 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
857 * things go more smoothly when it gets it right. It should covers cases such
858 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
860 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
861 struct resource *res)
863 struct pci_controller *hose = pci_bus_to_host(bus);
864 struct pci_dev *dev = bus->self;
865 resource_size_t offset;
866 struct pci_bus_region region;
870 /* We don't do anything if PCI_PROBE_ONLY is set */
871 if (pci_has_flag(PCI_PROBE_ONLY))
874 /* Job is a bit different between memory and IO */
875 if (res->flags & IORESOURCE_MEM) {
876 pcibios_resource_to_bus(dev->bus, ®ion, res);
878 /* If the BAR is non-0 then it's probably been initialized */
879 if (region.start != 0)
882 /* The BAR is 0, let's check if memory decoding is enabled on
883 * the bridge. If not, we consider it unassigned
885 pci_read_config_word(dev, PCI_COMMAND, &command);
886 if ((command & PCI_COMMAND_MEMORY) == 0)
889 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
890 * resources covers that starting address (0 then it's good enough for
891 * us for memory space)
893 for (i = 0; i < 3; i++) {
894 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
895 hose->mem_resources[i].start == hose->mem_offset[i])
899 /* Well, it starts at 0 and we know it will collide so we may as
900 * well consider it as unassigned. That covers the Apple case.
904 /* If the BAR is non-0, then we consider it assigned */
905 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
906 if (((res->start - offset) & 0xfffffffful) != 0)
909 /* Here, we are a bit different than memory as typically IO space
910 * starting at low addresses -is- valid. What we do instead if that
911 * we consider as unassigned anything that doesn't have IO enabled
912 * in the PCI command register, and that's it.
914 pci_read_config_word(dev, PCI_COMMAND, &command);
915 if (command & PCI_COMMAND_IO)
918 /* It's starting at 0 and IO is disabled in the bridge, consider
925 /* Fixup resources of a PCI<->PCI bridge */
926 static void pcibios_fixup_bridge(struct pci_bus *bus)
928 struct resource *res;
931 struct pci_dev *dev = bus->self;
933 pci_bus_for_each_resource(bus, res, i) {
934 if (!res || !res->flags)
936 if (i >= 3 && bus->self->transparent)
939 /* If we're going to reassign everything, we can
940 * shrink the P2P resource to have size as being
941 * of 0 in order to save space.
943 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
944 res->flags |= IORESOURCE_UNSET;
950 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
952 /* Try to detect uninitialized P2P bridge resources,
953 * and clear them out so they get re-assigned later
955 if (pcibios_uninitialized_bridge_resource(bus, res)) {
957 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
962 void pcibios_setup_bus_self(struct pci_bus *bus)
964 struct pci_controller *phb;
966 /* Fix up the bus resources for P2P bridges */
967 if (bus->self != NULL)
968 pcibios_fixup_bridge(bus);
970 /* Platform specific bus fixups. This is currently only used
971 * by fsl_pci and I'm hoping to get rid of it at some point
973 if (ppc_md.pcibios_fixup_bus)
974 ppc_md.pcibios_fixup_bus(bus);
976 /* Setup bus DMA mappings */
977 phb = pci_bus_to_host(bus);
978 if (phb->controller_ops.dma_bus_setup)
979 phb->controller_ops.dma_bus_setup(bus);
982 static void pcibios_setup_device(struct pci_dev *dev)
984 struct pci_controller *phb;
985 /* Fixup NUMA node as it may not be setup yet by the generic
986 * code and is needed by the DMA init
988 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
990 /* Hook up default DMA ops */
991 set_dma_ops(&dev->dev, pci_dma_ops);
992 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
994 /* Additional platform DMA/iommu setup */
995 phb = pci_bus_to_host(dev->bus);
996 if (phb->controller_ops.dma_dev_setup)
997 phb->controller_ops.dma_dev_setup(dev);
999 /* Read default IRQs and fixup if necessary */
1000 pci_read_irq_line(dev);
1001 if (ppc_md.pci_irq_fixup)
1002 ppc_md.pci_irq_fixup(dev);
1005 int pcibios_add_device(struct pci_dev *dev)
1008 * We can only call pcibios_setup_device() after bus setup is complete,
1009 * since some of the platform specific DMA setup code depends on it.
1011 if (dev->bus->is_added)
1012 pcibios_setup_device(dev);
1014 #ifdef CONFIG_PCI_IOV
1015 if (ppc_md.pcibios_fixup_sriov)
1016 ppc_md.pcibios_fixup_sriov(dev);
1017 #endif /* CONFIG_PCI_IOV */
1022 void pcibios_setup_bus_devices(struct pci_bus *bus)
1024 struct pci_dev *dev;
1026 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1027 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1029 list_for_each_entry(dev, &bus->devices, bus_list) {
1030 /* Cardbus can call us to add new devices to a bus, so ignore
1031 * those who are already fully discovered
1033 if (pci_dev_is_added(dev))
1036 pcibios_setup_device(dev);
1040 void pcibios_set_master(struct pci_dev *dev)
1042 /* No special bus mastering setup handling */
1045 void pcibios_fixup_bus(struct pci_bus *bus)
1047 /* When called from the generic PCI probe, read PCI<->PCI bridge
1048 * bases. This is -not- called when generating the PCI tree from
1049 * the OF device-tree.
1051 pci_read_bridge_bases(bus);
1053 /* Now fixup the bus bus */
1054 pcibios_setup_bus_self(bus);
1056 /* Now fixup devices on that bus */
1057 pcibios_setup_bus_devices(bus);
1059 EXPORT_SYMBOL(pcibios_fixup_bus);
1061 void pci_fixup_cardbus(struct pci_bus *bus)
1063 /* Now fixup devices on that bus */
1064 pcibios_setup_bus_devices(bus);
1068 static int skip_isa_ioresource_align(struct pci_dev *dev)
1070 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1071 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1077 * We need to avoid collisions with `mirrored' VGA ports
1078 * and other strange ISA hardware, so we always want the
1079 * addresses to be allocated in the 0x000-0x0ff region
1082 * Why? Because some silly external IO cards only decode
1083 * the low 10 bits of the IO address. The 0x00-0xff region
1084 * is reserved for motherboard devices that decode all 16
1085 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1086 * but we want to try to avoid allocating at 0x2900-0x2bff
1087 * which might have be mirrored at 0x0100-0x03ff..
1089 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1090 resource_size_t size, resource_size_t align)
1092 struct pci_dev *dev = data;
1093 resource_size_t start = res->start;
1095 if (res->flags & IORESOURCE_IO) {
1096 if (skip_isa_ioresource_align(dev))
1099 start = (start + 0x3ff) & ~0x3ff;
1104 EXPORT_SYMBOL(pcibios_align_resource);
1107 * Reparent resource children of pr that conflict with res
1108 * under res, and make res replace those children.
1110 static int reparent_resources(struct resource *parent,
1111 struct resource *res)
1113 struct resource *p, **pp;
1114 struct resource **firstpp = NULL;
1116 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1117 if (p->end < res->start)
1119 if (res->end < p->start)
1121 if (p->start < res->start || p->end > res->end)
1122 return -1; /* not completely contained */
1123 if (firstpp == NULL)
1126 if (firstpp == NULL)
1127 return -1; /* didn't find any conflicting entries? */
1128 res->parent = parent;
1129 res->child = *firstpp;
1133 for (p = res->child; p != NULL; p = p->sibling) {
1135 pr_debug("PCI: Reparented %s %pR under %s\n",
1136 p->name, p, res->name);
1142 * Handle resources of PCI devices. If the world were perfect, we could
1143 * just allocate all the resource regions and do nothing more. It isn't.
1144 * On the other hand, we cannot just re-allocate all devices, as it would
1145 * require us to know lots of host bridge internals. So we attempt to
1146 * keep as much of the original configuration as possible, but tweak it
1147 * when it's found to be wrong.
1149 * Known BIOS problems we have to work around:
1150 * - I/O or memory regions not configured
1151 * - regions configured, but not enabled in the command register
1152 * - bogus I/O addresses above 64K used
1153 * - expansion ROMs left enabled (this may sound harmless, but given
1154 * the fact the PCI specs explicitly allow address decoders to be
1155 * shared between expansion ROMs and other resource regions, it's
1156 * at least dangerous)
1159 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1160 * This gives us fixed barriers on where we can allocate.
1161 * (2) Allocate resources for all enabled devices. If there is
1162 * a collision, just mark the resource as unallocated. Also
1163 * disable expansion ROMs during this step.
1164 * (3) Try to allocate resources for disabled devices. If the
1165 * resources were assigned correctly, everything goes well,
1166 * if they weren't, they won't disturb allocation of other
1168 * (4) Assign new addresses to resources which were either
1169 * not configured at all or misconfigured. If explicitly
1170 * requested by the user, configure expansion ROM address
1174 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1178 struct resource *res, *pr;
1180 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1181 pci_domain_nr(bus), bus->number);
1183 pci_bus_for_each_resource(bus, res, i) {
1184 if (!res || !res->flags || res->start > res->end || res->parent)
1187 /* If the resource was left unset at this point, we clear it */
1188 if (res->flags & IORESOURCE_UNSET)
1189 goto clear_resource;
1191 if (bus->parent == NULL)
1192 pr = (res->flags & IORESOURCE_IO) ?
1193 &ioport_resource : &iomem_resource;
1195 pr = pci_find_parent_resource(bus->self, res);
1197 /* this happens when the generic PCI
1198 * code (wrongly) decides that this
1199 * bridge is transparent -- paulus
1205 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1206 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1207 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1209 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1210 struct pci_dev *dev = bus->self;
1212 if (request_resource(pr, res) == 0)
1215 * Must be a conflict with an existing entry.
1216 * Move that entry (or entries) under the
1217 * bridge resource and try again.
1219 if (reparent_resources(pr, res) == 0)
1222 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1223 pci_claim_bridge_resource(dev,
1224 i + PCI_BRIDGE_RESOURCES) == 0)
1227 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1230 /* The resource might be figured out when doing
1231 * reassignment based on the resources required
1232 * by the downstream PCI devices. Here we set
1233 * the size of the resource to be 0 in order to
1241 list_for_each_entry(b, &bus->children, node)
1242 pcibios_allocate_bus_resources(b);
1245 static inline void alloc_resource(struct pci_dev *dev, int idx)
1247 struct resource *pr, *r = &dev->resource[idx];
1249 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1250 pci_name(dev), idx, r);
1252 pr = pci_find_parent_resource(dev, r);
1253 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1254 request_resource(pr, r) < 0) {
1255 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1256 " of device %s, will remap\n", idx, pci_name(dev));
1258 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1259 /* We'll assign a new address later */
1260 r->flags |= IORESOURCE_UNSET;
1266 static void __init pcibios_allocate_resources(int pass)
1268 struct pci_dev *dev = NULL;
1273 for_each_pci_dev(dev) {
1274 pci_read_config_word(dev, PCI_COMMAND, &command);
1275 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1276 r = &dev->resource[idx];
1277 if (r->parent) /* Already allocated */
1279 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1280 continue; /* Not assigned at all */
1281 /* We only allocate ROMs on pass 1 just in case they
1282 * have been screwed up by firmware
1284 if (idx == PCI_ROM_RESOURCE )
1286 if (r->flags & IORESOURCE_IO)
1287 disabled = !(command & PCI_COMMAND_IO);
1289 disabled = !(command & PCI_COMMAND_MEMORY);
1290 if (pass == disabled)
1291 alloc_resource(dev, idx);
1295 r = &dev->resource[PCI_ROM_RESOURCE];
1297 /* Turn the ROM off, leave the resource region,
1298 * but keep it unregistered.
1301 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1302 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1303 pr_debug("PCI: Switching off ROM of %s\n",
1305 r->flags &= ~IORESOURCE_ROM_ENABLE;
1306 pci_write_config_dword(dev, dev->rom_base_reg,
1307 reg & ~PCI_ROM_ADDRESS_ENABLE);
1313 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1315 struct pci_controller *hose = pci_bus_to_host(bus);
1316 resource_size_t offset;
1317 struct resource *res, *pres;
1320 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1323 if (!(hose->io_resource.flags & IORESOURCE_IO))
1325 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1326 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1327 BUG_ON(res == NULL);
1328 res->name = "Legacy IO";
1329 res->flags = IORESOURCE_IO;
1330 res->start = offset;
1331 res->end = (offset + 0xfff) & 0xfffffffful;
1332 pr_debug("Candidate legacy IO: %pR\n", res);
1333 if (request_resource(&hose->io_resource, res)) {
1335 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1336 pci_domain_nr(bus), bus->number, res);
1341 /* Check for memory */
1342 for (i = 0; i < 3; i++) {
1343 pres = &hose->mem_resources[i];
1344 offset = hose->mem_offset[i];
1345 if (!(pres->flags & IORESOURCE_MEM))
1347 pr_debug("hose mem res: %pR\n", pres);
1348 if ((pres->start - offset) <= 0xa0000 &&
1349 (pres->end - offset) >= 0xbffff)
1354 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1355 BUG_ON(res == NULL);
1356 res->name = "Legacy VGA memory";
1357 res->flags = IORESOURCE_MEM;
1358 res->start = 0xa0000 + offset;
1359 res->end = 0xbffff + offset;
1360 pr_debug("Candidate VGA memory: %pR\n", res);
1361 if (request_resource(pres, res)) {
1363 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1364 pci_domain_nr(bus), bus->number, res);
1369 void __init pcibios_resource_survey(void)
1373 /* Allocate and assign resources */
1374 list_for_each_entry(b, &pci_root_buses, node)
1375 pcibios_allocate_bus_resources(b);
1376 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1377 pcibios_allocate_resources(0);
1378 pcibios_allocate_resources(1);
1381 /* Before we start assigning unassigned resource, we try to reserve
1382 * the low IO area and the VGA memory area if they intersect the
1383 * bus available resources to avoid allocating things on top of them
1385 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1386 list_for_each_entry(b, &pci_root_buses, node)
1387 pcibios_reserve_legacy_regions(b);
1390 /* Now, if the platform didn't decide to blindly trust the firmware,
1391 * we proceed to assigning things that were left unassigned
1393 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1394 pr_debug("PCI: Assigning unassigned resources...\n");
1395 pci_assign_unassigned_resources();
1398 /* Call machine dependent fixup */
1399 if (ppc_md.pcibios_fixup)
1400 ppc_md.pcibios_fixup();
1403 /* This is used by the PCI hotplug driver to allocate resource
1404 * of newly plugged busses. We can try to consolidate with the
1405 * rest of the code later, for now, keep it as-is as our main
1406 * resource allocation function doesn't deal with sub-trees yet.
1408 void pcibios_claim_one_bus(struct pci_bus *bus)
1410 struct pci_dev *dev;
1411 struct pci_bus *child_bus;
1413 list_for_each_entry(dev, &bus->devices, bus_list) {
1416 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1417 struct resource *r = &dev->resource[i];
1419 if (r->parent || !r->start || !r->flags)
1422 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1423 pci_name(dev), i, r);
1425 if (pci_claim_resource(dev, i) == 0)
1428 pci_claim_bridge_resource(dev, i);
1432 list_for_each_entry(child_bus, &bus->children, node)
1433 pcibios_claim_one_bus(child_bus);
1435 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1438 /* pcibios_finish_adding_to_bus
1440 * This is to be called by the hotplug code after devices have been
1441 * added to a bus, this include calling it for a PHB that is just
1444 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1446 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1447 pci_domain_nr(bus), bus->number);
1449 /* Allocate bus and devices resources */
1450 pcibios_allocate_bus_resources(bus);
1451 pcibios_claim_one_bus(bus);
1452 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1454 pci_assign_unassigned_bridge_resources(bus->self);
1456 pci_assign_unassigned_bus_resources(bus);
1460 eeh_add_device_tree_late(bus);
1462 /* Add new devices to global lists. Register in proc, sysfs. */
1463 pci_bus_add_devices(bus);
1465 /* sysfs files should only be added after devices are added */
1466 eeh_add_sysfs_files(bus);
1468 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1470 int pcibios_enable_device(struct pci_dev *dev, int mask)
1472 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1474 if (phb->controller_ops.enable_device_hook)
1475 if (!phb->controller_ops.enable_device_hook(dev))
1478 return pci_enable_resources(dev, mask);
1481 void pcibios_disable_device(struct pci_dev *dev)
1483 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1485 if (phb->controller_ops.disable_device)
1486 phb->controller_ops.disable_device(dev);
1489 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1491 return (unsigned long) hose->io_base_virt - _IO_BASE;
1494 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1495 struct list_head *resources)
1497 struct resource *res;
1498 resource_size_t offset;
1501 /* Hookup PHB IO resource */
1502 res = &hose->io_resource;
1505 pr_debug("PCI: I/O resource not set for host"
1506 " bridge %pOF (domain %d)\n",
1507 hose->dn, hose->global_number);
1509 offset = pcibios_io_space_offset(hose);
1511 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1512 res, (unsigned long long)offset);
1513 pci_add_resource_offset(resources, res, offset);
1516 /* Hookup PHB Memory resources */
1517 for (i = 0; i < 3; ++i) {
1518 res = &hose->mem_resources[i];
1522 offset = hose->mem_offset[i];
1523 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1524 res, (unsigned long long)offset);
1526 pci_add_resource_offset(resources, res, offset);
1531 * Null PCI config access functions, for the case when we can't
1534 #define NULL_PCI_OP(rw, size, type) \
1536 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1538 return PCIBIOS_DEVICE_NOT_FOUND; \
1542 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1545 return PCIBIOS_DEVICE_NOT_FOUND;
1549 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1552 return PCIBIOS_DEVICE_NOT_FOUND;
1555 static struct pci_ops null_pci_ops =
1557 .read = null_read_config,
1558 .write = null_write_config,
1562 * These functions are used early on before PCI scanning is done
1563 * and all of the pci_dev and pci_bus structures have been created.
1565 static struct pci_bus *
1566 fake_pci_bus(struct pci_controller *hose, int busnr)
1568 static struct pci_bus bus;
1571 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1575 bus.ops = hose? hose->ops: &null_pci_ops;
1579 #define EARLY_PCI_OP(rw, size, type) \
1580 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1581 int devfn, int offset, type value) \
1583 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1584 devfn, offset, value); \
1587 EARLY_PCI_OP(read, byte, u8 *)
1588 EARLY_PCI_OP(read, word, u16 *)
1589 EARLY_PCI_OP(read, dword, u32 *)
1590 EARLY_PCI_OP(write, byte, u8)
1591 EARLY_PCI_OP(write, word, u16)
1592 EARLY_PCI_OP(write, dword, u32)
1594 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1597 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1600 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1602 struct pci_controller *hose = bus->sysdata;
1604 return of_node_get(hose->dn);
1608 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1609 * @hose: Pointer to the PCI host controller instance structure
1611 void pcibios_scan_phb(struct pci_controller *hose)
1613 LIST_HEAD(resources);
1614 struct pci_bus *bus;
1615 struct device_node *node = hose->dn;
1618 pr_debug("PCI: Scanning PHB %pOF\n", node);
1620 /* Get some IO space for the new PHB */
1621 pcibios_setup_phb_io_space(hose);
1623 /* Wire up PHB bus resources */
1624 pcibios_setup_phb_resources(hose, &resources);
1626 hose->busn.start = hose->first_busno;
1627 hose->busn.end = hose->last_busno;
1628 hose->busn.flags = IORESOURCE_BUS;
1629 pci_add_resource(&resources, &hose->busn);
1631 /* Create an empty bus for the toplevel */
1632 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1633 hose->ops, hose, &resources);
1635 pr_err("Failed to create bus for PCI domain %04x\n",
1636 hose->global_number);
1637 pci_free_resource_list(&resources);
1642 /* Get probe mode and perform scan */
1643 mode = PCI_PROBE_NORMAL;
1644 if (node && hose->controller_ops.probe_mode)
1645 mode = hose->controller_ops.probe_mode(bus);
1646 pr_debug(" probe mode: %d\n", mode);
1647 if (mode == PCI_PROBE_DEVTREE)
1648 of_scan_bus(node, bus);
1650 if (mode == PCI_PROBE_NORMAL) {
1651 pci_bus_update_busn_res_end(bus, 255);
1652 hose->last_busno = pci_scan_child_bus(bus);
1653 pci_bus_update_busn_res_end(bus, hose->last_busno);
1656 /* Platform gets a chance to do some global fixups before
1657 * we proceed to resource allocation
1659 if (ppc_md.pcibios_fixup_phb)
1660 ppc_md.pcibios_fixup_phb(hose);
1662 /* Configure PCI Express settings */
1663 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1664 struct pci_bus *child;
1665 list_for_each_entry(child, &bus->children, node)
1666 pcie_bus_configure_settings(child);
1669 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1671 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1673 int i, class = dev->class >> 8;
1674 /* When configured as agent, programing interface = 1 */
1675 int prog_if = dev->class & 0xf;
1677 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1678 class == PCI_CLASS_BRIDGE_OTHER) &&
1679 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1681 (dev->bus->parent == NULL)) {
1682 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1683 dev->resource[i].start = 0;
1684 dev->resource[i].end = 0;
1685 dev->resource[i].flags = 0;
1689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1693 static int __init discover_phbs(void)
1695 if (ppc_md.discover_phbs)
1696 ppc_md.discover_phbs();
1700 core_initcall(discover_phbs);