2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@mips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/errno.h>
12 #include <linux/percpu.h>
14 #include <linux/of_address.h>
15 #include <linux/spinlock.h>
17 #include <asm/mips-cps.h>
19 void __iomem *mips_cpc_base;
21 static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
23 static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
25 phys_addr_t __weak mips_cpc_default_phys_base(void)
27 struct device_node *cpc_node;
31 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc");
33 err = of_address_to_resource(cpc_node, 0, &res);
34 of_node_put(cpc_node);
43 * mips_cpc_phys_base - retrieve the physical base address of the CPC
45 * This function returns the physical base address of the Cluster Power
46 * Controller memory mapped registers, or 0 if no Cluster Power Controller
49 static phys_addr_t mips_cpc_phys_base(void)
51 unsigned long cpc_base;
53 if (!mips_cm_present())
56 if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX))
59 /* If the CPC is already enabled, leave it so */
60 cpc_base = read_gcr_cpc_base();
61 if (cpc_base & CM_GCR_CPC_BASE_CPCEN)
62 return cpc_base & CM_GCR_CPC_BASE_CPCBASE;
64 /* Otherwise, use the default address */
65 cpc_base = mips_cpc_default_phys_base();
69 /* Enable the CPC, mapped at the default address */
70 write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN);
74 int mips_cpc_probe(void)
79 for_each_possible_cpu(cpu)
80 spin_lock_init(&per_cpu(cpc_core_lock, cpu));
82 addr = mips_cpc_phys_base();
86 mips_cpc_base = ioremap_nocache(addr, 0x8000);
93 void mips_cpc_lock_other(unsigned int core)
95 unsigned int curr_core;
97 if (mips_cm_revision() >= CM_REV_CM3)
98 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
102 curr_core = cpu_core(¤t_cpu_data);
103 spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
104 per_cpu(cpc_core_lock_flags, curr_core));
105 write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
108 * Ensure the core-other region reflects the appropriate core &
109 * VP before any accesses to it occur.
114 void mips_cpc_unlock_other(void)
116 unsigned int curr_core;
118 if (mips_cm_revision() >= CM_REV_CM3)
119 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
122 curr_core = cpu_core(¤t_cpu_data);
123 spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
124 per_cpu(cpc_core_lock_flags, curr_core));