1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _GEN_PV_LOCK_SLOWPATH
3 #error "do not include this file"
6 #include <linux/hash.h>
7 #include <linux/bootmem.h>
8 #include <linux/debug_locks.h>
11 * Implement paravirt qspinlocks; the general idea is to halt the vcpus instead
14 * This relies on the architecture to provide two paravirt hypercalls:
16 * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
17 * pv_kick(cpu) -- wakes a suspended vcpu
19 * Using these we implement __pv_queued_spin_lock_slowpath() and
20 * __pv_queued_spin_unlock() to replace native_queued_spin_lock_slowpath() and
21 * native_queued_spin_unlock().
24 #define _Q_SLOW_VAL (3U << _Q_LOCKED_OFFSET)
27 * Queue Node Adaptive Spinning
29 * A queue node vCPU will stop spinning if the vCPU in the previous node is
30 * not running. The one lock stealing attempt allowed at slowpath entry
31 * mitigates the slight slowdown for non-overcommitted guest with this
32 * aggressive wait-early mechanism.
34 * The status of the previous node will be checked at fixed interval
35 * controlled by PV_PREV_CHECK_MASK. This is to ensure that we won't
36 * pound on the cacheline of the previous node too heavily.
38 #define PV_PREV_CHECK_MASK 0xff
41 * Queue node uses: vcpu_running & vcpu_halted.
42 * Queue head uses: vcpu_running & vcpu_hashed.
46 vcpu_halted, /* Used only in pv_wait_node */
47 vcpu_hashed, /* = pv_hash'ed + vcpu_halted */
51 struct mcs_spinlock mcs;
52 struct mcs_spinlock __res[3];
59 * Include queued spinlock statistics code
61 #include "qspinlock_stat.h"
64 * By replacing the regular queued_spin_trylock() with the function below,
65 * it will be called once when a lock waiter enter the PV slowpath before
66 * being queued. By allowing one lock stealing attempt here when the pending
67 * bit is off, it helps to reduce the performance impact of lock waiter
68 * preemption without the drawback of lock starvation.
70 #define queued_spin_trylock(l) pv_queued_spin_steal_lock(l)
71 static inline bool pv_queued_spin_steal_lock(struct qspinlock *lock)
73 if (!(atomic_read(&lock->val) & _Q_LOCKED_PENDING_MASK) &&
74 (cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) {
75 qstat_inc(qstat_pv_lock_stealing, true);
83 * The pending bit is used by the queue head vCPU to indicate that it
84 * is actively spinning on the lock and no lock stealing is allowed.
86 #if _Q_PENDING_BITS == 8
87 static __always_inline void set_pending(struct qspinlock *lock)
89 WRITE_ONCE(lock->pending, 1);
93 * The pending bit check in pv_queued_spin_steal_lock() isn't a memory
94 * barrier. Therefore, an atomic cmpxchg_acquire() is used to acquire the
95 * lock just to be sure that it will get it.
97 static __always_inline int trylock_clear_pending(struct qspinlock *lock)
99 return !READ_ONCE(lock->locked) &&
100 (cmpxchg_acquire(&lock->locked_pending, _Q_PENDING_VAL,
101 _Q_LOCKED_VAL) == _Q_PENDING_VAL);
103 #else /* _Q_PENDING_BITS == 8 */
104 static __always_inline void set_pending(struct qspinlock *lock)
106 atomic_or(_Q_PENDING_VAL, &lock->val);
109 static __always_inline int trylock_clear_pending(struct qspinlock *lock)
111 int val = atomic_read(&lock->val);
116 if (val & _Q_LOCKED_MASK)
120 * Try to clear pending bit & set locked bit
123 new = (val & ~_Q_PENDING_MASK) | _Q_LOCKED_VAL;
124 val = atomic_cmpxchg_acquire(&lock->val, old, new);
131 #endif /* _Q_PENDING_BITS == 8 */
134 * Lock and MCS node addresses hash table for fast lookup
136 * Hashing is done on a per-cacheline basis to minimize the need to access
137 * more than one cacheline.
139 * Dynamically allocate a hash table big enough to hold at least 4X the
140 * number of possible cpus in the system. Allocation is done on page
141 * granularity. So the minimum number of hash buckets should be at least
142 * 256 (64-bit) or 512 (32-bit) to fully utilize a 4k page.
144 * Since we should not be holding locks from NMI context (very rare indeed) the
145 * max load factor is 0.75, which is around the point where open addressing
149 struct pv_hash_entry {
150 struct qspinlock *lock;
151 struct pv_node *node;
154 #define PV_HE_PER_LINE (SMP_CACHE_BYTES / sizeof(struct pv_hash_entry))
155 #define PV_HE_MIN (PAGE_SIZE / sizeof(struct pv_hash_entry))
157 static struct pv_hash_entry *pv_lock_hash;
158 static unsigned int pv_lock_hash_bits __read_mostly;
161 * Allocate memory for the PV qspinlock hash buckets
163 * This function should be called from the paravirt spinlock initialization
166 void __init __pv_init_lock_hash(void)
168 int pv_hash_size = ALIGN(4 * num_possible_cpus(), PV_HE_PER_LINE);
170 if (pv_hash_size < PV_HE_MIN)
171 pv_hash_size = PV_HE_MIN;
174 * Allocate space from bootmem which should be page-size aligned
175 * and hence cacheline aligned.
177 pv_lock_hash = alloc_large_system_hash("PV qspinlock",
178 sizeof(struct pv_hash_entry),
180 HASH_EARLY | HASH_ZERO,
181 &pv_lock_hash_bits, NULL,
182 pv_hash_size, pv_hash_size);
185 #define for_each_hash_entry(he, offset, hash) \
186 for (hash &= ~(PV_HE_PER_LINE - 1), he = &pv_lock_hash[hash], offset = 0; \
187 offset < (1 << pv_lock_hash_bits); \
188 offset++, he = &pv_lock_hash[(hash + offset) & ((1 << pv_lock_hash_bits) - 1)])
190 static struct qspinlock **pv_hash(struct qspinlock *lock, struct pv_node *node)
192 unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
193 struct pv_hash_entry *he;
196 for_each_hash_entry(he, offset, hash) {
198 if (!cmpxchg(&he->lock, NULL, lock)) {
199 WRITE_ONCE(he->node, node);
205 * Hard assume there is a free entry for us.
207 * This is guaranteed by ensuring every blocked lock only ever consumes
208 * a single entry, and since we only have 4 nesting levels per CPU
209 * and allocated 4*nr_possible_cpus(), this must be so.
211 * The single entry is guaranteed by having the lock owner unhash
212 * before it releases.
217 static struct pv_node *pv_unhash(struct qspinlock *lock)
219 unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
220 struct pv_hash_entry *he;
221 struct pv_node *node;
223 for_each_hash_entry(he, offset, hash) {
224 if (READ_ONCE(he->lock) == lock) {
225 node = READ_ONCE(he->node);
226 WRITE_ONCE(he->lock, NULL);
231 * Hard assume we'll find an entry.
233 * This guarantees a limited lookup time and is itself guaranteed by
234 * having the lock owner do the unhash -- IFF the unlock sees the
235 * SLOW flag, there MUST be a hash entry.
241 * Return true if when it is time to check the previous node which is not
242 * in a running state.
245 pv_wait_early(struct pv_node *prev, int loop)
247 if ((loop & PV_PREV_CHECK_MASK) != 0)
250 return READ_ONCE(prev->state) != vcpu_running;
254 * Initialize the PV part of the mcs_spinlock node.
256 static void pv_init_node(struct mcs_spinlock *node)
258 struct pv_node *pn = (struct pv_node *)node;
260 BUILD_BUG_ON(sizeof(struct pv_node) > 5*sizeof(struct mcs_spinlock));
262 pn->cpu = smp_processor_id();
263 pn->state = vcpu_running;
267 * Wait for node->locked to become true, halt the vcpu after a short spin.
268 * pv_kick_node() is used to set _Q_SLOW_VAL and fill in hash table on its
271 static void pv_wait_node(struct mcs_spinlock *node, struct mcs_spinlock *prev)
273 struct pv_node *pn = (struct pv_node *)node;
274 struct pv_node *pp = (struct pv_node *)prev;
279 for (wait_early = false, loop = SPIN_THRESHOLD; loop; loop--) {
280 if (READ_ONCE(node->locked))
282 if (pv_wait_early(pp, loop)) {
290 * Order pn->state vs pn->locked thusly:
292 * [S] pn->state = vcpu_halted [S] next->locked = 1
294 * [L] pn->locked [RmW] pn->state = vcpu_hashed
296 * Matches the cmpxchg() from pv_kick_node().
298 smp_store_mb(pn->state, vcpu_halted);
300 if (!READ_ONCE(node->locked)) {
301 qstat_inc(qstat_pv_wait_node, true);
302 qstat_inc(qstat_pv_wait_early, wait_early);
303 pv_wait(&pn->state, vcpu_halted);
307 * If pv_kick_node() changed us to vcpu_hashed, retain that
308 * value so that pv_wait_head_or_lock() knows to not also try
311 cmpxchg(&pn->state, vcpu_halted, vcpu_running);
314 * If the locked flag is still not set after wakeup, it is a
315 * spurious wakeup and the vCPU should wait again. However,
316 * there is a pretty high overhead for CPU halting and kicking.
317 * So it is better to spin for a while in the hope that the
318 * MCS lock will be released soon.
320 qstat_inc(qstat_pv_spurious_wakeup, !READ_ONCE(node->locked));
324 * By now our node->locked should be 1 and our caller will not actually
325 * spin-wait for it. We do however rely on our caller to do a
326 * load-acquire for us.
331 * Called after setting next->locked = 1 when we're the lock owner.
333 * Instead of waking the waiters stuck in pv_wait_node() advance their state
334 * such that they're waiting in pv_wait_head_or_lock(), this avoids a
337 static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node)
339 struct pv_node *pn = (struct pv_node *)node;
342 * If the vCPU is indeed halted, advance its state to match that of
343 * pv_wait_node(). If OTOH this fails, the vCPU was running and will
344 * observe its next->locked value and advance itself.
346 * Matches with smp_store_mb() and cmpxchg() in pv_wait_node()
348 * The write to next->locked in arch_mcs_spin_unlock_contended()
349 * must be ordered before the read of pn->state in the cmpxchg()
350 * below for the code to work correctly. To guarantee full ordering
351 * irrespective of the success or failure of the cmpxchg(),
352 * a relaxed version with explicit barrier is used. The control
353 * dependency will order the reading of pn->state before any
356 smp_mb__before_atomic();
357 if (cmpxchg_relaxed(&pn->state, vcpu_halted, vcpu_hashed)
362 * Put the lock into the hash table and set the _Q_SLOW_VAL.
364 * As this is the same vCPU that will check the _Q_SLOW_VAL value and
365 * the hash table later on at unlock time, no atomic instruction is
368 WRITE_ONCE(lock->locked, _Q_SLOW_VAL);
369 (void)pv_hash(lock, pn);
373 * Wait for l->locked to become clear and acquire the lock;
374 * halt the vcpu after a short spin.
375 * __pv_queued_spin_unlock() will wake us.
377 * The current value of the lock will be returned for additional processing.
380 pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node)
382 struct pv_node *pn = (struct pv_node *)node;
383 struct qspinlock **lp = NULL;
388 * If pv_kick_node() already advanced our state, we don't need to
389 * insert ourselves into the hash table anymore.
391 if (READ_ONCE(pn->state) == vcpu_hashed)
392 lp = (struct qspinlock **)1;
395 * Tracking # of slowpath locking operations
397 qstat_inc(qstat_pv_lock_slowpath, true);
401 * Set correct vCPU state to be used by queue node wait-early
404 WRITE_ONCE(pn->state, vcpu_running);
407 * Set the pending bit in the active lock spinning loop to
408 * disable lock stealing before attempting to acquire the lock.
411 for (loop = SPIN_THRESHOLD; loop; loop--) {
412 if (trylock_clear_pending(lock))
419 if (!lp) { /* ONCE */
420 lp = pv_hash(lock, pn);
423 * We must hash before setting _Q_SLOW_VAL, such that
424 * when we observe _Q_SLOW_VAL in __pv_queued_spin_unlock()
425 * we'll be sure to be able to observe our hash entry.
427 * [S] <hash> [Rmw] l->locked == _Q_SLOW_VAL
429 * [RmW] l->locked = _Q_SLOW_VAL [L] <unhash>
431 * Matches the smp_rmb() in __pv_queued_spin_unlock().
433 if (xchg(&lock->locked, _Q_SLOW_VAL) == 0) {
435 * The lock was free and now we own the lock.
436 * Change the lock value back to _Q_LOCKED_VAL
437 * and unhash the table.
439 WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
440 WRITE_ONCE(*lp, NULL);
444 WRITE_ONCE(pn->state, vcpu_hashed);
445 qstat_inc(qstat_pv_wait_head, true);
446 qstat_inc(qstat_pv_wait_again, waitcnt);
447 pv_wait(&lock->locked, _Q_SLOW_VAL);
450 * Because of lock stealing, the queue head vCPU may not be
451 * able to acquire the lock before it has to wait again.
456 * The cmpxchg() or xchg() call before coming here provides the
457 * acquire semantics for locking. The dummy ORing of _Q_LOCKED_VAL
458 * here is to indicate to the compiler that the value will always
459 * be nozero to enable better code optimization.
462 return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL);
466 * PV versions of the unlock fastpath and slowpath functions to be used
467 * instead of queued_spin_unlock().
470 __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked)
472 struct pv_node *node;
474 if (unlikely(locked != _Q_SLOW_VAL)) {
475 WARN(!debug_locks_silent,
476 "pvqspinlock: lock 0x%lx has corrupted value 0x%x!\n",
477 (unsigned long)lock, atomic_read(&lock->val));
482 * A failed cmpxchg doesn't provide any memory-ordering guarantees,
483 * so we need a barrier to order the read of the node data in
484 * pv_unhash *after* we've read the lock being _Q_SLOW_VAL.
486 * Matches the cmpxchg() in pv_wait_head_or_lock() setting _Q_SLOW_VAL.
491 * Since the above failed to release, this must be the SLOW path.
492 * Therefore start by looking up the blocked node and unhashing it.
494 node = pv_unhash(lock);
497 * Now that we have a reference to the (likely) blocked pv_node,
500 smp_store_release(&lock->locked, 0);
503 * At this point the memory pointed at by lock can be freed/reused,
504 * however we can still use the pv_node to kick the CPU.
505 * The other vCPU may not really be halted, but kicking an active
506 * vCPU is harmless other than the additional latency in completing
509 qstat_inc(qstat_pv_kick_unlock, true);
514 * Include the architecture specific callee-save thunk of the
515 * __pv_queued_spin_unlock(). This thunk is put together with
516 * __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock
517 * function close to each other sharing consecutive instruction cachelines.
518 * Alternatively, architecture specific version of __pv_queued_spin_unlock()
521 #include <asm/qspinlock_paravirt.h>
523 #ifndef __pv_queued_spin_unlock
524 __visible void __pv_queued_spin_unlock(struct qspinlock *lock)
529 * We must not unlock if SLOW, because in that case we must first
530 * unhash. Otherwise it would be possible to have multiple @lock
531 * entries, which would be BAD.
533 locked = cmpxchg_release(&lock->locked, _Q_LOCKED_VAL, 0);
534 if (likely(locked == _Q_LOCKED_VAL))
537 __pv_queued_spin_unlock_slowpath(lock, locked);
539 #endif /* __pv_queued_spin_unlock */