4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
15 * (C) Copyright 2013-2014,2018 Red Hat, Inc.
16 * (C) Copyright 2015 Intel Corp.
17 * (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
19 * Authors: Waiman Long <longman@redhat.com>
20 * Peter Zijlstra <peterz@infradead.org>
23 #ifndef _GEN_PV_LOCK_SLOWPATH
25 #include <linux/smp.h>
26 #include <linux/bug.h>
27 #include <linux/cpumask.h>
28 #include <linux/percpu.h>
29 #include <linux/hardirq.h>
30 #include <linux/mutex.h>
31 #include <linux/prefetch.h>
32 #include <asm/byteorder.h>
33 #include <asm/qspinlock.h>
36 * Include queued spinlock statistics code
38 #include "qspinlock_stat.h"
41 * The basic principle of a queue-based spinlock can best be understood
42 * by studying a classic queue-based spinlock implementation called the
43 * MCS lock. The paper below provides a good description for this kind
46 * http://www.cise.ufl.edu/tr/DOC/REP-1992-71.pdf
48 * This queued spinlock implementation is based on the MCS lock, however to make
49 * it fit the 4 bytes we assume spinlock_t to be, and preserve its existing
50 * API, we must modify it somehow.
52 * In particular; where the traditional MCS lock consists of a tail pointer
53 * (8 bytes) and needs the next pointer (another 8 bytes) of its own node to
54 * unlock the next pending (next->locked), we compress both these: {tail,
55 * next->locked} into a single u32 value.
57 * Since a spinlock disables recursion of its own context and there is a limit
58 * to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there
59 * are at most 4 nesting levels, it can be encoded by a 2-bit number. Now
60 * we can encode the tail by combining the 2-bit nesting level with the cpu
61 * number. With one byte for the lock value and 3 bytes for the tail, only a
62 * 32-bit word is now needed. Even though we only need 1 bit for the lock,
63 * we extend it to a full byte to achieve better performance for architectures
64 * that support atomic byte write.
66 * We also change the first spinner to spin on the lock bit instead of its
67 * node; whereby avoiding the need to carry a node from lock to unlock, and
68 * preserving existing lock API. This also makes the unlock code simpler and
71 * N.B. The current implementation only supports architectures that allow
72 * atomic operations on smaller 8-bit and 16-bit data types.
76 #include "mcs_spinlock.h"
78 #ifdef CONFIG_PARAVIRT_SPINLOCKS
85 * The pending bit spinning loop count.
86 * This heuristic is used to limit the number of lockword accesses
87 * made by atomic_cond_read_relaxed when waiting for the lock to
88 * transition out of the "== _Q_PENDING_VAL" state. We don't spin
89 * indefinitely because there's no guarantee that we'll make forward
92 #ifndef _Q_PENDING_LOOPS
93 #define _Q_PENDING_LOOPS 1
97 * Per-CPU queue node structures; we can never have more than 4 nested
98 * contexts: task, softirq, hardirq, nmi.
100 * Exactly fits one 64-byte cacheline on a 64-bit architecture.
102 * PV doubles the storage and uses the second cacheline for PV state.
104 static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[MAX_NODES]);
107 * We must be able to distinguish between no-tail and the tail at 0:0,
108 * therefore increment the cpu number by one.
111 static inline __pure u32 encode_tail(int cpu, int idx)
115 #ifdef CONFIG_DEBUG_SPINLOCK
118 tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
119 tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
124 static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
126 int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;
127 int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
129 return per_cpu_ptr(&mcs_nodes[idx], cpu);
132 #define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)
134 #if _Q_PENDING_BITS == 8
136 * clear_pending - clear the pending bit.
137 * @lock: Pointer to queued spinlock structure
141 static __always_inline void clear_pending(struct qspinlock *lock)
143 WRITE_ONCE(lock->pending, 0);
147 * clear_pending_set_locked - take ownership and clear the pending bit.
148 * @lock: Pointer to queued spinlock structure
152 * Lock stealing is not allowed if this function is used.
154 static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
156 WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);
160 * xchg_tail - Put in the new queue tail code word & retrieve previous one
161 * @lock : Pointer to queued spinlock structure
162 * @tail : The new queue tail code word
163 * Return: The previous queue tail code word
165 * xchg(lock, tail), which heads an address dependency
167 * p,*,* -> n,*,* ; prev = xchg(lock, node)
169 static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
172 * We can use relaxed semantics since the caller ensures that the
173 * MCS node is properly initialized before updating the tail.
175 return (u32)xchg_relaxed(&lock->tail,
176 tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
179 #else /* _Q_PENDING_BITS == 8 */
182 * clear_pending - clear the pending bit.
183 * @lock: Pointer to queued spinlock structure
187 static __always_inline void clear_pending(struct qspinlock *lock)
189 atomic_andnot(_Q_PENDING_VAL, &lock->val);
193 * clear_pending_set_locked - take ownership and clear the pending bit.
194 * @lock: Pointer to queued spinlock structure
198 static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
200 atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
204 * xchg_tail - Put in the new queue tail code word & retrieve previous one
205 * @lock : Pointer to queued spinlock structure
206 * @tail : The new queue tail code word
207 * Return: The previous queue tail code word
211 * p,*,* -> n,*,* ; prev = xchg(lock, node)
213 static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
215 u32 old, new, val = atomic_read(&lock->val);
218 new = (val & _Q_LOCKED_PENDING_MASK) | tail;
220 * We can use relaxed semantics since the caller ensures that
221 * the MCS node is properly initialized before updating the
224 old = atomic_cmpxchg_relaxed(&lock->val, val, new);
232 #endif /* _Q_PENDING_BITS == 8 */
235 * queued_fetch_set_pending_acquire - fetch the whole lock value and set pending
236 * @lock : Pointer to queued spinlock structure
237 * Return: The previous lock value
241 #ifndef queued_fetch_set_pending_acquire
242 static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
244 return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val);
249 * set_locked - Set the lock bit and own the lock
250 * @lock: Pointer to queued spinlock structure
254 static __always_inline void set_locked(struct qspinlock *lock)
256 WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
261 * Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for
262 * all the PV callbacks.
265 static __always_inline void __pv_init_node(struct mcs_spinlock *node) { }
266 static __always_inline void __pv_wait_node(struct mcs_spinlock *node,
267 struct mcs_spinlock *prev) { }
268 static __always_inline void __pv_kick_node(struct qspinlock *lock,
269 struct mcs_spinlock *node) { }
270 static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock,
271 struct mcs_spinlock *node)
274 #define pv_enabled() false
276 #define pv_init_node __pv_init_node
277 #define pv_wait_node __pv_wait_node
278 #define pv_kick_node __pv_kick_node
279 #define pv_wait_head_or_lock __pv_wait_head_or_lock
281 #ifdef CONFIG_PARAVIRT_SPINLOCKS
282 #define queued_spin_lock_slowpath native_queued_spin_lock_slowpath
285 #endif /* _GEN_PV_LOCK_SLOWPATH */
288 * queued_spin_lock_slowpath - acquire the queued spinlock
289 * @lock: Pointer to queued spinlock structure
290 * @val: Current value of the queued spinlock 32-bit word
292 * (queue tail, pending bit, lock value)
294 * fast : slow : unlock
296 * uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0)
297 * : | ^--------.------. / :
299 * pending : (0,1,1) +--> (0,1,0) \ | :
302 * uncontended : (n,x,y) +--> (n,0,0) --' | :
305 * contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' :
308 void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
310 struct mcs_spinlock *prev, *next, *node;
314 BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
319 if (virt_spin_lock(lock))
323 * Wait for in-progress pending->locked hand-overs with a bounded
324 * number of spins so that we guarantee forward progress.
328 if (val == _Q_PENDING_VAL) {
329 int cnt = _Q_PENDING_LOOPS;
330 val = atomic_cond_read_relaxed(&lock->val,
331 (VAL != _Q_PENDING_VAL) || !cnt--);
335 * If we observe any contention; queue.
337 if (val & ~_Q_LOCKED_MASK)
343 * 0,0,0 -> 0,0,1 ; trylock
344 * 0,0,1 -> 0,1,1 ; pending
346 val = queued_fetch_set_pending_acquire(lock);
349 * If we observe any contention; undo and queue.
351 if (unlikely(val & ~_Q_LOCKED_MASK)) {
352 if (!(val & _Q_PENDING_MASK))
358 * We're pending, wait for the owner to go away.
362 * this wait loop must be a load-acquire such that we match the
363 * store-release that clears the locked bit and create lock
364 * sequentiality; this is because not all
365 * clear_pending_set_locked() implementations imply full
368 if (val & _Q_LOCKED_MASK)
369 atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK));
372 * take ownership and clear the pending bit.
376 clear_pending_set_locked(lock);
377 qstat_inc(qstat_lock_pending, true);
381 * End of pending bit optimistic spinning and beginning of MCS
385 qstat_inc(qstat_lock_slowpath, true);
387 node = this_cpu_ptr(&mcs_nodes[0]);
389 tail = encode_tail(smp_processor_id(), idx);
394 * Ensure that we increment the head node->count before initialising
395 * the actual node. If the compiler is kind enough to reorder these
396 * stores, then an IRQ could overwrite our assignments.
405 * We touched a (possibly) cold cacheline in the per-cpu queue node;
406 * attempt the trylock once more in the hope someone let go while we
409 if (queued_spin_trylock(lock))
413 * Ensure that the initialisation of @node is complete before we
414 * publish the updated tail via xchg_tail() and potentially link
415 * @node into the waitqueue via WRITE_ONCE(prev->next, node) below.
420 * Publish the updated tail.
421 * We have already touched the queueing cacheline; don't bother with
426 old = xchg_tail(lock, tail);
430 * if there was a previous node; link it and wait until reaching the
431 * head of the waitqueue.
433 if (old & _Q_TAIL_MASK) {
434 prev = decode_tail(old);
436 /* Link @node into the waitqueue. */
437 WRITE_ONCE(prev->next, node);
439 pv_wait_node(node, prev);
440 arch_mcs_spin_lock_contended(&node->locked);
443 * While waiting for the MCS lock, the next pointer may have
444 * been set by another lock waiter. We optimistically load
445 * the next pointer & prefetch the cacheline for writing
446 * to reduce latency in the upcoming MCS unlock operation.
448 next = READ_ONCE(node->next);
454 * we're at the head of the waitqueue, wait for the owner & pending to
459 * this wait loop must use a load-acquire such that we match the
460 * store-release that clears the locked bit and create lock
461 * sequentiality; this is because the set_locked() function below
462 * does not imply a full barrier.
464 * The PV pv_wait_head_or_lock function, if active, will acquire
465 * the lock and return a non-zero value. So we have to skip the
466 * atomic_cond_read_acquire() call. As the next PV queue head hasn't
467 * been designated yet, there is no way for the locked value to become
468 * _Q_SLOW_VAL. So both the set_locked() and the
469 * atomic_cmpxchg_relaxed() calls will be safe.
471 * If PV isn't active, 0 will be returned instead.
474 if ((val = pv_wait_head_or_lock(lock, node)))
477 val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK));
483 * n,0,0 -> 0,0,1 : lock, uncontended
484 * *,*,0 -> *,*,1 : lock, contended
486 * If the queue head is the only one in the queue (lock value == tail)
487 * and nobody is pending, clear the tail code and grab the lock.
488 * Otherwise, we only need to grab the lock.
492 * In the PV case we might already have _Q_LOCKED_VAL set.
494 * The atomic_cond_read_acquire() call above has provided the
495 * necessary acquire semantics required for locking.
497 if (((val & _Q_TAIL_MASK) == tail) &&
498 atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))
499 goto release; /* No contention */
501 /* Either somebody is queued behind us or _Q_PENDING_VAL is set */
505 * contended path; wait for next if not observed yet, release.
508 next = smp_cond_load_relaxed(&node->next, (VAL));
510 arch_mcs_spin_unlock_contended(&next->locked);
511 pv_kick_node(lock, next);
517 __this_cpu_dec(mcs_nodes[0].count);
519 EXPORT_SYMBOL(queued_spin_lock_slowpath);
522 * Generate the paravirt code for queued_spin_unlock_slowpath().
524 #if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS)
525 #define _GEN_PV_LOCK_SLOWPATH
528 #define pv_enabled() true
533 #undef pv_wait_head_or_lock
535 #undef queued_spin_lock_slowpath
536 #define queued_spin_lock_slowpath __pv_queued_spin_lock_slowpath
538 #include "qspinlock_paravirt.h"
539 #include "qspinlock.c"