1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
5 * Copyright (C) 2011, Thomas Gleixner
9 #include <linux/slab.h>
10 #include <linux/export.h>
11 #include <linux/irqdomain.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/syscore_ops.h>
16 #include "internals.h"
18 static LIST_HEAD(gc_list);
19 static DEFINE_RAW_SPINLOCK(gc_lock);
22 * irq_gc_noop - NOOP function
25 void irq_gc_noop(struct irq_data *d)
28 EXPORT_SYMBOL_GPL(irq_gc_noop);
31 * irq_gc_mask_disable_reg - Mask chip via disable register
34 * Chip has separate enable/disable registers instead of a single mask
37 void irq_gc_mask_disable_reg(struct irq_data *d)
39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
40 struct irq_chip_type *ct = irq_data_get_chip_type(d);
44 irq_reg_writel(gc, mask, ct->regs.disable);
45 *ct->mask_cache &= ~mask;
48 EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
51 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
54 * Chip has a single mask register. Values of this register are cached
55 * and protected by gc->lock
57 void irq_gc_mask_set_bit(struct irq_data *d)
59 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
60 struct irq_chip_type *ct = irq_data_get_chip_type(d);
64 *ct->mask_cache |= mask;
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
68 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
71 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
74 * Chip has a single mask register. Values of this register are cached
75 * and protected by gc->lock
77 void irq_gc_mask_clr_bit(struct irq_data *d)
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
84 *ct->mask_cache &= ~mask;
85 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
88 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
91 * irq_gc_unmask_enable_reg - Unmask chip via enable register
94 * Chip has separate enable/disable registers instead of a single mask
97 void irq_gc_unmask_enable_reg(struct irq_data *d)
99 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
100 struct irq_chip_type *ct = irq_data_get_chip_type(d);
104 irq_reg_writel(gc, mask, ct->regs.enable);
105 *ct->mask_cache |= mask;
108 EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
111 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
114 void irq_gc_ack_set_bit(struct irq_data *d)
116 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
117 struct irq_chip_type *ct = irq_data_get_chip_type(d);
121 irq_reg_writel(gc, mask, ct->regs.ack);
124 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
127 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
130 void irq_gc_ack_clr_bit(struct irq_data *d)
132 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
133 struct irq_chip_type *ct = irq_data_get_chip_type(d);
137 irq_reg_writel(gc, mask, ct->regs.ack);
142 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
145 * This generic implementation of the irq_mask_ack method is for chips
146 * with separate enable/disable registers instead of a single mask
147 * register and where a pending interrupt is acknowledged by setting a
150 * Note: This is the only permutation currently used. Similar generic
151 * functions should be added here if other permutations are required.
153 void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
156 struct irq_chip_type *ct = irq_data_get_chip_type(d);
160 irq_reg_writel(gc, mask, ct->regs.disable);
161 *ct->mask_cache &= ~mask;
162 irq_reg_writel(gc, mask, ct->regs.ack);
167 * irq_gc_eoi - EOI interrupt
170 void irq_gc_eoi(struct irq_data *d)
172 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
173 struct irq_chip_type *ct = irq_data_get_chip_type(d);
177 irq_reg_writel(gc, mask, ct->regs.eoi);
182 * irq_gc_set_wake - Set/clr wake bit for an interrupt
184 * @on: Indicates whether the wake bit should be set or cleared
186 * For chips where the wake from suspend functionality is not
187 * configured in a separate register and the wakeup active state is
188 * just stored in a bitmask.
190 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
192 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
195 if (!(mask & gc->wake_enabled))
200 gc->wake_active |= mask;
202 gc->wake_active &= ~mask;
206 EXPORT_SYMBOL_GPL(irq_gc_set_wake);
208 static u32 irq_readl_be(void __iomem *addr)
210 return ioread32be(addr);
213 static void irq_writel_be(u32 val, void __iomem *addr)
215 iowrite32be(val, addr);
218 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
219 int num_ct, unsigned int irq_base,
220 void __iomem *reg_base, irq_flow_handler_t handler)
222 struct irq_chip_type *ct = gc->chip_types;
225 raw_spin_lock_init(&gc->lock);
227 gc->irq_base = irq_base;
228 gc->reg_base = reg_base;
229 for (i = 0; i < num_ct; i++)
230 ct[i].chip.name = name;
231 gc->chip_types->handler = handler;
235 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
236 * @name: Name of the irq chip
237 * @num_ct: Number of irq_chip_type instances associated with this
238 * @irq_base: Interrupt base nr for this chip
239 * @reg_base: Register base address (virtual)
240 * @handler: Default flow handler associated with this chip
242 * Returns an initialized irq_chip_generic structure. The chip defaults
243 * to the primary (index 0) irq_chip_type and @handler
245 struct irq_chip_generic *
246 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
247 void __iomem *reg_base, irq_flow_handler_t handler)
249 struct irq_chip_generic *gc;
251 gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
253 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
258 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
261 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
263 struct irq_chip_type *ct = gc->chip_types;
264 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
267 for (i = 0; i < gc->num_ct; i++) {
268 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
269 mskptr = &ct[i].mask_cache_priv;
270 mskreg = ct[i].regs.mask;
272 ct[i].mask_cache = mskptr;
273 if (flags & IRQ_GC_INIT_MASK_CACHE)
274 *mskptr = irq_reg_readl(gc, mskreg);
279 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
280 * @d: irq domain for which to allocate chips
281 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
282 * @num_ct: Number of irq_chip_type instances associated with this
283 * @name: Name of the irq chip
284 * @handler: Default flow handler associated with these chips
285 * @clr: IRQ_* bits to clear in the mapping function
286 * @set: IRQ_* bits to set in the mapping function
287 * @gcflags: Generic chip specific setup flags
289 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
290 int num_ct, const char *name,
291 irq_flow_handler_t handler,
292 unsigned int clr, unsigned int set,
293 enum irq_gc_flags gcflags)
295 struct irq_domain_chip_generic *dgc;
296 struct irq_chip_generic *gc;
307 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
311 /* Allocate a pointer, generic chip and chiptypes for each chip */
312 gc_sz = struct_size(gc, chip_types, num_ct);
313 dgc_sz = struct_size(dgc, gc, numchips);
314 sz = dgc_sz + numchips * gc_sz;
316 tmp = dgc = kzalloc(sz, GFP_KERNEL);
319 dgc->irqs_per_chip = irqs_per_chip;
320 dgc->num_chips = numchips;
321 dgc->irq_flags_to_set = set;
322 dgc->irq_flags_to_clear = clr;
323 dgc->gc_flags = gcflags;
326 /* Calc pointer to the first generic chip */
328 for (i = 0; i < numchips; i++) {
329 /* Store the pointer to the generic chip */
330 dgc->gc[i] = gc = tmp;
331 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
335 if (gcflags & IRQ_GC_BE_IO) {
336 gc->reg_readl = &irq_readl_be;
337 gc->reg_writel = &irq_writel_be;
340 raw_spin_lock_irqsave(&gc_lock, flags);
341 list_add_tail(&gc->list, &gc_list);
342 raw_spin_unlock_irqrestore(&gc_lock, flags);
343 /* Calc pointer to the next generic chip */
348 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
350 static struct irq_chip_generic *
351 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
353 struct irq_domain_chip_generic *dgc = d->gc;
357 return ERR_PTR(-ENODEV);
358 idx = hw_irq / dgc->irqs_per_chip;
359 if (idx >= dgc->num_chips)
360 return ERR_PTR(-EINVAL);
365 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
366 * @d: irq domain pointer
367 * @hw_irq: Hardware interrupt number
369 struct irq_chip_generic *
370 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
372 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
374 return !IS_ERR(gc) ? gc : NULL;
376 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
379 * Separate lockdep classes for interrupt chip which can nest irq_desc
380 * lock and request mutex.
382 static struct lock_class_key irq_nested_lock_class;
383 static struct lock_class_key irq_nested_request_class;
386 * irq_map_generic_chip - Map a generic chip for an irq domain
388 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
389 irq_hw_number_t hw_irq)
391 struct irq_data *data = irq_domain_get_irq_data(d, virq);
392 struct irq_domain_chip_generic *dgc = d->gc;
393 struct irq_chip_generic *gc;
394 struct irq_chip_type *ct;
395 struct irq_chip *chip;
399 gc = __irq_get_domain_generic_chip(d, hw_irq);
403 idx = hw_irq % dgc->irqs_per_chip;
405 if (test_bit(idx, &gc->unused))
408 if (test_bit(idx, &gc->installed))
414 /* We only init the cache for the first mapping of a generic chip */
415 if (!gc->installed) {
416 raw_spin_lock_irqsave(&gc->lock, flags);
417 irq_gc_init_mask_cache(gc, dgc->gc_flags);
418 raw_spin_unlock_irqrestore(&gc->lock, flags);
421 /* Mark the interrupt as installed */
422 set_bit(idx, &gc->installed);
424 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
425 irq_set_lockdep_class(virq, &irq_nested_lock_class,
426 &irq_nested_request_class);
428 if (chip->irq_calc_mask)
429 chip->irq_calc_mask(data);
431 data->mask = 1 << idx;
433 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
434 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
438 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
440 struct irq_data *data = irq_domain_get_irq_data(d, virq);
441 struct irq_domain_chip_generic *dgc = d->gc;
442 unsigned int hw_irq = data->hwirq;
443 struct irq_chip_generic *gc;
446 gc = irq_get_domain_generic_chip(d, hw_irq);
450 irq_idx = hw_irq % dgc->irqs_per_chip;
452 clear_bit(irq_idx, &gc->installed);
453 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
458 const struct irq_domain_ops irq_generic_chip_ops = {
459 .map = irq_map_generic_chip,
460 .unmap = irq_unmap_generic_chip,
461 .xlate = irq_domain_xlate_onetwocell,
463 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
466 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
467 * @gc: Generic irq chip holding all data
468 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
469 * @flags: Flags for initialization
470 * @clr: IRQ_* bits to clear
471 * @set: IRQ_* bits to set
473 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
474 * initializes all interrupts to the primary irq_chip_type and its
475 * associated handler.
477 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
478 enum irq_gc_flags flags, unsigned int clr,
481 struct irq_chip_type *ct = gc->chip_types;
482 struct irq_chip *chip = &ct->chip;
485 raw_spin_lock(&gc_lock);
486 list_add_tail(&gc->list, &gc_list);
487 raw_spin_unlock(&gc_lock);
489 irq_gc_init_mask_cache(gc, flags);
491 for (i = gc->irq_base; msk; msk >>= 1, i++) {
495 if (flags & IRQ_GC_INIT_NESTED_LOCK)
496 irq_set_lockdep_class(i, &irq_nested_lock_class,
497 &irq_nested_request_class);
499 if (!(flags & IRQ_GC_NO_MASK)) {
500 struct irq_data *d = irq_get_irq_data(i);
502 if (chip->irq_calc_mask)
503 chip->irq_calc_mask(d);
505 d->mask = 1 << (i - gc->irq_base);
507 irq_set_chip_and_handler(i, chip, ct->handler);
508 irq_set_chip_data(i, gc);
509 irq_modify_status(i, clr, set);
511 gc->irq_cnt = i - gc->irq_base;
513 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
516 * irq_setup_alt_chip - Switch to alternative chip
517 * @d: irq_data for this interrupt
518 * @type: Flow type to be initialized
520 * Only to be called from chip->irq_set_type() callbacks.
522 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
524 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
525 struct irq_chip_type *ct = gc->chip_types;
528 for (i = 0; i < gc->num_ct; i++, ct++) {
529 if (ct->type & type) {
531 irq_data_to_desc(d)->handle_irq = ct->handler;
537 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
540 * irq_remove_generic_chip - Remove a chip
541 * @gc: Generic irq chip holding all data
542 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
543 * @clr: IRQ_* bits to clear
544 * @set: IRQ_* bits to set
546 * Remove up to 32 interrupts starting from gc->irq_base.
548 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
549 unsigned int clr, unsigned int set)
551 unsigned int i, virq;
553 raw_spin_lock(&gc_lock);
555 raw_spin_unlock(&gc_lock);
557 for (i = 0; msk; msk >>= 1, i++) {
562 * Interrupt domain based chips store the base hardware
563 * interrupt number in gc::irq_base. Otherwise gc::irq_base
564 * contains the base Linux interrupt number.
567 virq = irq_find_mapping(gc->domain, gc->irq_base + i);
571 virq = gc->irq_base + i;
574 /* Remove handler first. That will mask the irq line */
575 irq_set_handler(virq, NULL);
576 irq_set_chip(virq, &no_irq_chip);
577 irq_set_chip_data(virq, NULL);
578 irq_modify_status(virq, clr, set);
581 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
583 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
588 return irq_get_irq_data(gc->irq_base);
591 * We don't know which of the irqs has been actually
592 * installed. Use the first one.
597 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
598 return virq ? irq_get_irq_data(virq) : NULL;
602 static int irq_gc_suspend(void)
604 struct irq_chip_generic *gc;
606 list_for_each_entry(gc, &gc_list, list) {
607 struct irq_chip_type *ct = gc->chip_types;
609 if (ct->chip.irq_suspend) {
610 struct irq_data *data = irq_gc_get_irq_data(gc);
613 ct->chip.irq_suspend(data);
622 static void irq_gc_resume(void)
624 struct irq_chip_generic *gc;
626 list_for_each_entry(gc, &gc_list, list) {
627 struct irq_chip_type *ct = gc->chip_types;
632 if (ct->chip.irq_resume) {
633 struct irq_data *data = irq_gc_get_irq_data(gc);
636 ct->chip.irq_resume(data);
641 #define irq_gc_suspend NULL
642 #define irq_gc_resume NULL
645 static void irq_gc_shutdown(void)
647 struct irq_chip_generic *gc;
649 list_for_each_entry(gc, &gc_list, list) {
650 struct irq_chip_type *ct = gc->chip_types;
652 if (ct->chip.irq_pm_shutdown) {
653 struct irq_data *data = irq_gc_get_irq_data(gc);
656 ct->chip.irq_pm_shutdown(data);
661 static struct syscore_ops irq_gc_syscore_ops = {
662 .suspend = irq_gc_suspend,
663 .resume = irq_gc_resume,
664 .shutdown = irq_gc_shutdown,
667 static int __init irq_gc_init_ops(void)
669 register_syscore_ops(&irq_gc_syscore_ops);
672 device_initcall(irq_gc_init_ops);