1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
14 #include <linux/linkage.h>
15 #include <linux/threads.h>
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/serial_reg.h>
19 #include <asm/processor.h>
22 #include <asm/pgtable.h>
23 #include <asm/thread_info.h>
24 #include <asm/cache.h>
25 #include <asm/spr_defs.h>
26 #include <asm/asm-offsets.h>
27 #include <linux/of_fdt.h>
29 #define tophys(rd,rs) \
30 l.movhi rd,hi(-KERNELBASE) ;\
33 #define CLEAR_GPR(gpr) \
36 #define LOAD_SYMBOL_2_GPR(gpr,symbol) \
37 l.movhi gpr,hi(symbol) ;\
38 l.ori gpr,gpr,lo(symbol)
41 #define UART_BASE_ADD 0x90000000
43 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
44 #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
46 /* ============================================[ tmp store locations ]=== */
48 #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
51 * emergency_print temporary stores
53 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
54 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
72 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
94 * TLB miss handlers temorary stores
96 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
97 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
98 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
100 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
101 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
103 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
104 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
106 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
107 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
109 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
110 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
112 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
131 * EXCEPTION_HANDLE temporary stores
134 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
135 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
136 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
138 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
139 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
141 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
142 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
144 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
155 /* =========================================================[ macros ]=== */
158 #define GET_CURRENT_PGD(reg,t1) \
159 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
160 l.mfspr t1,r0,SPR_COREID ;\
166 #define GET_CURRENT_PGD(reg,t1) \
167 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
172 /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
174 #define GET_CURRENT_THREAD_INFO \
175 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
177 l.mfspr r10,r0,SPR_COREID ;\
180 /* r10: current_thread_info */ ;\
183 #define GET_CURRENT_THREAD_INFO \
184 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
186 /* r10: current_thread_info */ ;\
191 * DSCR: this is a common hook for handling exceptions. it will save
192 * the needed registers, set up stack and pointer to current
193 * then jump to the handler while enabling MMU
195 * PRMS: handler - a function to jump to. it has to save the
196 * remaining registers to kernel stack, call
197 * appropriate arch-independant exception handler
198 * and finaly jump to ret_from_except
200 * PREQ: unchanged state from the time exception happened
202 * POST: SAVED the following registers original value
203 * to the new created exception frame pointed to by r1
205 * r1 - ksp pointing to the new (exception) frame
206 * r4 - EEAR exception EA
207 * r10 - current pointing to current_thread_info struct
208 * r12 - syscall 0, since we didn't come from syscall
209 * r30 - handler address of the handler we'll jump to
211 * handler has to save remaining registers to the exception
212 * ksp frame *before* tainting them!
214 * NOTE: this function is not reentrant per se. reentrancy is guaranteed
215 * by processor disabling all exceptions/interrupts when exception
218 * OPTM: no need to make it so wasteful to extract ksp when in user mode
221 #define EXCEPTION_HANDLE(handler) \
222 EXCEPTION_T_STORE_GPR30 ;\
223 l.mfspr r30,r0,SPR_ESR_BASE ;\
224 l.andi r30,r30,SPR_SR_SM ;\
226 EXCEPTION_T_STORE_GPR10 ;\
227 l.bnf 2f /* kernel_mode */ ;\
228 EXCEPTION_T_STORE_SP /* delay slot */ ;\
229 1: /* user_mode: */ ;\
230 GET_CURRENT_THREAD_INFO ;\
232 l.lwz r1,(TI_KSP)(r30) ;\
233 /* fall through */ ;\
234 2: /* kernel_mode: */ ;\
235 /* create new stack frame, save only needed gprs */ ;\
236 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
237 /* r12: temp, syscall indicator */ ;\
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
239 /* r1 is KSP, r30 is __pa(KSP) */ ;\
241 l.sw PT_GPR12(r30),r12 ;\
242 /* r4 use for tmp before EA */ ;\
243 l.mfspr r12,r0,SPR_EPCR_BASE ;\
244 l.sw PT_PC(r30),r12 ;\
245 l.mfspr r12,r0,SPR_ESR_BASE ;\
246 l.sw PT_SR(r30),r12 ;\
248 EXCEPTION_T_LOAD_GPR30(r12) ;\
249 l.sw PT_GPR30(r30),r12 ;\
250 /* save r10 as was prior to exception */ ;\
251 EXCEPTION_T_LOAD_GPR10(r12) ;\
252 l.sw PT_GPR10(r30),r12 ;\
253 /* save PT_SP as was prior to exception */ ;\
254 EXCEPTION_T_LOAD_SP(r12) ;\
255 l.sw PT_SP(r30),r12 ;\
256 /* save exception r4, set r4 = EA */ ;\
257 l.sw PT_GPR4(r30),r4 ;\
258 l.mfspr r4,r0,SPR_EEAR_BASE ;\
259 /* r12 == 1 if we come from syscall */ ;\
261 /* ----- turn on MMU ----- */ ;\
262 /* Carry DSX into exception SR */ ;\
263 l.mfspr r30,r0,SPR_SR ;\
264 l.andi r30,r30,SPR_SR_DSX ;\
265 l.ori r30,r30,(EXCEPTION_SR) ;\
266 l.mtspr r0,r30,SPR_ESR_BASE ;\
267 /* r30: EA address of handler */ ;\
268 LOAD_SYMBOL_2_GPR(r30,handler) ;\
269 l.mtspr r0,r30,SPR_EPCR_BASE ;\
276 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
277 * #define UNHANDLED_EXCEPTION(handler) \
279 * l.mtspr r0,r3,SPR_SR ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
288 /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
289 * a bit more carefull (if we have a PT_SP or current pointer
290 * corruption) and set them up from 'current_set'
293 #define UNHANDLED_EXCEPTION(handler) \
294 EXCEPTION_T_STORE_GPR30 ;\
295 EXCEPTION_T_STORE_GPR10 ;\
296 EXCEPTION_T_STORE_SP ;\
297 /* temporary store r3, r9 into r1, r10 */ ;\
300 /* the string referenced by r3 must be low enough */ ;\
301 l.jal _emergency_print ;\
302 l.ori r3,r0,lo(_string_unhandled_exception) ;\
303 l.mfspr r3,r0,SPR_NPC ;\
304 l.jal _emergency_print_nr ;\
305 l.andi r3,r3,0x1f00 ;\
306 /* the string referenced by r3 must be low enough */ ;\
307 l.jal _emergency_print ;\
308 l.ori r3,r0,lo(_string_epc_prefix) ;\
309 l.jal _emergency_print_nr ;\
310 l.mfspr r3,r0,SPR_EPCR_BASE ;\
311 l.jal _emergency_print ;\
312 l.ori r3,r0,lo(_string_nl) ;\
313 /* end of printing */ ;\
316 /* extract current, ksp from current_set */ ;\
317 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
318 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
319 /* create new stack frame, save only needed gprs */ ;\
320 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
321 /* r12: temp, syscall indicator, r13 temp */ ;\
322 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
323 /* r1 is KSP, r30 is __pa(KSP) */ ;\
325 l.sw PT_GPR12(r30),r12 ;\
326 l.mfspr r12,r0,SPR_EPCR_BASE ;\
327 l.sw PT_PC(r30),r12 ;\
328 l.mfspr r12,r0,SPR_ESR_BASE ;\
329 l.sw PT_SR(r30),r12 ;\
331 EXCEPTION_T_LOAD_GPR30(r12) ;\
332 l.sw PT_GPR30(r30),r12 ;\
333 /* save r10 as was prior to exception */ ;\
334 EXCEPTION_T_LOAD_GPR10(r12) ;\
335 l.sw PT_GPR10(r30),r12 ;\
336 /* save PT_SP as was prior to exception */ ;\
337 EXCEPTION_T_LOAD_SP(r12) ;\
338 l.sw PT_SP(r30),r12 ;\
339 l.sw PT_GPR13(r30),r13 ;\
341 /* save exception r4, set r4 = EA */ ;\
342 l.sw PT_GPR4(r30),r4 ;\
343 l.mfspr r4,r0,SPR_EEAR_BASE ;\
344 /* r12 == 1 if we come from syscall */ ;\
346 /* ----- play a MMU trick ----- */ ;\
347 l.ori r30,r0,(EXCEPTION_SR) ;\
348 l.mtspr r0,r30,SPR_ESR_BASE ;\
349 /* r31: EA address of handler */ ;\
350 LOAD_SYMBOL_2_GPR(r30,handler) ;\
351 l.mtspr r0,r30,SPR_EPCR_BASE ;\
354 /* =====================================================[ exceptions] === */
356 /* ---[ 0x100: RESET exception ]----------------------------------------- */
358 /* Jump to .init code at _start which lives in the .head section
359 * and will be discarded after boot.
361 LOAD_SYMBOL_2_GPR(r15, _start)
362 tophys (r13,r15) /* MMU disabled */
366 /* ---[ 0x200: BUS exception ]------------------------------------------- */
369 EXCEPTION_HANDLE(_bus_fault_handler)
371 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
373 _dispatch_do_dpage_fault:
374 // totaly disable timer interrupt
375 // l.mtspr r0,r0,SPR_TTMR
376 // DEBUG_TLB_PROBE(0x300)
377 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
378 EXCEPTION_HANDLE(_data_page_fault_handler)
380 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
382 _dispatch_do_ipage_fault:
383 // totaly disable timer interrupt
384 // l.mtspr r0,r0,SPR_TTMR
385 // DEBUG_TLB_PROBE(0x400)
386 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
387 EXCEPTION_HANDLE(_insn_page_fault_handler)
389 /* ---[ 0x500: Timer exception ]----------------------------------------- */
391 EXCEPTION_HANDLE(_timer_handler)
393 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
395 EXCEPTION_HANDLE(_alignment_handler)
397 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
399 EXCEPTION_HANDLE(_illegal_instruction_handler)
401 /* ---[ 0x800: External interrupt exception ]---------------------------- */
403 EXCEPTION_HANDLE(_external_irq_handler)
405 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
407 l.j boot_dtlb_miss_handler
410 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
412 l.j boot_itlb_miss_handler
415 /* ---[ 0xb00: Range exception ]----------------------------------------- */
417 UNHANDLED_EXCEPTION(_vector_0xb00)
419 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
421 EXCEPTION_HANDLE(_sys_call_handler)
423 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
425 UNHANDLED_EXCEPTION(_vector_0xd00)
427 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
429 // UNHANDLED_EXCEPTION(_vector_0xe00)
430 EXCEPTION_HANDLE(_trap_handler)
432 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
434 UNHANDLED_EXCEPTION(_vector_0xf00)
436 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
438 UNHANDLED_EXCEPTION(_vector_0x1000)
440 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
442 UNHANDLED_EXCEPTION(_vector_0x1100)
444 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
446 UNHANDLED_EXCEPTION(_vector_0x1200)
448 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
450 UNHANDLED_EXCEPTION(_vector_0x1300)
452 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
454 UNHANDLED_EXCEPTION(_vector_0x1400)
456 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
458 UNHANDLED_EXCEPTION(_vector_0x1500)
460 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
462 UNHANDLED_EXCEPTION(_vector_0x1600)
464 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
466 UNHANDLED_EXCEPTION(_vector_0x1700)
468 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
470 UNHANDLED_EXCEPTION(_vector_0x1800)
472 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
474 UNHANDLED_EXCEPTION(_vector_0x1900)
476 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
478 UNHANDLED_EXCEPTION(_vector_0x1a00)
480 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
482 UNHANDLED_EXCEPTION(_vector_0x1b00)
484 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
486 UNHANDLED_EXCEPTION(_vector_0x1c00)
488 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
490 UNHANDLED_EXCEPTION(_vector_0x1d00)
492 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
494 UNHANDLED_EXCEPTION(_vector_0x1e00)
496 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
498 UNHANDLED_EXCEPTION(_vector_0x1f00)
501 /* ===================================================[ kernel start ]=== */
505 /* This early stuff belongs in HEAD, but some of the functions below definitely
511 /* Init r0 to zero as per spec */
514 /* save kernel parameters */
515 l.or r25,r0,r3 /* pointer to fdt */
518 * ensure a deterministic start
525 * Start the TTCR as early as possible, so that the RNG can make use of
526 * measurements of boot time from the earliest opportunity. Especially
527 * important is that the TTCR does not return zero by the time we reach
530 l.movhi r3,hi(SPR_TTMR_CR)
531 l.mtspr r0,r3,SPR_TTMR
565 l.mfspr r26,r0,SPR_COREID
571 * set up initial ksp and current
573 /* setup kernel stack */
574 LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE)
575 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
583 * .data contains initialized data,
584 * .bss contains uninitialized data - clear it up
587 LOAD_SYMBOL_2_GPR(r24, __bss_start)
588 LOAD_SYMBOL_2_GPR(r26, _end)
611 /* The MMU needs to be enabled before or32_early_setup is called */
616 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
618 l.mfspr r30,r0,SPR_SR
619 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
620 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
622 l.mtspr r0,r30,SPR_SR
640 // reset the simulation counters
643 /* check fdt header magic word */
644 l.lwz r3,0(r25) /* load magic from fdt into r3 */
645 l.movhi r4,hi(OF_DT_HEADER)
646 l.ori r4,r4,lo(OF_DT_HEADER)
650 /* magic number mismatch, set fdt pointer to null */
653 /* pass fdt pointer to or32_early_setup in r3 */
655 LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
661 * clear all GPRS to increase determinism
695 * jump to kernel entry (start_kernel)
697 LOAD_SYMBOL_2_GPR(r30, start_kernel)
703 * I N V A L I D A T E T L B e n t r i e s
705 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
706 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
707 l.addi r7,r0,128 /* Maximum number of sets */
723 /* Doze the cpu until we are asked to run */
724 /* If we dont have power management skip doze */
725 l.mfspr r25,r0,SPR_UPR
726 l.andi r25,r25,SPR_UPR_PMP
728 l.bf secondary_check_release
731 /* Setup special secondary exception handler */
732 LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
734 l.mtspr r0,r25,SPR_EVBAR
736 /* Enable Interrupts */
737 l.mfspr r25,r0,SPR_SR
738 l.ori r25,r25,SPR_SR_IEE
739 l.mtspr r0,r25,SPR_SR
741 /* Unmask interrupts interrupts */
742 l.mfspr r25,r0,SPR_PICMR
744 l.mtspr r0,r25,SPR_PICMR
747 l.mfspr r25,r0,SPR_PMR
748 LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
750 l.mtspr r0,r25,SPR_PMR
752 /* Wakeup - Restore exception handler */
753 l.mtspr r0,r0,SPR_EVBAR
755 secondary_check_release:
757 * Check if we actually got the release signal, if not go-back to
760 l.mfspr r25,r0,SPR_COREID
761 LOAD_SYMBOL_2_GPR(r3, secondary_release)
767 /* fall through to secondary_init */
771 * set up initial ksp and current
773 LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
776 l.addi r1,r10,THREAD_SIZE
792 l.mfspr r30,r0,SPR_SR
793 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
794 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
797 * This is a bit tricky, we need to switch over from physical addresses
798 * to virtual addresses on the fly.
799 * To do that, we first set up ESR with the IME and DME bits set.
800 * Then EPCR is set to secondary_start and then a l.rfe is issued to
803 l.mtspr r0,r30,SPR_ESR_BASE
804 LOAD_SYMBOL_2_GPR(r30, secondary_start)
805 l.mtspr r0,r30,SPR_EPCR_BASE
809 LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel)
815 /* ========================================[ cache ]=== */
817 /* alignment here so we don't change memory offsets with
818 * memory controller defined
823 /* Check if IC present and skip enabling otherwise */
824 l.mfspr r24,r0,SPR_UPR
825 l.andi r26,r24,SPR_UPR_ICP
833 l.xori r5,r5,SPR_SR_ICE
837 /* Establish cache block size
840 r14 contain block size
842 l.mfspr r24,r0,SPR_ICCFGR
843 l.andi r26,r24,SPR_ICCFGR_CBS
848 /* Establish number of cache sets
849 r16 contains number of cache sets
850 r28 contains log(# of cache sets)
852 l.andi r26,r24,SPR_ICCFGR_NCS
862 // l.addi r5,r0,IC_SIZE
864 l.mtspr r0,r6,SPR_ICBIR
868 // l.addi r6,r6,IC_LINE
872 l.ori r6,r6,SPR_SR_ICE
889 /* Check if DC present and skip enabling otherwise */
890 l.mfspr r24,r0,SPR_UPR
891 l.andi r26,r24,SPR_UPR_DCP
899 l.xori r5,r5,SPR_SR_DCE
903 /* Establish cache block size
906 r14 contain block size
908 l.mfspr r24,r0,SPR_DCCFGR
909 l.andi r26,r24,SPR_DCCFGR_CBS
914 /* Establish number of cache sets
915 r16 contains number of cache sets
916 r28 contains log(# of cache sets)
918 l.andi r26,r24,SPR_DCCFGR_NCS
927 l.mtspr r0,r6,SPR_DCBIR
934 l.ori r6,r6,SPR_SR_DCE
940 /* ===============================================[ page table masks ]=== */
942 #define DTLB_UP_CONVERT_MASK 0x3fa
943 #define ITLB_UP_CONVERT_MASK 0x3a
945 /* for SMP we'd have (this is a bit subtle, CC must be always set
946 * for SMP, but since we have _PAGE_PRESENT bit always defined
947 * we can just modify the mask)
949 #define DTLB_SMP_CONVERT_MASK 0x3fb
950 #define ITLB_SMP_CONVERT_MASK 0x3b
952 /* ---[ boot dtlb miss handler ]----------------------------------------- */
954 boot_dtlb_miss_handler:
956 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
957 * - (31-12) sets bits belonging to VPN (31-12)
959 #define DTLB_MR_MASK 0xfffff001
961 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
962 * - (4) sets A (access) bit,
963 * - (5) sets D (dirty) bit,
964 * - (8) sets SRE (superuser read) bit
965 * - (9) sets SWE (superuser write) bit
966 * - (31-12) sets bits belonging to VPN (31-12)
968 #define DTLB_TR_MASK 0xfffff332
970 /* These are for masking out the VPN/PPN value from the MR/TR registers...
971 * it's not the same as the PFN */
972 #define VPN_MASK 0xfffff000
973 #define PPN_MASK 0xfffff000
979 l.mfspr r6,r0,SPR_ESR_BASE //
980 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
981 l.sfeqi r6,0 // r6 == 0x1 --> SM
982 l.bf exit_with_no_dtranslation //
986 /* this could be optimized by moving storing of
987 * non r6 registers here, and jumping r6 restore
988 * if not in supervisor mode
996 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
998 immediate_translation:
1001 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
1003 l.mfspr r6, r0, SPR_DMMUCFGR
1004 l.andi r6, r6, SPR_DMMUCFGR_NTS
1005 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1007 l.sll r5, r5, r6 // r5 = number DMMU sets
1008 l.addi r6, r5, -1 // r6 = nsets mask
1009 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1011 l.or r6,r6,r4 // r6 <- r4
1012 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1013 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1014 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1015 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1016 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1018 /* set up DTLB with no translation for EA <= 0xbfffffff */
1019 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1020 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1022 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1024 tophys(r3,r4) // r3 <- PA
1026 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1027 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1028 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1029 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1030 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1038 l.rfe // SR <- ESR, PC <- EPC
1040 exit_with_no_dtranslation:
1041 /* EA out of memory or not in supervisor mode */
1044 l.j _dispatch_bus_fault
1046 /* ---[ boot itlb miss handler ]----------------------------------------- */
1048 boot_itlb_miss_handler:
1050 /* mask for ITLB_MR register: - sets V (valid) bit,
1051 * - sets bits belonging to VPN (15-12)
1053 #define ITLB_MR_MASK 0xfffff001
1055 /* mask for ITLB_TR register: - sets A (access) bit,
1056 * - sets SXE (superuser execute) bit
1057 * - sets bits belonging to VPN (15-12)
1059 #define ITLB_TR_MASK 0xfffff050
1062 #define VPN_MASK 0xffffe000
1063 #define PPN_MASK 0xffffe000
1068 EXCEPTION_STORE_GPR2
1069 EXCEPTION_STORE_GPR3
1070 EXCEPTION_STORE_GPR4
1071 EXCEPTION_STORE_GPR5
1072 EXCEPTION_STORE_GPR6
1075 l.mfspr r6,r0,SPR_ESR_BASE //
1076 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1077 l.sfeqi r6,0 // r6 == 0x1 --> SM
1078 l.bf exit_with_no_itranslation
1083 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1088 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
1090 l.mfspr r6, r0, SPR_IMMUCFGR
1091 l.andi r6, r6, SPR_IMMUCFGR_NTS
1092 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1094 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1095 l.addi r6, r5, -1 // r6 = nsets mask
1096 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1098 l.or r6,r6,r4 // r6 <- r4
1099 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1100 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1101 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1102 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1103 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1106 * set up ITLB with no translation for EA <= 0x0fffffff
1108 * we need this for head.S mapping (EA = PA). if we move all functions
1109 * which run with mmu enabled into entry.S, we might be able to eliminate this.
1112 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1113 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1115 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1117 tophys(r3,r4) // r3 <- PA
1119 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1120 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1121 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1122 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1123 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1131 l.rfe // SR <- ESR, PC <- EPC
1133 exit_with_no_itranslation:
1136 l.j _dispatch_bus_fault
1139 /* ====================================================================== */
1141 * Stuff below here shouldn't go into .head section... maybe this stuff
1142 * can be moved to entry.S ???
1145 /* ==============================================[ DTLB miss handler ]=== */
1149 * Exception handlers are entered with MMU off so the following handler
1150 * needs to use physical addressing
1155 ENTRY(dtlb_miss_handler)
1156 EXCEPTION_STORE_GPR2
1157 EXCEPTION_STORE_GPR3
1158 EXCEPTION_STORE_GPR4
1160 * get EA of the miss
1162 l.mfspr r2,r0,SPR_EEAR_BASE
1164 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1166 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
1167 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1168 l.slli r4,r4,0x2 // to get address << 2
1169 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1171 * if (pmd_none(*pmd))
1175 l.lwz r3,0x0(r4) // get *pmd value
1178 l.addi r3,r0,0xffffe000 // PAGE_MASK
1182 * pte = *pte_offset(pmd, daddr);
1184 l.lwz r4,0x0(r4) // get **pmd value
1185 l.and r4,r4,r3 // & PAGE_MASK
1186 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1187 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1188 l.slli r3,r3,0x2 // to get address << 2
1190 l.lwz r3,0x0(r3) // this is pte at last
1192 * if (!pte_present(pte))
1195 l.sfne r4,r0 // is pte present
1196 l.bnf d_pte_not_present
1197 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1199 * fill DTLB TR register
1201 l.and r4,r3,r4 // apply the mask
1202 // Determine number of DMMU sets
1203 l.mfspr r2, r0, SPR_DMMUCFGR
1204 l.andi r2, r2, SPR_DMMUCFGR_NTS
1205 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1207 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1208 l.addi r2, r3, -1 // r2 = nsets mask
1209 l.mfspr r3, r0, SPR_EEAR_BASE
1210 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1211 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1213 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1215 * fill DTLB MR register
1217 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1218 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1219 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1230 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
1232 /* ==============================================[ ITLB miss handler ]=== */
1233 ENTRY(itlb_miss_handler)
1234 EXCEPTION_STORE_GPR2
1235 EXCEPTION_STORE_GPR3
1236 EXCEPTION_STORE_GPR4
1238 * get EA of the miss
1240 l.mfspr r2,r0,SPR_EEAR_BASE
1243 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1246 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
1247 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1248 l.slli r4,r4,0x2 // to get address << 2
1249 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1251 * if (pmd_none(*pmd))
1255 l.lwz r3,0x0(r4) // get *pmd value
1258 l.addi r3,r0,0xffffe000 // PAGE_MASK
1262 * pte = *pte_offset(pmd, iaddr);
1265 l.lwz r4,0x0(r4) // get **pmd value
1266 l.and r4,r4,r3 // & PAGE_MASK
1267 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1268 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1269 l.slli r3,r3,0x2 // to get address << 2
1271 l.lwz r3,0x0(r3) // this is pte at last
1273 * if (!pte_present(pte))
1277 l.sfne r4,r0 // is pte present
1278 l.bnf i_pte_not_present
1279 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1281 * fill ITLB TR register
1283 l.and r4,r3,r4 // apply the mask
1284 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1286 l.bf itlb_tr_fill //_workaround
1287 // Determine number of IMMU sets
1288 l.mfspr r2, r0, SPR_IMMUCFGR
1289 l.andi r2, r2, SPR_IMMUCFGR_NTS
1290 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1292 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1293 l.addi r2, r3, -1 // r2 = nsets mask
1294 l.mfspr r3, r0, SPR_EEAR_BASE
1295 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1296 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1300 * we should not just blindly set executable flags,
1301 * but it does help with ping. the clean way would be to find out
1302 * (and fix it) why stack doesn't have execution permissions
1305 itlb_tr_fill_workaround:
1306 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1308 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1310 * fill DTLB MR register
1312 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1313 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1314 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1326 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
1328 /* ==============================================[ boot tlb handlers ]=== */
1331 /* =================================================[ debugging aids ]=== */
1336 _immu_trampoline_top:
1338 #define TRAMP_SLOT_0 (0x0)
1339 #define TRAMP_SLOT_1 (0x4)
1340 #define TRAMP_SLOT_2 (0x8)
1341 #define TRAMP_SLOT_3 (0xc)
1342 #define TRAMP_SLOT_4 (0x10)
1343 #define TRAMP_SLOT_5 (0x14)
1344 #define TRAMP_FRAME_SIZE (0x18)
1346 ENTRY(_immu_trampoline_workaround)
1348 // r6 is physical EEA
1351 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1352 tophys (r3,r5) // r3 is trampoline (physical)
1354 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1355 l.sw TRAMP_SLOT_0(r3),r4
1356 l.sw TRAMP_SLOT_1(r3),r4
1357 l.sw TRAMP_SLOT_4(r3),r4
1358 l.sw TRAMP_SLOT_5(r3),r4
1361 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1362 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1363 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1364 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1366 l.srli r5,r4,26 // check opcode for write access
1369 l.sfeqi r5,0x11 // l.jr
1371 l.sfeqi r5,1 // l.jal
1373 l.sfeqi r5,0x12 // l.jalr
1375 l.sfeqi r5,3 // l.bnf
1377 l.sfeqi r5,4 // l.bf
1381 l.j 99b // should never happen
1385 // r3 is trampoline address (physical)
1386 // r4 is instruction
1387 // r6 is physical(EEA)
1393 /* 19 20 aa aa l.movhi r9,0xaaaa
1394 * a9 29 bb bb l.ori r9,0xbbbb
1396 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1399 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1401 // l.movhi r9,0xaaaa
1402 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1403 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1405 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1408 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1409 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1411 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1413 /* falthrough, need to set up new jump offset */
1417 l.slli r6,r4,6 // original offset shifted left 6 - 2
1418 // l.srli r6,r6,6 // original offset shifted right 2
1420 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1421 // l.srli r4,r4,6 // old jump position: shifted right 2
1423 l.addi r5,r3,0xc // new jump position (physical)
1424 l.slli r5,r5,4 // new jump position: shifted left 4
1426 // calculate new jump offset
1427 // new_off = old_off + (old_jump - new_jump)
1429 l.sub r5,r4,r5 // old_jump - new_jump
1430 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1431 l.srli r5,r5,6 // new offset shifted right 2
1433 // r5 is new jump offset
1434 // l.j has opcode 0x0...
1435 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1440 /* ----------------------------- */
1444 /* 19 20 aa aa l.movhi r9,0xaaaa
1445 * a9 29 bb bb l.ori r9,0xbbbb
1447 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1450 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1452 // l.movhi r9,0xaaaa
1453 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1454 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1456 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1459 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1460 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1462 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1464 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1465 l.andi r5,r5,0x3ff // clear out opcode part
1466 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1467 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1475 /* ----------------------------- */
1479 l.slli r6,r4,6 // original offset shifted left 6 - 2
1480 // l.srli r6,r6,6 // original offset shifted right 2
1482 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1483 // l.srli r4,r4,6 // old jump position: shifted right 2
1485 l.addi r5,r3,0xc // new jump position (physical)
1486 l.slli r5,r5,4 // new jump position: shifted left 4
1488 // calculate new jump offset
1489 // new_off = old_off + (old_jump - new_jump)
1491 l.add r6,r6,r4 // (orig_off + old_jump)
1492 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1493 l.srli r6,r6,6 // new offset shifted right 2
1495 // r6 is new jump offset
1496 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1498 l.andi r4,r4,0xfc00 // get opcode part
1500 l.or r6,r4,r6 // l.b(n)f new offset
1501 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1503 /* we need to add l.j to EEA + 0x8 */
1504 tophys (r4,r2) // may not be needed (due to shifts down_
1505 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1506 // jump position = r5 + 0x8 (0x8 compensated)
1507 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1509 l.slli r4,r4,4 // the amount of info in imediate of jump
1510 l.srli r4,r4,6 // jump instruction with offset
1511 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1516 // set up new EPC to point to our trampoline code
1517 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1518 l.mtspr r0,r5,SPR_EPCR_BASE
1520 // immu_trampoline is (4x) CACHE_LINE aligned
1521 // and only 6 instructions long,
1522 // so we need to invalidate only 2 lines
1524 /* Establish cache block size
1527 r14 contain block size
1529 l.mfspr r21,r0,SPR_ICCFGR
1530 l.andi r21,r21,SPR_ICCFGR_CBS
1535 l.mtspr r0,r5,SPR_ICBIR
1537 l.mtspr r0,r5,SPR_ICBIR
1544 * DSCR: prints a string referenced by r3.
1546 * PRMS: r3 - address of the first character of null
1547 * terminated string to be printed
1549 * PREQ: UART at UART_BASE_ADD has to be initialized
1551 * POST: caller should be aware that r3, r9 are changed
1553 ENTRY(_emergency_print)
1554 EMERGENCY_PRINT_STORE_GPR4
1555 EMERGENCY_PRINT_STORE_GPR5
1556 EMERGENCY_PRINT_STORE_GPR6
1557 EMERGENCY_PRINT_STORE_GPR7
1565 l.movhi r4,hi(UART_BASE_ADD)
1583 /* next character */
1588 EMERGENCY_PRINT_LOAD_GPR7
1589 EMERGENCY_PRINT_LOAD_GPR6
1590 EMERGENCY_PRINT_LOAD_GPR5
1591 EMERGENCY_PRINT_LOAD_GPR4
1595 ENTRY(_emergency_print_nr)
1596 EMERGENCY_PRINT_STORE_GPR4
1597 EMERGENCY_PRINT_STORE_GPR5
1598 EMERGENCY_PRINT_STORE_GPR6
1599 EMERGENCY_PRINT_STORE_GPR7
1600 EMERGENCY_PRINT_STORE_GPR8
1602 l.addi r8,r0,32 // shift register
1604 1: /* remove leading zeros */
1609 /* don't skip the last zero if number == 0x0 */
1633 l.movhi r4,hi(UART_BASE_ADD)
1651 /* next character */
1656 EMERGENCY_PRINT_LOAD_GPR8
1657 EMERGENCY_PRINT_LOAD_GPR7
1658 EMERGENCY_PRINT_LOAD_GPR6
1659 EMERGENCY_PRINT_LOAD_GPR5
1660 EMERGENCY_PRINT_LOAD_GPR4
1666 * This should be used for debugging only.
1667 * It messes up the Linux early serial output
1668 * somehow, so use it sparingly and essentially
1669 * only if you need to debug something that goes wrong
1670 * before Linux gets the early serial going.
1672 * Furthermore, you'll have to make sure you set the
1673 * UART_DEVISOR correctly according to the system
1681 #define SYS_CLK 20000000
1682 //#define SYS_CLK 1843200
1683 #define OR32_CONSOLE_BAUD 115200
1684 #define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
1686 ENTRY(_early_uart_init)
1687 l.movhi r3,hi(UART_BASE_ADD)
1701 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1702 l.sb UART_DLM(r3),r4
1703 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1704 l.sb UART_DLL(r3),r4
1711 .global _secondary_evbar
1715 /* Just disable interrupts and Return */
1716 l.ori r3,r0,SPR_SR_SM
1717 l.mtspr r0,r3,SPR_ESR_BASE
1722 _string_unhandled_exception:
1723 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1726 .string ": EPC=0x\0"
1732 /* ========================================[ page aligned structures ]=== */
1735 * .data section should be page aligned
1736 * (look into arch/openrisc/kernel/vmlinux.lds.S)
1740 .global empty_zero_page
1744 .global swapper_pg_dir
1748 .global _unhandled_stack
1751 _unhandled_stack_top:
1753 /* ============================================================[ EOF ]=== */