3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ptrace.h>
35 #include <asm/export.h>
36 #include <asm/asm-405.h>
37 #include <asm/feature-fixups.h>
38 #include <asm/barrier.h>
41 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
43 #if MSR_KERNEL >= 0x10000
44 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
46 #define LOAD_MSR_KERNEL(r, x) li r,(x)
50 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
51 * fit into one page in order to not encounter a TLB miss between the
52 * modification of srr0/srr1 and the associated rfi.
57 .globl mcheck_transfer_to_handler
58 mcheck_transfer_to_handler:
65 .globl debug_transfer_to_handler
66 debug_transfer_to_handler:
73 .globl crit_transfer_to_handler
74 crit_transfer_to_handler:
75 #ifdef CONFIG_PPC_BOOK3E_MMU
86 #ifdef CONFIG_PHYS_64BIT
89 #endif /* CONFIG_PHYS_64BIT */
90 #endif /* CONFIG_PPC_BOOK3E_MMU */
100 /* set the stack limit to the current stack
101 * and set the limit to protect the thread_info
104 mfspr r8,SPRN_SPRG_THREAD
106 stw r0,SAVED_KSP_LIMIT(r11)
107 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
113 .globl crit_transfer_to_handler
114 crit_transfer_to_handler:
120 stw r0,crit_srr0@l(0)
122 stw r0,crit_srr1@l(0)
124 /* set the stack limit to the current stack
125 * and set the limit to protect the thread_info
128 mfspr r8,SPRN_SPRG_THREAD
130 stw r0,saved_ksp_limit@l(0)
131 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
137 * This code finishes saving the registers to the exception frame
138 * and jumps to the appropriate handler for the exception, turning
139 * on address translation.
140 * Note that we rely on the caller having set cr0.eq iff the exception
141 * occurred in kernel mode (i.e. MSR:PR = 0).
143 .globl transfer_to_handler_full
144 transfer_to_handler_full:
148 .globl transfer_to_handler
158 mfspr r12,SPRN_SPRG_THREAD
160 tovirt(r2,r2) /* set r2 to current */
161 beq 2f /* if from user, fix up THREAD.regs */
162 addi r11,r1,STACK_FRAME_OVERHEAD
164 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
165 /* Check to see if the dbcr0 register is set up to debug. Use the
166 internal debug mode bit to do this. */
167 lwz r12,THREAD_DBCR0(r12)
168 andis. r12,r12,DBCR0_IDM@h
170 /* From user and task is ptraced - load up global dbcr0 */
171 li r12,-1 /* clear all pending debug events */
173 lis r11,global_dbcr0@ha
175 addi r11,r11,global_dbcr0@l
177 CURRENT_THREAD_INFO(r9, r1)
188 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
189 CURRENT_THREAD_INFO(r9, r1)
191 ACCOUNT_CPU_USER_ENTRY(r9, r11, r12)
196 2: /* if from kernel, check interrupted DOZE/NAP mode and
197 * check for stack overflow
199 lwz r9,KSP_LIMIT(r12)
200 cmplw r1,r9 /* if r1 <= ksp_limit */
201 ble- stack_ovf /* then the kernel stack overflowed */
203 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
204 CURRENT_THREAD_INFO(r9, r1)
205 tophys(r9,r9) /* check local flags */
206 lwz r12,TI_LOCAL_FLAGS(r9)
208 bt- 31-TLF_NAPPING,4f
209 bt- 31-TLF_SLEEPING,7f
210 #endif /* CONFIG_6xx || CONFIG_E500 */
211 .globl transfer_to_handler_cont
212 transfer_to_handler_cont:
215 lwz r11,0(r9) /* virtual address of handler */
216 lwz r9,4(r9) /* where to go when done */
217 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
220 #ifdef CONFIG_TRACE_IRQFLAGS
221 lis r12,reenable_mmu@h
222 ori r12,r12,reenable_mmu@l
227 reenable_mmu: /* re-enable mmu so we can */
231 andi. r10,r10,MSR_EE /* Did EE change? */
235 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
236 * If from user mode there is only one stack frame on the stack, and
237 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
238 * stack frame to make trace_hardirqs_off happy.
240 * This is handy because we also need to save a bunch of GPRs,
241 * r3 can be different from GPR3(r1) at this point, r9 and r11
242 * contains the old MSR and handler address respectively,
243 * r4 & r5 can contain page fault arguments that need to be passed
244 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
245 * they aren't useful past this point (aren't syscall arguments),
246 * the rest is restored from the exception frame.
254 bl trace_hardirqs_off
267 bctr /* jump to handler */
268 #else /* CONFIG_TRACE_IRQFLAGS */
273 RFI /* jump to handler, enable MMU */
274 #endif /* CONFIG_TRACE_IRQFLAGS */
276 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
277 4: rlwinm r12,r12,0,~_TLF_NAPPING
278 stw r12,TI_LOCAL_FLAGS(r9)
279 b power_save_ppc32_restore
281 7: rlwinm r12,r12,0,~_TLF_SLEEPING
282 stw r12,TI_LOCAL_FLAGS(r9)
283 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
284 rlwinm r9,r9,0,~MSR_EE
285 lwz r12,_LINK(r11) /* and return to address in LR */
286 b fast_exception_return
290 * On kernel stack overflow, load up an initial stack pointer
291 * and call StackOverflow(regs), which should not return.
294 /* sometimes we use a statically-allocated stack, which is OK. */
298 ble 5b /* r1 <= &_end is OK */
300 addi r3,r1,STACK_FRAME_OVERHEAD
301 lis r1,init_thread_union@ha
302 addi r1,r1,init_thread_union@l
303 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
304 lis r9,StackOverflow@ha
305 addi r9,r9,StackOverflow@l
306 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
307 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
316 * Handle a system call.
318 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
319 .stabs "entry_32.S",N_SO,0,0,0f
326 lwz r11,_CCR(r1) /* Clear SO bit in CR */
329 #ifdef CONFIG_TRACE_IRQFLAGS
330 /* Return from syscalls can (and generally will) hard enable
331 * interrupts. You aren't supposed to call a syscall with
332 * interrupts disabled in the first place. However, to ensure
333 * that we get it right vs. lockdep if it happens, we force
334 * that hard enable here with appropriate tracing if we see
335 * that we have been called with interrupts off
340 /* We came in with interrupts disabled, we enable them now */
353 #endif /* CONFIG_TRACE_IRQFLAGS */
354 CURRENT_THREAD_INFO(r10, r1)
355 lwz r11,TI_FLAGS(r10)
356 andi. r11,r11,_TIF_SYSCALL_DOTRACE
358 syscall_dotrace_cont:
359 cmplwi 0,r0,NR_syscalls
360 lis r10,sys_call_table@h
361 ori r10,r10,sys_call_table@l
367 * Prevent the load of the handler below (based on the user-passed
368 * system call number) being speculatively executed until the test
369 * against NR_syscalls and branch to .66f above has
373 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
375 addi r9,r1,STACK_FRAME_OVERHEAD
377 blrl /* Call handler */
378 .globl ret_from_syscall
380 #ifdef CONFIG_DEBUG_RSEQ
381 /* Check whether the syscall is issued inside a restartable sequence */
383 addi r3,r1,STACK_FRAME_OVERHEAD
388 CURRENT_THREAD_INFO(r12, r1)
389 /* disable interrupts so current_thread_info()->flags can't change */
390 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
391 /* Note: We don't bother telling lockdep about it */
396 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
397 bne- syscall_exit_work
399 blt+ syscall_exit_cont
400 lwz r11,_CCR(r1) /* Load CR */
402 oris r11,r11,0x1000 /* Set SO bit in CR */
406 #ifdef CONFIG_TRACE_IRQFLAGS
407 /* If we are going to return from the syscall with interrupts
408 * off, we trace that here. It shouldn't happen though but we
409 * want to catch the bugger if it does right ?
414 bl trace_hardirqs_off
417 #endif /* CONFIG_TRACE_IRQFLAGS */
418 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
419 /* If the process has its own DBCR0 value, load it up. The internal
420 debug mode bit tells us that dbcr0 should be loaded. */
421 lwz r0,THREAD+THREAD_DBCR0(r2)
422 andis. r10,r0,DBCR0_IDM@h
426 BEGIN_MMU_FTR_SECTION
427 lis r4,icache_44x_need_flush@ha
428 lwz r5,icache_44x_need_flush@l(r4)
432 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
433 #endif /* CONFIG_44x */
436 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
437 stwcx. r0,0,r1 /* to clear the reservation */
438 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
441 CURRENT_THREAD_INFO(r4, r1)
442 ACCOUNT_CPU_USER_EXIT(r4, r5, r7)
452 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
462 stw r7,icache_44x_need_flush@l(r4)
464 #endif /* CONFIG_44x */
476 .globl ret_from_kernel_thread
477 ret_from_kernel_thread:
487 /* Traced system call support */
492 addi r3,r1,STACK_FRAME_OVERHEAD
493 bl do_syscall_trace_enter
495 * Restore argument registers possibly just changed.
496 * We use the return value of do_syscall_trace_enter
497 * for call number to look up in the table (r0).
508 cmplwi r0,NR_syscalls
509 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
510 bge- ret_from_syscall
511 b syscall_dotrace_cont
514 andi. r0,r9,_TIF_RESTOREALL
520 andi. r0,r9,_TIF_NOERROR
522 lwz r11,_CCR(r1) /* Load CR */
524 oris r11,r11,0x1000 /* Set SO bit in CR */
527 1: stw r6,RESULT(r1) /* Save result */
528 stw r3,GPR3(r1) /* Update return value */
529 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
532 /* Clear per-syscall TIF flags if any are set. */
534 li r11,_TIF_PERSYSCALL_MASK
535 addi r12,r12,TI_FLAGS
538 #ifdef CONFIG_IBM405_ERR77
543 subi r12,r12,TI_FLAGS
545 4: /* Anything which requires enabling interrupts? */
546 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
549 /* Re-enable interrupts. There is no need to trace that with
550 * lockdep as we are supposed to have IRQs on at this point
556 /* Save NVGPRS if they're not saved already */
564 addi r3,r1,STACK_FRAME_OVERHEAD
565 bl do_syscall_trace_leave
566 b ret_from_except_full
569 * The fork/clone functions need to copy the full register set into
570 * the child process. Therefore we need to save all the nonvolatile
571 * registers (r13 - r31) before calling the C code.
577 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
578 stw r0,_TRAP(r1) /* register set saved */
585 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
586 stw r0,_TRAP(r1) /* register set saved */
593 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
594 stw r0,_TRAP(r1) /* register set saved */
597 .globl ppc_swapcontext
601 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
602 stw r0,_TRAP(r1) /* register set saved */
606 * Top-level page fault handling.
607 * This is in assembler because if do_page_fault tells us that
608 * it is a bad kernel page fault, we want to save the non-volatile
609 * registers before calling bad_page_fault.
611 .globl handle_page_fault
614 addi r3,r1,STACK_FRAME_OVERHEAD
616 andis. r0,r5,DSISR_DABRMATCH@h
617 bne- handle_dabr_fault
627 addi r3,r1,STACK_FRAME_OVERHEAD
630 b ret_from_except_full
633 /* We have a data breakpoint exception - handle it */
640 b ret_from_except_full
644 * This routine switches between two different tasks. The process
645 * state of one is saved on its kernel stack. Then the state
646 * of the other is restored from its kernel stack. The memory
647 * management hardware is updated to the second process's state.
648 * Finally, we can return to the second process.
649 * On entry, r3 points to the THREAD for the current task, r4
650 * points to the THREAD for the new task.
652 * This routine is always called with interrupts disabled.
654 * Note: there are two ways to get to the "going out" portion
655 * of this code; either by coming in via the entry (_switch)
656 * or via "fork" which must set up an environment equivalent
657 * to the "_switch" path. If you change this , you'll have to
658 * change the fork code also.
660 * The code which creates the new task context is in 'copy_thread'
661 * in arch/ppc/kernel/process.c
664 stwu r1,-INT_FRAME_SIZE(r1)
666 stw r0,INT_FRAME_SIZE+4(r1)
667 /* r3-r12 are caller saved -- Cort */
669 stw r0,_NIP(r1) /* Return to switch caller */
671 li r0,MSR_FP /* Disable floating-point */
672 #ifdef CONFIG_ALTIVEC
674 oris r0,r0,MSR_VEC@h /* Disable altivec */
675 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
676 stw r12,THREAD+THREAD_VRSAVE(r2)
677 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
678 #endif /* CONFIG_ALTIVEC */
681 oris r0,r0,MSR_SPE@h /* Disable SPE */
682 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
683 stw r12,THREAD+THREAD_SPEFSCR(r2)
684 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
685 #endif /* CONFIG_SPE */
686 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
694 stw r1,KSP(r3) /* Set old stack pointer */
697 /* We need a sync somewhere here to make sure that if the
698 * previous task gets rescheduled on another CPU, it sees all
699 * stores it has performed on this one.
702 #endif /* CONFIG_SMP */
705 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
706 lwz r1,KSP(r4) /* Load new stack pointer */
708 /* save the old current 'last' for return value */
710 addi r2,r4,-THREAD /* Update current */
712 #ifdef CONFIG_ALTIVEC
714 lwz r0,THREAD+THREAD_VRSAVE(r2)
715 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
716 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
717 #endif /* CONFIG_ALTIVEC */
720 lwz r0,THREAD+THREAD_SPEFSCR(r2)
721 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
722 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
723 #endif /* CONFIG_SPE */
727 /* r3-r12 are destroyed -- Cort */
730 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
732 addi r1,r1,INT_FRAME_SIZE
735 .globl fast_exception_return
736 fast_exception_return:
737 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
738 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
739 beq 1f /* if not, we've got problems */
742 2: REST_4GPRS(3, r11)
748 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
752 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
763 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
764 /* check if the exception happened in a restartable section */
765 1: lis r3,exc_exit_restart_end@ha
766 addi r3,r3,exc_exit_restart_end@l
769 lis r4,exc_exit_restart@ha
770 addi r4,r4,exc_exit_restart@l
773 lis r3,fee_restarts@ha
775 lwz r5,fee_restarts@l(r3)
777 stw r5,fee_restarts@l(r3)
778 mr r12,r4 /* restart at exc_exit_restart */
787 /* aargh, a nonrecoverable interrupt, panic */
788 /* aargh, we don't know which trap this is */
789 /* but the 601 doesn't implement the RI bit, so assume it's OK */
793 END_FTR_SECTION_IFSET(CPU_FTR_601)
796 addi r3,r1,STACK_FRAME_OVERHEAD
798 ori r10,r10,MSR_KERNEL@l
799 bl transfer_to_handler_full
800 .long nonrecoverable_exception
801 .long ret_from_except
804 .globl ret_from_except_full
805 ret_from_except_full:
809 .globl ret_from_except
811 /* Hard-disable interrupts so that current_thread_info()->flags
812 * can't change between when we test it and when we return
813 * from the interrupt. */
814 /* Note: We don't bother telling lockdep about it */
815 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
816 SYNC /* Some chip revs have problems here... */
817 MTMSRD(r10) /* disable interrupts */
819 lwz r3,_MSR(r1) /* Returning to user mode? */
823 user_exc_return: /* r10 contains MSR_KERNEL here */
824 /* Check current_thread_info()->flags */
825 CURRENT_THREAD_INFO(r9, r1)
827 andi. r0,r9,_TIF_USER_WORK_MASK
831 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
832 /* Check whether this process has its own DBCR0 value. The internal
833 debug mode bit tells us that dbcr0 should be loaded. */
834 lwz r0,THREAD+THREAD_DBCR0(r2)
835 andis. r10,r0,DBCR0_IDM@h
838 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
839 CURRENT_THREAD_INFO(r9, r1)
840 ACCOUNT_CPU_USER_EXIT(r9, r10, r11)
845 /* N.B. the only way to get here is from the beq following ret_from_except. */
847 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
848 CURRENT_THREAD_INFO(r9, r1)
850 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
853 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
856 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
857 mr r4,r1 /* src: current exception frame */
858 mr r1,r3 /* Reroute the trampoline frame to r1 */
860 /* Copy from the original to the trampoline. */
861 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
862 li r6,0 /* start offset: 0 */
869 /* Do real store operation to complete stwu */
873 /* Clear _TIF_EMULATE_STACK_STORE flag */
874 lis r11,_TIF_EMULATE_STACK_STORE@h
878 #ifdef CONFIG_IBM405_ERR77
885 #ifdef CONFIG_PREEMPT
886 /* check current_thread_info->preempt_count */
887 lwz r0,TI_PREEMPT(r9)
888 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
890 andi. r8,r8,_TIF_NEED_RESCHED
893 andi. r0,r3,MSR_EE /* interrupts off? */
894 beq restore /* don't schedule if so */
895 #ifdef CONFIG_TRACE_IRQFLAGS
896 /* Lockdep thinks irqs are enabled, we need to call
897 * preempt_schedule_irq with IRQs off, so we inform lockdep
898 * now that we -did- turn them off already
900 bl trace_hardirqs_off
902 1: bl preempt_schedule_irq
903 CURRENT_THREAD_INFO(r9, r1)
905 andi. r0,r3,_TIF_NEED_RESCHED
907 #ifdef CONFIG_TRACE_IRQFLAGS
908 /* And now, to properly rebalance the above, we tell lockdep they
909 * are being turned back on, which will happen when we return
913 #endif /* CONFIG_PREEMPT */
915 /* interrupts are hard-disabled at this point */
918 BEGIN_MMU_FTR_SECTION
920 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
921 lis r4,icache_44x_need_flush@ha
922 lwz r5,icache_44x_need_flush@l(r4)
927 stw r6,icache_44x_need_flush@l(r4)
929 #endif /* CONFIG_44x */
932 #ifdef CONFIG_TRACE_IRQFLAGS
933 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
934 * off in this assembly code while peeking at TI_FLAGS() and such. However
935 * we need to inform it if the exception turned interrupts off, and we
936 * are about to trun them back on.
938 * The problem here sadly is that we don't know whether the exceptions was
939 * one that turned interrupts off or not. So we always tell lockdep about
940 * turning them on here when we go back to wherever we came from with EE
941 * on, even if that may meen some redudant calls being tracked. Maybe later
942 * we could encode what the exception did somewhere or test the exception
943 * type in the pt_regs but that sounds overkill
948 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
949 * which is the stack frame here, we need to force a stack frame
950 * in case we came from user space.
961 #endif /* CONFIG_TRACE_IRQFLAGS */
976 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
977 stwcx. r0,0,r1 /* to clear the reservation */
979 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
980 andi. r10,r9,MSR_RI /* check if this exception occurred */
981 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
988 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
992 * Once we put values in SRR0 and SRR1, we are in a state
993 * where exceptions are not recoverable, since taking an
994 * exception will trash SRR0 and SRR1. Therefore we clear the
995 * MSR:RI bit to indicate this. If we do take an exception,
996 * we can't return to the point of the exception but we
997 * can restart the exception exit path at the label
998 * exc_exit_restart below. -- paulus
1000 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
1002 MTMSRD(r10) /* clear the RI bit */
1003 .globl exc_exit_restart
1006 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
1013 .globl exc_exit_restart_end
1014 exc_exit_restart_end:
1018 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1020 * This is a bit different on 4xx/Book-E because it doesn't have
1021 * the RI bit in the MSR.
1022 * The TLB miss handler checks if we have interrupted
1023 * the exception exit path and restarts it if so
1024 * (well maybe one day it will... :).
1030 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1034 .globl exc_exit_restart
1043 .globl exc_exit_restart_end
1044 exc_exit_restart_end:
1047 b . /* prevent prefetch past rfi */
1050 * Returning from a critical interrupt in user mode doesn't need
1051 * to be any different from a normal exception. For a critical
1052 * interrupt in the kernel, we just return (without checking for
1053 * preemption) since the interrupt may have happened at some crucial
1054 * place (e.g. inside the TLB miss handler), and because we will be
1055 * running with r1 pointing into critical_stack, not the current
1056 * process's kernel stack (and therefore current_thread_info() will
1057 * give the wrong answer).
1058 * We have to restore various SPRs that may have been in use at the
1059 * time of the critical interrupt.
1063 #define PPC_40x_TURN_OFF_MSR_DR \
1064 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1065 * assume the instructions here are mapped by a pinned TLB entry */ \
1071 #define PPC_40x_TURN_OFF_MSR_DR
1074 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1077 andi. r3,r3,MSR_PR; \
1078 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1079 bne user_exc_return; \
1082 REST_4GPRS(3, r1); \
1083 REST_2GPRS(7, r1); \
1086 mtspr SPRN_XER,r10; \
1088 PPC405_ERR77(0,r1); \
1089 stwcx. r0,0,r1; /* to clear the reservation */ \
1090 lwz r11,_LINK(r1); \
1094 PPC_40x_TURN_OFF_MSR_DR; \
1097 mtspr SPRN_DEAR,r9; \
1098 mtspr SPRN_ESR,r10; \
1101 mtspr exc_lvl_srr0,r11; \
1102 mtspr exc_lvl_srr1,r12; \
1104 lwz r12,GPR12(r1); \
1105 lwz r10,GPR10(r1); \
1106 lwz r11,GPR11(r1); \
1108 PPC405_ERR77_SYNC; \
1110 b .; /* prevent prefetch past exc_lvl_rfi */
1112 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1113 lwz r9,_##exc_lvl_srr0(r1); \
1114 lwz r10,_##exc_lvl_srr1(r1); \
1115 mtspr SPRN_##exc_lvl_srr0,r9; \
1116 mtspr SPRN_##exc_lvl_srr1,r10;
1118 #if defined(CONFIG_PPC_BOOK3E_MMU)
1119 #ifdef CONFIG_PHYS_64BIT
1120 #define RESTORE_MAS7 \
1122 mtspr SPRN_MAS7,r11;
1124 #define RESTORE_MAS7
1125 #endif /* CONFIG_PHYS_64BIT */
1126 #define RESTORE_MMU_REGS \
1130 mtspr SPRN_MAS0,r9; \
1132 mtspr SPRN_MAS1,r10; \
1134 mtspr SPRN_MAS2,r11; \
1135 mtspr SPRN_MAS3,r9; \
1136 mtspr SPRN_MAS6,r10; \
1138 #elif defined(CONFIG_44x)
1139 #define RESTORE_MMU_REGS \
1141 mtspr SPRN_MMUCR,r9;
1143 #define RESTORE_MMU_REGS
1147 .globl ret_from_crit_exc
1149 mfspr r9,SPRN_SPRG_THREAD
1150 lis r10,saved_ksp_limit@ha;
1151 lwz r10,saved_ksp_limit@l(r10);
1153 stw r10,KSP_LIMIT(r9)
1154 lis r9,crit_srr0@ha;
1155 lwz r9,crit_srr0@l(r9);
1156 lis r10,crit_srr1@ha;
1157 lwz r10,crit_srr1@l(r10);
1159 mtspr SPRN_SRR1,r10;
1160 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1161 #endif /* CONFIG_40x */
1164 .globl ret_from_crit_exc
1166 mfspr r9,SPRN_SPRG_THREAD
1167 lwz r10,SAVED_KSP_LIMIT(r1)
1168 stw r10,KSP_LIMIT(r9)
1169 RESTORE_xSRR(SRR0,SRR1);
1171 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1173 .globl ret_from_debug_exc
1175 mfspr r9,SPRN_SPRG_THREAD
1176 lwz r10,SAVED_KSP_LIMIT(r1)
1177 stw r10,KSP_LIMIT(r9)
1178 lwz r9,THREAD_INFO-THREAD(r9)
1179 CURRENT_THREAD_INFO(r10, r1)
1180 lwz r10,TI_PREEMPT(r10)
1181 stw r10,TI_PREEMPT(r9)
1182 RESTORE_xSRR(SRR0,SRR1);
1183 RESTORE_xSRR(CSRR0,CSRR1);
1185 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1187 .globl ret_from_mcheck_exc
1188 ret_from_mcheck_exc:
1189 mfspr r9,SPRN_SPRG_THREAD
1190 lwz r10,SAVED_KSP_LIMIT(r1)
1191 stw r10,KSP_LIMIT(r9)
1192 RESTORE_xSRR(SRR0,SRR1);
1193 RESTORE_xSRR(CSRR0,CSRR1);
1194 RESTORE_xSRR(DSRR0,DSRR1);
1196 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1197 #endif /* CONFIG_BOOKE */
1200 * Load the DBCR0 value for a task that is being ptraced,
1201 * having first saved away the global DBCR0. Note that r0
1202 * has the dbcr0 value to set upon entry to this.
1205 mfmsr r10 /* first disable debug exceptions */
1206 rlwinm r10,r10,0,~MSR_DE
1209 mfspr r10,SPRN_DBCR0
1210 lis r11,global_dbcr0@ha
1211 addi r11,r11,global_dbcr0@l
1213 CURRENT_THREAD_INFO(r9, r1)
1224 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1232 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1234 do_work: /* r10 contains MSR_KERNEL here */
1235 andi. r0,r9,_TIF_NEED_RESCHED
1238 do_resched: /* r10 contains MSR_KERNEL here */
1239 /* Note: We don't need to inform lockdep that we are enabling
1240 * interrupts here. As far as it knows, they are already enabled
1244 MTMSRD(r10) /* hard-enable interrupts */
1247 /* Note: And we don't tell it we are disabling them again
1248 * neither. Those disable/enable cycles used to peek at
1249 * TI_FLAGS aren't advertised.
1251 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1253 MTMSRD(r10) /* disable interrupts */
1254 CURRENT_THREAD_INFO(r9, r1)
1256 andi. r0,r9,_TIF_NEED_RESCHED
1258 andi. r0,r9,_TIF_USER_WORK_MASK
1260 do_user_signal: /* r10 contains MSR_KERNEL here */
1263 MTMSRD(r10) /* hard-enable interrupts */
1264 /* save r13-r31 in the exception frame, if not already done */
1271 2: addi r3,r1,STACK_FRAME_OVERHEAD
1278 * We come here when we are at the end of handling an exception
1279 * that occurred at a place where taking an exception will lose
1280 * state information, such as the contents of SRR0 and SRR1.
1283 lis r10,exc_exit_restart_end@ha
1284 addi r10,r10,exc_exit_restart_end@l
1287 lis r11,exc_exit_restart@ha
1288 addi r11,r11,exc_exit_restart@l
1291 lis r10,ee_restarts@ha
1292 lwz r12,ee_restarts@l(r10)
1294 stw r12,ee_restarts@l(r10)
1295 mr r12,r11 /* restart at exc_exit_restart */
1297 3: /* OK, we can't recover, kill this process */
1298 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1301 END_FTR_SECTION_IFSET(CPU_FTR_601)
1308 4: addi r3,r1,STACK_FRAME_OVERHEAD
1309 bl nonrecoverable_exception
1310 /* shouldn't return */
1320 * PROM code for specific machines follows. Put it
1321 * here so it's easy to add arch-specific sections later.
1324 #ifdef CONFIG_PPC_RTAS
1326 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1327 * called with the MMU off.
1330 stwu r1,-INT_FRAME_SIZE(r1)
1332 stw r0,INT_FRAME_SIZE+4(r1)
1333 LOAD_REG_ADDR(r4, rtas)
1334 lis r6,1f@ha /* physical return address for rtas */
1338 lwz r8,RTASENTRY(r4)
1342 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1343 SYNC /* disable interrupts so SRR0/1 */
1344 MTMSRD(r0) /* don't get trashed */
1345 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1347 mtspr SPRN_SPRG_RTAS,r7
1352 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1353 lwz r9,8(r9) /* original msr value */
1354 addi r1,r1,INT_FRAME_SIZE
1356 mtspr SPRN_SPRG_RTAS,r0
1359 RFI /* return to caller */
1361 .globl machine_check_in_rtas
1362 machine_check_in_rtas:
1364 /* XXX load up BATs and panic */
1366 #endif /* CONFIG_PPC_RTAS */