2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
39 #include <asm/traps.h>
40 #include <asm/thread_info.h>
42 #include <linux/linkage.h>
50 .import pa_tlb_lock,data
51 .macro load_pa_tlb_lock reg
52 #if __PA_LDCW_ALIGNMENT > 4
53 load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
54 depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
56 load32 PA(pa_tlb_lock), \reg
60 /* space_to_prot macro creates a prot id from a space id */
62 #if (SPACEID_SHIFT) == 0
63 .macro space_to_prot spc prot
64 depd,z \spc,62,31,\prot
67 .macro space_to_prot spc prot
68 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
72 /* Switch to virtual mapping, trashing only %r1 */
75 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
80 load32 KERNEL_PSW, %r1
82 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
83 mtctl %r0, %cr17 /* Clear IIASQ tail */
84 mtctl %r0, %cr17 /* Clear IIASQ head */
87 mtctl %r1, %cr18 /* Set IIAOQ tail */
89 mtctl %r1, %cr18 /* Set IIAOQ head */
96 * The "get_stack" macros are responsible for determining the
100 * Already using a kernel stack, so call the
101 * get_stack_use_r30 macro to push a pt_regs structure
102 * on the stack, and store registers there.
104 * Need to set up a kernel stack, so call the
105 * get_stack_use_cr30 macro to set up a pointer
106 * to the pt_regs structure contained within the
107 * task pointer pointed to by cr30. Set the stack
108 * pointer to point to the end of the task structure.
110 * Note that we use shadowed registers for temps until
111 * we can save %r26 and %r29. %r26 is used to preserve
112 * %r8 (a shadowed register) which temporarily contained
113 * either the fault type ("code") or the eirr. We need
114 * to use a non-shadowed register to carry the value over
115 * the rfir in virt_map. We use %r26 since this value winds
116 * up being passed as the argument to either do_cpu_irq_mask
117 * or handle_interruption. %r29 is used to hold a pointer
118 * the register save area, and once again, it needs to
119 * be a non-shadowed register so that it survives the rfir.
121 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
124 .macro get_stack_use_cr30
126 /* we save the registers in the task struct */
130 ldo THREAD_SZ_ALGN(%r1), %r30
134 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
136 ldo TASK_REGS(%r9),%r9
137 STREG %r17,PT_GR30(%r9)
138 STREG %r29,PT_GR29(%r9)
139 STREG %r26,PT_GR26(%r9)
140 STREG %r16,PT_SR7(%r9)
144 .macro get_stack_use_r30
146 /* we put a struct pt_regs on the stack and save the registers there */
150 ldo PT_SZ_ALGN(%r30),%r30
151 STREG %r1,PT_GR30(%r9)
152 STREG %r29,PT_GR29(%r9)
153 STREG %r26,PT_GR26(%r9)
154 STREG %r16,PT_SR7(%r9)
159 LDREG PT_GR1(%r29), %r1
160 LDREG PT_GR30(%r29),%r30
161 LDREG PT_GR29(%r29),%r29
164 /* default interruption handler
165 * (calls traps.c:handle_interruption) */
172 /* Interrupt interruption handler
173 * (calls irq.c:do_cpu_irq_mask) */
180 .import os_hpmc, code
184 nop /* must be a NOP, will be patched later */
185 load32 PA(os_hpmc), %r3
188 .word 0 /* checksum (will be patched) */
189 .word 0 /* address of handler */
190 .word 0 /* length of handler */
194 * Performance Note: Instructions will be moved up into
195 * this part of the code later on, once we are sure
196 * that the tlb miss handlers are close to final form.
199 /* Register definitions for tlb miss handler macros */
201 va = r8 /* virtual address for which the trap occurred */
202 spc = r24 /* space for which the trap occurred */
207 * itlb miss interruption handler (parisc 1.1 - 32 bit)
221 * itlb miss interruption handler (parisc 2.0)
238 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
241 .macro naitlb_11 code
252 * naitlb miss interruption handler (parisc 2.0)
255 .macro naitlb_20 code
270 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
284 * dtlb miss interruption handler (parisc 2.0)
301 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
303 .macro nadtlb_11 code
313 /* nadtlb miss interruption handler (parisc 2.0) */
315 .macro nadtlb_20 code
330 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
344 * dirty bit trap interruption handler (parisc 2.0)
360 /* In LP64, the space contains part of the upper 32 bits of the
361 * fault. We have to extract this and place it in the va,
362 * zeroing the corresponding bits in the space register */
363 .macro space_adjust spc,va,tmp
365 extrd,u \spc,63,SPACEID_SHIFT,\tmp
366 depd %r0,63,SPACEID_SHIFT,\spc
367 depd \tmp,31,SPACEID_SHIFT,\va
371 .import swapper_pg_dir,code
373 /* Get the pgd. For faults on space zero (kernel space), this
374 * is simply swapper_pg_dir. For user space faults, the
375 * pgd is stored in %cr25 */
376 .macro get_pgd spc,reg
377 ldil L%PA(swapper_pg_dir),\reg
378 ldo R%PA(swapper_pg_dir)(\reg),\reg
379 or,COND(=) %r0,\spc,%r0
384 space_check(spc,tmp,fault)
386 spc - The space we saw the fault with.
387 tmp - The place to store the current space.
388 fault - Function to call on failure.
390 Only allow faults on different spaces from the
391 currently active one if we're the kernel
394 .macro space_check spc,tmp,fault
396 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
397 * as kernel, so defeat the space
400 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
401 cmpb,COND(<>),n \tmp,\spc,\fault
404 /* Look up a PTE in a 2-Level scheme (faulting at each
405 * level if the entry isn't present
407 * NOTE: we use ldw even for LP64, since the short pointers
408 * can address up to 1TB
410 .macro L2_ptep pmd,pte,index,va,fault
411 #if CONFIG_PGTABLE_LEVELS == 3
412 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
414 # if defined(CONFIG_64BIT)
415 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
417 # if PAGE_SIZE > 4096
418 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
420 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
424 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
426 ldw,s \index(\pmd),\pmd
427 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
428 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
430 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
431 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
432 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
433 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
435 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
438 /* Look up PTE in a 3-Level scheme.
440 * Here we implement a Hybrid L2/L3 scheme: we allocate the
441 * first pmd adjacent to the pgd. This means that we can
442 * subtract a constant offset to get to it. The pmd and pgd
443 * sizes are arranged so that a single pmd covers 4GB (giving
444 * a full LP64 process access to 8TB) so our lookups are
445 * effectively L2 for the first 4GB of the kernel (i.e. for
446 * all ILP32 processes and all the kernel for machines with
447 * under 4GB of memory) */
448 .macro L3_ptep pgd,pte,index,va,fault
449 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
450 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
452 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
453 ldw,s \index(\pgd),\pgd
454 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
455 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
456 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
457 shld \pgd,PxD_VALUE_SHIFT,\index
458 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
460 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
461 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
463 L2_ptep \pgd,\pte,\index,\va,\fault
466 /* Acquire pa_tlb_lock lock and recheck page is still present. */
467 .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
469 cmpib,COND(=),n 0,\spc,2f
470 load_pa_tlb_lock \tmp
471 1: LDCW 0(\tmp),\tmp1
472 cmpib,COND(=) 0,\tmp1,1b
475 bb,<,n \pte,_PAGE_PRESENT_BIT,2f
482 /* Release pa_tlb_lock lock without reloading lock address. */
483 .macro tlb_unlock0 spc,tmp
485 or,COND(=) %r0,\spc,%r0
487 or,COND(=) %r0,\spc,%r0
492 /* Release pa_tlb_lock lock. */
493 .macro tlb_unlock1 spc,tmp
495 load_pa_tlb_lock \tmp
496 tlb_unlock0 \spc,\tmp
500 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
501 * don't needlessly dirty the cache line if it was already set */
502 .macro update_accessed ptp,pte,tmp,tmp1
503 ldi _PAGE_ACCESSED,\tmp1
505 and,COND(<>) \tmp1,\pte,%r0
509 /* Set the dirty bit (and accessed bit). No need to be
510 * clever, this is only used from the dirty fault */
511 .macro update_dirty ptp,pte,tmp
512 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
517 /* We have (depending on the page size):
518 * - 38 to 52-bit Physical Page Number
519 * - 12 to 26-bit page offset
521 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
522 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
523 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
524 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
526 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
527 .macro convert_for_tlb_insert20 pte,tmp
528 #ifdef CONFIG_HUGETLB_PAGE
530 extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
531 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
533 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
534 (63-58)+PAGE_ADD_SHIFT,\pte
535 extrd,u,*= \tmp,_PAGE_HPAGE_BIT+32,1,%r0
536 depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
537 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
538 #else /* Huge pages disabled */
539 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
540 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
541 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
542 (63-58)+PAGE_ADD_SHIFT,\pte
546 /* Convert the pte and prot to tlb insertion values. How
547 * this happens is quite subtle, read below */
548 .macro make_insert_tlb spc,pte,prot,tmp
549 space_to_prot \spc \prot /* create prot id from space */
550 /* The following is the real subtlety. This is depositing
551 * T <-> _PAGE_REFTRAP
553 * B <-> _PAGE_DMB (memory break)
555 * Then incredible subtlety: The access rights are
556 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
557 * See 3-14 of the parisc 2.0 manual
559 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
560 * trigger an access rights trap in user space if the user
561 * tries to read an unreadable page */
564 /* PAGE_USER indicates the page can be read with user privileges,
565 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
566 * contains _PAGE_READ) */
567 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
569 /* If we're a gateway page, drop PL2 back to zero for promotion
570 * to kernel privilege (so we can execute the page as kernel).
571 * Any privilege promotion page always denys read and write */
572 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
573 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
575 /* Enforce uncacheable pages.
576 * This should ONLY be use for MMIO on PA 2.0 machines.
577 * Memory/DMA is cache coherent on all PA2.0 machines we support
578 * (that means T-class is NOT supported) and the memory controllers
579 * on most of those machines only handles cache transactions.
581 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
584 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
585 convert_for_tlb_insert20 \pte \tmp
588 /* Identical macro to make_insert_tlb above, except it
589 * makes the tlb entry for the differently formatted pa11
590 * insertion instructions */
591 .macro make_insert_tlb_11 spc,pte,prot
592 zdep \spc,30,15,\prot
594 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
596 extru,= \pte,_PAGE_USER_BIT,1,%r0
597 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
598 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
599 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
601 /* Get rid of prot bits and convert to page addr for iitlba */
603 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
604 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
607 /* This is for ILP32 PA2.0 only. The TLB insertion needs
608 * to extend into I/O space if the address is 0xfXXXXXXX
609 * so we extend the f's into the top word of the pte in
611 .macro f_extend pte,tmp
612 extrd,s \pte,42,4,\tmp
614 extrd,s \pte,63,25,\pte
617 /* The alias region is an 8MB aligned 16MB to do clear and
618 * copy user pages at addresses congruent with the user
621 * To use the alias page, you set %r26 up with the to TLB
622 * entry (identifying the physical page) and %r23 up with
623 * the from tlb entry (or nothing if only a to entry---for
624 * clear_user_page_asm) */
625 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
626 cmpib,COND(<>),n 0,\spc,\fault
627 ldil L%(TMPALIAS_MAP_START),\tmp
628 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
629 /* on LP64, ldi will sign extend into the upper 32 bits,
630 * which is behaviour we don't want */
635 cmpb,COND(<>),n \tmp,\tmp1,\fault
636 mfctl %cr19,\tmp /* iir */
637 /* get the opcode (first six bits) into \tmp */
638 extrw,u \tmp,5,6,\tmp
640 * Only setting the T bit prevents data cache movein
641 * Setting access rights to zero prevents instruction cache movein
643 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
644 * to type field and _PAGE_READ goes to top bit of PL1
646 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
648 * so if the opcode is one (i.e. this is a memory management
649 * instruction) nullify the next load so \prot is only T.
650 * Otherwise this is a normal data operation
652 cmpiclr,= 0x01,\tmp,%r0
653 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
655 depd,z \prot,8,7,\prot
658 depw,z \prot,8,7,\prot
660 .error "undefined PA type to do_alias"
664 * OK, it is in the temp alias region, check whether "from" or "to".
665 * Check "subtle" note in pacache.S re: r23/r26.
668 extrd,u,*= \va,41,1,%r0
670 extrw,u,= \va,9,1,%r0
672 or,COND(tr) %r23,%r0,\pte
678 * Fault_vectors are architecturally required to be aligned on a 2K
685 ENTRY(fault_vector_20)
686 /* First vector is invalid (0) */
687 .ascii "cows can fly"
696 itlb_20 PARISC_ITLB_TRAP
728 ENTRY(fault_vector_11)
729 /* First vector is invalid (0) */
730 .ascii "cows can fly"
739 itlb_11 PARISC_ITLB_TRAP
768 /* Fault vector is separately protected and *must* be on its own page */
771 .import handle_interruption,code
772 .import do_cpu_irq_mask,code
777 * copy_thread moved args into task save area.
780 ENTRY(ret_from_kernel_thread)
781 /* Call schedule_tail first though */
782 BL schedule_tail, %r2
785 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
786 LDREG TASK_PT_GR25(%r1), %r26
788 LDREG TASK_PT_GR27(%r1), %r27
790 LDREG TASK_PT_GR26(%r1), %r1
793 b finish_child_return
795 END(ret_from_kernel_thread)
799 * struct task_struct *_switch_to(struct task_struct *prev,
800 * struct task_struct *next)
802 * switch kernel stacks and return prev */
803 ENTRY_CFI(_switch_to)
804 STREG %r2, -RP_OFFSET(%r30)
809 load32 _switch_to_ret, %r2
811 STREG %r2, TASK_PT_KPC(%r26)
812 LDREG TASK_PT_KPC(%r25), %r2
814 STREG %r30, TASK_PT_KSP(%r26)
815 LDREG TASK_PT_KSP(%r25), %r30
816 LDREG TASK_THREAD_INFO(%r25), %r25
820 ENTRY(_switch_to_ret)
821 mtctl %r0, %cr0 /* Needed for single stepping */
825 LDREG -RP_OFFSET(%r30), %r2
828 ENDPROC_CFI(_switch_to)
831 * Common rfi return path for interruptions, kernel execve, and
832 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
833 * return via this path if the signal was received when the process
834 * was running; if the process was blocked on a syscall then the
835 * normal syscall_exit path is used. All syscalls for traced
836 * proceses exit via intr_restore.
838 * XXX If any syscalls that change a processes space id ever exit
839 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
846 ENTRY_CFI(syscall_exit_rfi)
848 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
849 ldo TASK_REGS(%r16),%r16
850 /* Force iaoq to userspace, as the user has had access to our current
851 * context via sigcontext. Also Filter the PSW for the same reason.
853 LDREG PT_IAOQ0(%r16),%r19
855 STREG %r19,PT_IAOQ0(%r16)
856 LDREG PT_IAOQ1(%r16),%r19
858 STREG %r19,PT_IAOQ1(%r16)
859 LDREG PT_PSW(%r16),%r19
860 load32 USER_PSW_MASK,%r1
862 load32 USER_PSW_HI_MASK,%r20
865 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
867 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
868 STREG %r19,PT_PSW(%r16)
871 * If we aren't being traced, we never saved space registers
872 * (we don't store them in the sigcontext), so set them
873 * to "proper" values now (otherwise we'll wind up restoring
874 * whatever was last stored in the task structure, which might
875 * be inconsistent if an interrupt occurred while on the gateway
876 * page). Note that we may be "trashing" values the user put in
877 * them, but we don't support the user changing them.
880 STREG %r0,PT_SR2(%r16)
882 STREG %r19,PT_SR0(%r16)
883 STREG %r19,PT_SR1(%r16)
884 STREG %r19,PT_SR3(%r16)
885 STREG %r19,PT_SR4(%r16)
886 STREG %r19,PT_SR5(%r16)
887 STREG %r19,PT_SR6(%r16)
888 STREG %r19,PT_SR7(%r16)
891 /* check for reschedule */
893 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
894 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
896 .import do_notify_resume,code
900 LDREG TI_FLAGS(%r1),%r19
901 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
902 and,COND(<>) %r19, %r20, %r0
903 b,n intr_restore /* skip past if we've nothing to do */
905 /* This check is critical to having LWS
906 * working. The IASQ is zero on the gateway
907 * page and we cannot deliver any signals until
908 * we get off the gateway page.
910 * Only do signals if we are returning to user space
912 LDREG PT_IASQ0(%r16), %r20
913 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
914 LDREG PT_IASQ1(%r16), %r20
915 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
917 /* NOTE: We need to enable interrupts if we have to deliver
918 * signals. We used to do this earlier but it caused kernel
919 * stack overflows. */
922 copy %r0, %r25 /* long in_syscall = 0 */
924 ldo -16(%r30),%r29 /* Reference param save area */
927 BL do_notify_resume,%r2
928 copy %r16, %r26 /* struct pt_regs *regs */
934 ldo PT_FR31(%r29),%r1
938 /* inverse of virt_map */
940 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
943 /* Restore space id's and special cr's from PT_REGS
944 * structure pointed to by r29
948 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
949 * It also restores r1 and r30.
956 #ifndef CONFIG_PREEMPT
957 # define intr_do_preempt intr_restore
958 #endif /* !CONFIG_PREEMPT */
960 .import schedule,code
962 /* Only call schedule on return to userspace. If we're returning
963 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
964 * we jump back to intr_restore.
966 LDREG PT_IASQ0(%r16), %r20
967 cmpib,COND(=) 0, %r20, intr_do_preempt
969 LDREG PT_IASQ1(%r16), %r20
970 cmpib,COND(=) 0, %r20, intr_do_preempt
973 /* NOTE: We need to enable interrupts if we schedule. We used
974 * to do this earlier but it caused kernel stack overflows. */
978 ldo -16(%r30),%r29 /* Reference param save area */
981 ldil L%intr_check_sig, %r2
985 load32 schedule, %r20
988 ldo R%intr_check_sig(%r2), %r2
990 /* preempt the current task on returning to kernel
991 * mode from an interrupt, iff need_resched is set,
992 * and preempt_count is 0. otherwise, we continue on
993 * our merry way back to the current running task.
995 #ifdef CONFIG_PREEMPT
996 .import preempt_schedule_irq,code
998 rsm PSW_SM_I, %r0 /* disable interrupts */
1000 /* current_thread_info()->preempt_count */
1002 LDREG TI_PRE_COUNT(%r1), %r19
1003 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1004 nop /* prev insn branched backwards */
1006 /* check if we interrupted a critical path */
1007 LDREG PT_PSW(%r16), %r20
1008 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1011 BL preempt_schedule_irq, %r2
1014 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1015 #endif /* CONFIG_PREEMPT */
1018 * External interrupts.
1022 cmpib,COND(=),n 0,%r16,1f
1034 ldo PT_FR0(%r29), %r24
1039 copy %r29, %r26 /* arg0 is pt_regs */
1040 copy %r29, %r16 /* save pt_regs */
1042 ldil L%intr_return, %r2
1045 ldo -16(%r30),%r29 /* Reference param save area */
1049 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1050 ENDPROC_CFI(syscall_exit_rfi)
1053 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1055 ENTRY_CFI(intr_save) /* for os_hpmc */
1057 cmpib,COND(=),n 0,%r16,1f
1069 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1070 cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
1074 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1080 * If the interrupted code was running with W bit off (32 bit),
1081 * clear the b bits (bits 0 & 1) in the ior.
1082 * save_specials left ipsw value in r8 for us to test.
1084 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1087 /* adjust isr/ior: get high bits from isr and deposit in ior */
1088 space_adjust %r16,%r17,%r1
1090 STREG %r16, PT_ISR(%r29)
1091 STREG %r17, PT_IOR(%r29)
1093 #if 0 && defined(CONFIG_64BIT)
1094 /* Revisit when we have 64-bit code above 4Gb */
1098 /* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
1099 * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
1102 extrd,u,* %r8,PSW_W_BIT,1,%r1
1103 cmpib,COND(=),n 1,%r1,intr_save2
1104 LDREG PT_IASQ0(%r29), %r16
1105 LDREG PT_IAOQ0(%r29), %r17
1106 /* adjust iasq/iaoq */
1107 space_adjust %r16,%r17,%r1
1108 STREG %r16, PT_IASQ0(%r29)
1109 STREG %r17, PT_IAOQ0(%r29)
1118 ldo PT_FR0(%r29), %r25
1123 copy %r29, %r25 /* arg1 is pt_regs */
1125 ldo -16(%r30),%r29 /* Reference param save area */
1128 ldil L%intr_check_sig, %r2
1129 copy %r25, %r16 /* save pt_regs */
1131 b handle_interruption
1132 ldo R%intr_check_sig(%r2), %r2
1133 ENDPROC_CFI(intr_save)
1137 * Note for all tlb miss handlers:
1139 * cr24 contains a pointer to the kernel address space
1142 * cr25 contains a pointer to the current user address
1143 * space page directory.
1145 * sr3 will contain the space id of the user address space
1146 * of the current running thread while that thread is
1147 * running in the kernel.
1151 * register number allocations. Note that these are all
1152 * in the shadowed registers
1155 t0 = r1 /* temporary register 0 */
1156 va = r8 /* virtual address for which the trap occurred */
1157 t1 = r9 /* temporary register 1 */
1158 pte = r16 /* pte/phys page # */
1159 prot = r17 /* prot bits */
1160 spc = r24 /* space for which the trap occurred */
1161 ptp = r25 /* page directory/page table pointer */
1166 space_adjust spc,va,t0
1168 space_check spc,t0,dtlb_fault
1170 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1172 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
1173 update_accessed ptp,pte,t0,t1
1175 make_insert_tlb spc,pte,prot,t1
1183 dtlb_check_alias_20w:
1184 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1192 space_adjust spc,va,t0
1194 space_check spc,t0,nadtlb_fault
1196 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1198 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
1199 update_accessed ptp,pte,t0,t1
1201 make_insert_tlb spc,pte,prot,t1
1209 nadtlb_check_alias_20w:
1210 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1222 space_check spc,t0,dtlb_fault
1224 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1226 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
1227 update_accessed ptp,pte,t0,t1
1229 make_insert_tlb_11 spc,pte,prot
1231 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1234 idtlba pte,(%sr1,va)
1235 idtlbp prot,(%sr1,va)
1237 mtsp t1, %sr1 /* Restore sr1 */
1243 dtlb_check_alias_11:
1244 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1255 space_check spc,t0,nadtlb_fault
1257 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1259 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
1260 update_accessed ptp,pte,t0,t1
1262 make_insert_tlb_11 spc,pte,prot
1264 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1267 idtlba pte,(%sr1,va)
1268 idtlbp prot,(%sr1,va)
1270 mtsp t1, %sr1 /* Restore sr1 */
1276 nadtlb_check_alias_11:
1277 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1286 space_adjust spc,va,t0
1288 space_check spc,t0,dtlb_fault
1290 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1292 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
1293 update_accessed ptp,pte,t0,t1
1295 make_insert_tlb spc,pte,prot,t1
1305 dtlb_check_alias_20:
1306 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1316 space_check spc,t0,nadtlb_fault
1318 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1320 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
1321 update_accessed ptp,pte,t0,t1
1323 make_insert_tlb spc,pte,prot,t1
1333 nadtlb_check_alias_20:
1334 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1346 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1347 * probei instructions. We don't want to fault for these
1348 * instructions (not only does it not make sense, it can cause
1349 * deadlocks, since some flushes are done with the mmap
1350 * semaphore held). If the translation doesn't exist, we can't
1351 * insert a translation, so have to emulate the side effects
1352 * of the instruction. Since we don't insert a translation
1353 * we can get a lot of faults during a flush loop, so it makes
1354 * sense to try to do it here with minimum overhead. We only
1355 * emulate fdc,fic,pdc,probew,prober instructions whose base
1356 * and index registers are not shadowed. We defer everything
1357 * else to the "slow" path.
1360 mfctl %cr19,%r9 /* Get iir */
1362 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1363 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1365 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1368 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1369 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1370 BL get_register,%r25
1371 extrw,u %r9,15,5,%r8 /* Get index register # */
1372 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1374 BL get_register,%r25
1375 extrw,u %r9,10,5,%r8 /* Get base register # */
1376 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1377 BL set_register,%r25
1378 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1383 or %r8,%r9,%r8 /* Set PSW_N */
1390 When there is no translation for the probe address then we
1391 must nullify the insn and return zero in the target register.
1392 This will indicate to the calling code that it does not have
1393 write/read privileges to this address.
1395 This should technically work for prober and probew in PA 1.1,
1396 and also probe,r and probe,w in PA 2.0
1398 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1399 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1405 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1406 BL get_register,%r25 /* Find the target register */
1407 extrw,u %r9,31,5,%r8 /* Get target register */
1408 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1409 BL set_register,%r25
1410 copy %r0,%r1 /* Write zero to target register */
1411 b nadtlb_nullify /* Nullify return insn */
1419 * I miss is a little different, since we allow users to fault
1420 * on the gateway page which is in the kernel address space.
1423 space_adjust spc,va,t0
1425 space_check spc,t0,itlb_fault
1427 L3_ptep ptp,pte,t0,va,itlb_fault
1429 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1430 update_accessed ptp,pte,t0,t1
1432 make_insert_tlb spc,pte,prot,t1
1443 * I miss is a little different, since we allow users to fault
1444 * on the gateway page which is in the kernel address space.
1447 space_adjust spc,va,t0
1449 space_check spc,t0,naitlb_fault
1451 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1453 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
1454 update_accessed ptp,pte,t0,t1
1456 make_insert_tlb spc,pte,prot,t1
1464 naitlb_check_alias_20w:
1465 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1477 space_check spc,t0,itlb_fault
1479 L2_ptep ptp,pte,t0,va,itlb_fault
1481 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1482 update_accessed ptp,pte,t0,t1
1484 make_insert_tlb_11 spc,pte,prot
1486 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1489 iitlba pte,(%sr1,va)
1490 iitlbp prot,(%sr1,va)
1492 mtsp t1, %sr1 /* Restore sr1 */
1501 space_check spc,t0,naitlb_fault
1503 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1505 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
1506 update_accessed ptp,pte,t0,t1
1508 make_insert_tlb_11 spc,pte,prot
1510 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1513 iitlba pte,(%sr1,va)
1514 iitlbp prot,(%sr1,va)
1516 mtsp t1, %sr1 /* Restore sr1 */
1522 naitlb_check_alias_11:
1523 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1525 iitlba pte,(%sr0, va)
1526 iitlbp prot,(%sr0, va)
1535 space_check spc,t0,itlb_fault
1537 L2_ptep ptp,pte,t0,va,itlb_fault
1539 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1540 update_accessed ptp,pte,t0,t1
1542 make_insert_tlb spc,pte,prot,t1
1555 space_check spc,t0,naitlb_fault
1557 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1559 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
1560 update_accessed ptp,pte,t0,t1
1562 make_insert_tlb spc,pte,prot,t1
1572 naitlb_check_alias_20:
1573 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1585 space_adjust spc,va,t0
1587 space_check spc,t0,dbit_fault
1589 L3_ptep ptp,pte,t0,va,dbit_fault
1591 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1592 update_dirty ptp,pte,t1
1594 make_insert_tlb spc,pte,prot,t1
1607 space_check spc,t0,dbit_fault
1609 L2_ptep ptp,pte,t0,va,dbit_fault
1611 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1612 update_dirty ptp,pte,t1
1614 make_insert_tlb_11 spc,pte,prot
1616 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1619 idtlba pte,(%sr1,va)
1620 idtlbp prot,(%sr1,va)
1622 mtsp t1, %sr1 /* Restore sr1 */
1631 space_check spc,t0,dbit_fault
1633 L2_ptep ptp,pte,t0,va,dbit_fault
1635 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1636 update_dirty ptp,pte,t1
1638 make_insert_tlb spc,pte,prot,t1
1649 .import handle_interruption,code
1653 ldi 31,%r8 /* Use an unused code */
1675 /* Register saving semantics for system calls:
1677 %r1 clobbered by system call macro in userspace
1678 %r2 saved in PT_REGS by gateway page
1679 %r3 - %r18 preserved by C code (saved by signal code)
1680 %r19 - %r20 saved in PT_REGS by gateway page
1681 %r21 - %r22 non-standard syscall args
1682 stored in kernel stack by gateway page
1683 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1684 %r27 - %r30 saved in PT_REGS by gateway page
1685 %r31 syscall return pointer
1688 /* Floating point registers (FIXME: what do we do with these?)
1690 %fr0 - %fr3 status/exception, not preserved
1691 %fr4 - %fr7 arguments
1692 %fr8 - %fr11 not preserved by C code
1693 %fr12 - %fr21 preserved by C code
1694 %fr22 - %fr31 not preserved by C code
1697 .macro reg_save regs
1698 STREG %r3, PT_GR3(\regs)
1699 STREG %r4, PT_GR4(\regs)
1700 STREG %r5, PT_GR5(\regs)
1701 STREG %r6, PT_GR6(\regs)
1702 STREG %r7, PT_GR7(\regs)
1703 STREG %r8, PT_GR8(\regs)
1704 STREG %r9, PT_GR9(\regs)
1705 STREG %r10,PT_GR10(\regs)
1706 STREG %r11,PT_GR11(\regs)
1707 STREG %r12,PT_GR12(\regs)
1708 STREG %r13,PT_GR13(\regs)
1709 STREG %r14,PT_GR14(\regs)
1710 STREG %r15,PT_GR15(\regs)
1711 STREG %r16,PT_GR16(\regs)
1712 STREG %r17,PT_GR17(\regs)
1713 STREG %r18,PT_GR18(\regs)
1716 .macro reg_restore regs
1717 LDREG PT_GR3(\regs), %r3
1718 LDREG PT_GR4(\regs), %r4
1719 LDREG PT_GR5(\regs), %r5
1720 LDREG PT_GR6(\regs), %r6
1721 LDREG PT_GR7(\regs), %r7
1722 LDREG PT_GR8(\regs), %r8
1723 LDREG PT_GR9(\regs), %r9
1724 LDREG PT_GR10(\regs),%r10
1725 LDREG PT_GR11(\regs),%r11
1726 LDREG PT_GR12(\regs),%r12
1727 LDREG PT_GR13(\regs),%r13
1728 LDREG PT_GR14(\regs),%r14
1729 LDREG PT_GR15(\regs),%r15
1730 LDREG PT_GR16(\regs),%r16
1731 LDREG PT_GR17(\regs),%r17
1732 LDREG PT_GR18(\regs),%r18
1735 .macro fork_like name
1736 ENTRY_CFI(sys_\name\()_wrapper)
1737 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1738 ldo TASK_REGS(%r1),%r1
1741 ldil L%sys_\name, %r31
1742 be R%sys_\name(%sr4,%r31)
1743 STREG %r28, PT_CR27(%r1)
1744 ENDPROC_CFI(sys_\name\()_wrapper)
1751 /* Set the return value for the child */
1753 BL schedule_tail, %r2
1755 finish_child_return:
1756 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1757 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1759 LDREG PT_CR27(%r1), %r3
1766 ENTRY_CFI(sys_rt_sigreturn_wrapper)
1767 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1768 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1769 /* Don't save regs, we are going to restore them from sigcontext. */
1770 STREG %r2, -RP_OFFSET(%r30)
1772 ldo FRAME_SIZE(%r30), %r30
1773 BL sys_rt_sigreturn,%r2
1774 ldo -16(%r30),%r29 /* Reference param save area */
1776 BL sys_rt_sigreturn,%r2
1777 ldo FRAME_SIZE(%r30), %r30
1780 ldo -FRAME_SIZE(%r30), %r30
1781 LDREG -RP_OFFSET(%r30), %r2
1783 /* FIXME: I think we need to restore a few more things here. */
1784 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1785 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1788 /* If the signal was received while the process was blocked on a
1789 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1790 * take us to syscall_exit_rfi and on to intr_return.
1793 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1794 ENDPROC_CFI(sys_rt_sigreturn_wrapper)
1797 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1798 * via syscall_exit_rfi if the signal was received while the process
1802 /* save return value now */
1805 LDREG TI_TASK(%r1),%r1
1806 STREG %r28,TASK_PT_GR28(%r1)
1808 /* Seems to me that dp could be wrong here, if the syscall involved
1809 * calling a module, and nothing got round to restoring dp on return.
1813 syscall_check_resched:
1815 /* check for reschedule */
1817 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1818 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1820 .import do_signal,code
1822 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1823 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1824 and,COND(<>) %r19, %r26, %r0
1825 b,n syscall_restore /* skip past if we've nothing to do */
1828 /* Save callee-save registers (for sigcontext).
1829 * FIXME: After this point the process structure should be
1830 * consistent with all the relevant state of the process
1831 * before the syscall. We need to verify this.
1833 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1834 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1838 ldo -16(%r30),%r29 /* Reference param save area */
1841 BL do_notify_resume,%r2
1842 ldi 1, %r25 /* long in_syscall = 1 */
1844 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1845 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1848 b,n syscall_check_sig
1851 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1853 /* Are we being ptraced? */
1854 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1855 ldi _TIF_SINGLESTEP|_TIF_BLOCKSTEP,%r2
1856 and,COND(=) %r19,%r2,%r0
1857 b,n syscall_restore_rfi
1859 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1862 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1865 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1866 LDREG TASK_PT_GR19(%r1),%r19
1867 LDREG TASK_PT_GR20(%r1),%r20
1868 LDREG TASK_PT_GR21(%r1),%r21
1869 LDREG TASK_PT_GR22(%r1),%r22
1870 LDREG TASK_PT_GR23(%r1),%r23
1871 LDREG TASK_PT_GR24(%r1),%r24
1872 LDREG TASK_PT_GR25(%r1),%r25
1873 LDREG TASK_PT_GR26(%r1),%r26
1874 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1875 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1876 LDREG TASK_PT_GR29(%r1),%r29
1877 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1879 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1880 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1882 copy %r1,%r30 /* Restore user sp */
1883 mfsp %sr3,%r1 /* Get user space id */
1884 mtsp %r1,%sr7 /* Restore sr7 */
1887 /* Set sr2 to zero for userspace syscalls to work. */
1889 mtsp %r1,%sr4 /* Restore sr4 */
1890 mtsp %r1,%sr5 /* Restore sr5 */
1891 mtsp %r1,%sr6 /* Restore sr6 */
1893 depi 3,31,2,%r31 /* ensure return to user mode. */
1896 /* decide whether to reset the wide mode bit
1898 * For a syscall, the W bit is stored in the lowest bit
1899 * of sp. Extract it and reset W if it is zero */
1900 extrd,u,*<> %r30,63,1,%r1
1902 /* now reset the lowest bit of sp if it was set */
1905 be,n 0(%sr3,%r31) /* return to user space */
1907 /* We have to return via an RFI, so that PSW T and R bits can be set
1909 * This sets up pt_regs so we can return via intr_restore, which is not
1910 * the most efficient way of doing things, but it works.
1912 syscall_restore_rfi:
1913 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1914 mtctl %r2,%cr0 /* for immediate trap */
1915 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1916 ldi 0x0b,%r20 /* Create new PSW */
1917 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1919 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1920 * set in thread_info.h and converted to PA bitmap
1921 * numbers in asm-offsets.c */
1923 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1924 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1925 depi -1,27,1,%r20 /* R bit */
1927 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1928 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1929 depi -1,7,1,%r20 /* T bit */
1931 STREG %r20,TASK_PT_PSW(%r1)
1933 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1936 STREG %r25,TASK_PT_SR3(%r1)
1937 STREG %r25,TASK_PT_SR4(%r1)
1938 STREG %r25,TASK_PT_SR5(%r1)
1939 STREG %r25,TASK_PT_SR6(%r1)
1940 STREG %r25,TASK_PT_SR7(%r1)
1941 STREG %r25,TASK_PT_IASQ0(%r1)
1942 STREG %r25,TASK_PT_IASQ1(%r1)
1945 /* Now if old D bit is clear, it means we didn't save all registers
1946 * on syscall entry, so do that now. This only happens on TRACEME
1947 * calls, or if someone attached to us while we were on a syscall.
1948 * We could make this more efficient by not saving r3-r18, but
1949 * then we wouldn't be able to use the common intr_restore path.
1950 * It is only for traced processes anyway, so performance is not
1953 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1954 ldo TASK_REGS(%r1),%r25
1955 reg_save %r25 /* Save r3 to r18 */
1957 /* Save the current sr */
1959 STREG %r2,TASK_PT_SR0(%r1)
1961 /* Save the scratch sr */
1963 STREG %r2,TASK_PT_SR1(%r1)
1965 /* sr2 should be set to zero for userspace syscalls */
1966 STREG %r0,TASK_PT_SR2(%r1)
1968 LDREG TASK_PT_GR31(%r1),%r2
1969 depi 3,31,2,%r2 /* ensure return to user mode. */
1970 STREG %r2,TASK_PT_IAOQ0(%r1)
1972 STREG %r2,TASK_PT_IAOQ1(%r1)
1977 LDREG TASK_PT_IAOQ0(%r1),%r2
1978 depi 3,31,2,%r2 /* ensure return to user mode. */
1979 STREG %r2,TASK_PT_IAOQ0(%r1)
1980 LDREG TASK_PT_IAOQ1(%r1),%r2
1982 STREG %r2,TASK_PT_IAOQ1(%r1)
1987 load32 syscall_check_resched,%r2 /* if resched, we start over again */
1988 load32 schedule,%r19
1989 bv %r0(%r19) /* jumps to schedule() */
1991 ldo -16(%r30),%r29 /* Reference param save area */
1998 #ifdef CONFIG_FUNCTION_TRACER
2000 .import ftrace_function_trampoline,code
2001 .align L1_CACHE_BYTES
2002 ENTRY_CFI(mcount, caller)
2004 .export _mcount,data
2006 * The 64bit mcount() function pointer needs 4 dwords, of which the
2007 * first two are free. We optimize it here and put 2 instructions for
2008 * calling mcount(), and 2 instructions for ftrace_stub(). That way we
2009 * have all on one L1 cacheline.
2011 b ftrace_function_trampoline
2012 copy %r3, %arg2 /* caller original %sp */
2015 .type ftrace_stub, @function
2024 .dword 0 /* code in head.S puts value of global gp here */
2028 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2030 ENTRY_CFI(return_to_handler, caller,frame=FRAME_SIZE)
2031 .export parisc_return_to_handler,data
2032 parisc_return_to_handler:
2034 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2036 STREGM %r1,FRAME_SIZE(%sp)
2044 /* call ftrace_return_to_handler(0) */
2045 .import ftrace_return_to_handler,code
2046 load32 ftrace_return_to_handler,%ret0
2047 load32 .Lftrace_ret,%r2
2049 ldo -16(%sp),%ret1 /* Reference param save area */
2058 /* restore original return values */
2062 /* return from function */
2068 LDREGM -FRAME_SIZE(%sp),%r3
2069 ENDPROC_CFI(return_to_handler)
2071 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
2073 #endif /* CONFIG_FUNCTION_TRACER */
2075 #ifdef CONFIG_IRQSTACKS
2076 /* void call_on_stack(unsigned long param1, void *func,
2077 unsigned long new_stack) */
2078 ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
2079 ENTRY(_call_on_stack)
2082 /* Regarding the HPPA calling conventions for function pointers,
2083 we assume the PIC register is not changed across call. For
2084 CONFIG_64BIT, the argument pointer is left to point at the
2085 argument region allocated for the call to call_on_stack. */
2087 /* Switch to new stack. We allocate two frames. */
2088 ldo 2*FRAME_SIZE(%arg2), %sp
2089 # ifdef CONFIG_64BIT
2090 /* Save previous stack pointer and return pointer in frame marker */
2091 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2092 /* Calls always use function descriptor */
2093 LDREG 16(%arg1), %arg1
2095 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2096 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2098 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2100 /* Save previous stack pointer and return pointer in frame marker */
2101 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2102 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2103 /* Calls use function descriptor if PLABEL bit is set */
2104 bb,>=,n %arg1, 30, 1f
2106 LDREG 0(%arg1), %arg1
2108 be,l 0(%sr4,%arg1), %sr0, %r31
2110 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2112 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2113 # endif /* CONFIG_64BIT */
2114 ENDPROC_CFI(call_on_stack)
2115 #endif /* CONFIG_IRQSTACKS */
2117 ENTRY_CFI(get_register)
2119 * get_register is used by the non access tlb miss handlers to
2120 * copy the value of the general register specified in r8 into
2121 * r1. This routine can't be used for shadowed registers, since
2122 * the rfir will restore the original value. So, for the shadowed
2123 * registers we put a -1 into r1 to indicate that the register
2124 * should not be used (the register being copied could also have
2125 * a -1 in it, but that is OK, it just means that we will have
2126 * to use the slow path instead).
2130 bv %r0(%r25) /* r0 */
2132 bv %r0(%r25) /* r1 - shadowed */
2134 bv %r0(%r25) /* r2 */
2136 bv %r0(%r25) /* r3 */
2138 bv %r0(%r25) /* r4 */
2140 bv %r0(%r25) /* r5 */
2142 bv %r0(%r25) /* r6 */
2144 bv %r0(%r25) /* r7 */
2146 bv %r0(%r25) /* r8 - shadowed */
2148 bv %r0(%r25) /* r9 - shadowed */
2150 bv %r0(%r25) /* r10 */
2152 bv %r0(%r25) /* r11 */
2154 bv %r0(%r25) /* r12 */
2156 bv %r0(%r25) /* r13 */
2158 bv %r0(%r25) /* r14 */
2160 bv %r0(%r25) /* r15 */
2162 bv %r0(%r25) /* r16 - shadowed */
2164 bv %r0(%r25) /* r17 - shadowed */
2166 bv %r0(%r25) /* r18 */
2168 bv %r0(%r25) /* r19 */
2170 bv %r0(%r25) /* r20 */
2172 bv %r0(%r25) /* r21 */
2174 bv %r0(%r25) /* r22 */
2176 bv %r0(%r25) /* r23 */
2178 bv %r0(%r25) /* r24 - shadowed */
2180 bv %r0(%r25) /* r25 - shadowed */
2182 bv %r0(%r25) /* r26 */
2184 bv %r0(%r25) /* r27 */
2186 bv %r0(%r25) /* r28 */
2188 bv %r0(%r25) /* r29 */
2190 bv %r0(%r25) /* r30 */
2192 bv %r0(%r25) /* r31 */
2194 ENDPROC_CFI(get_register)
2197 ENTRY_CFI(set_register)
2199 * set_register is used by the non access tlb miss handlers to
2200 * copy the value of r1 into the general register specified in
2205 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2207 bv %r0(%r25) /* r1 */
2209 bv %r0(%r25) /* r2 */
2211 bv %r0(%r25) /* r3 */
2213 bv %r0(%r25) /* r4 */
2215 bv %r0(%r25) /* r5 */
2217 bv %r0(%r25) /* r6 */
2219 bv %r0(%r25) /* r7 */
2221 bv %r0(%r25) /* r8 */
2223 bv %r0(%r25) /* r9 */
2225 bv %r0(%r25) /* r10 */
2227 bv %r0(%r25) /* r11 */
2229 bv %r0(%r25) /* r12 */
2231 bv %r0(%r25) /* r13 */
2233 bv %r0(%r25) /* r14 */
2235 bv %r0(%r25) /* r15 */
2237 bv %r0(%r25) /* r16 */
2239 bv %r0(%r25) /* r17 */
2241 bv %r0(%r25) /* r18 */
2243 bv %r0(%r25) /* r19 */
2245 bv %r0(%r25) /* r20 */
2247 bv %r0(%r25) /* r21 */
2249 bv %r0(%r25) /* r22 */
2251 bv %r0(%r25) /* r23 */
2253 bv %r0(%r25) /* r24 */
2255 bv %r0(%r25) /* r25 */
2257 bv %r0(%r25) /* r26 */
2259 bv %r0(%r25) /* r27 */
2261 bv %r0(%r25) /* r28 */
2263 bv %r0(%r25) /* r29 */
2265 bv %r0(%r25) /* r30 */
2267 bv %r0(%r25) /* r31 */
2269 ENDPROC_CFI(set_register)