2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <linux/init.h>
20 #include <asm/assembler.h>
21 #include <asm/memory.h>
22 #include <asm/glue-df.h>
23 #include <asm/glue-pf.h>
24 #include <asm/vfpmacros.h>
25 #ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER
26 #include <mach/entry-macro.S>
28 #include <asm/thread_notify.h>
29 #include <asm/unwind.h>
30 #include <asm/unistd.h>
32 #include <asm/system_info.h>
33 #include <asm/uaccess-asm.h>
35 #include "entry-header.S"
36 #include <asm/entry-macro-multi.S>
37 #include <asm/probes.h>
43 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
44 ldr r1, =handle_arch_irq
49 arch_irq_handler_default
55 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
59 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
68 @ Call the processor-specific abort handler:
71 @ r4 - aborted context pc
72 @ r5 - aborted context psr
74 @ The abort handler must return the aborted address in r0, and
75 @ the fault status register in r1. r9 must be preserved.
80 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
86 .section .entry.text,"ax",%progbits
89 * Invalid mode handlers
91 .macro inv_entry, reason
92 sub sp, sp, #PT_REGS_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
101 inv_entry BAD_PREFETCH
103 ENDPROC(__pabt_invalid)
108 ENDPROC(__dabt_invalid)
113 ENDPROC(__irq_invalid)
116 inv_entry BAD_UNDEFINSTR
119 @ XXX fall through to common_invalid
123 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
137 ENDPROC(__und_invalid)
143 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144 #define SPFIX(code...) code
146 #define SPFIX(code...)
149 .macro svc_entry, stack_hole=0, trace=1, uaccess=1
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
153 #ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
161 SPFIX( subeq sp, sp, #4 )
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
175 @ We are now ready to fill in the remaining blanks on the stack:
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
186 uaccess_entry tsk, r0, r1, r2, \uaccess
189 #ifdef CONFIG_TRACE_IRQFLAGS
190 bl trace_hardirqs_off
200 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
201 svc_exit r5 @ return from exception
210 #ifdef CONFIG_PREEMPT
211 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
212 ldr r0, [tsk, #TI_FLAGS] @ get flags
213 teq r8, #0 @ if preempt count != 0
214 movne r0, #0 @ force flags to 0
215 tst r0, #_TIF_NEED_RESCHED
219 svc_exit r5, irq = 1 @ return from exception
225 #ifdef CONFIG_PREEMPT
228 1: bl preempt_schedule_irq @ irq en/disable is done inside
229 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
230 tst r0, #_TIF_NEED_RESCHED
236 @ Correct the PC such that it is pointing at the instruction
237 @ which caused the fault. If the faulting instruction was ARM
238 @ the PC will be pointing at the next instruction, and have to
239 @ subtract 4. Otherwise, it is Thumb, and the PC will be
240 @ pointing at the second half of the Thumb instruction. We
241 @ have to subtract 2.
250 #ifdef CONFIG_KPROBES
251 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
252 @ it obviously needs free stack space which then will belong to
254 svc_entry MAX_STACK_SIZE
259 @ call emulation code, which returns using r9 if it has emulated
260 @ the instruction, or the more conventional lr if we are to treat
261 @ this as a real undefined instruction
265 #ifndef CONFIG_THUMB2_KERNEL
269 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
270 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
272 ldrh r9, [r4] @ bottom 16 bits
275 orr r0, r9, r0, lsl #16
277 badr r9, __und_svc_finish
281 mov r1, #4 @ PC correction to apply
283 mov r0, sp @ struct pt_regs *regs
288 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
289 svc_exit r5 @ return from exception
298 svc_exit r5 @ return from exception
305 mov r0, sp @ struct pt_regs *regs
322 * Abort mode handlers
326 @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
327 @ and reuses the same macros. However in abort mode we must also
328 @ save/restore lr_abt and spsr_abt to make nested aborts safe.
334 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
335 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
336 THUMB( msr cpsr_c, r0 )
337 mov r1, lr @ Save lr_abt
338 mrs r2, spsr @ Save spsr_abt, abort is now safe
339 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
340 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
341 THUMB( msr cpsr_c, r0 )
344 add r0, sp, #8 @ struct pt_regs *regs
348 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
349 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
350 THUMB( msr cpsr_c, r0 )
351 mov lr, r1 @ Restore lr_abt, abort is unsafe
352 msr spsr_cxsf, r2 @ Restore spsr_abt
353 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
354 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
355 THUMB( msr cpsr_c, r0 )
364 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
367 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7)
368 #error "sizeof(struct pt_regs) must be a multiple of 8"
371 .macro usr_entry, trace=1, uaccess=1
373 UNWIND(.cantunwind ) @ don't unwind the user space
374 sub sp, sp, #PT_REGS_SIZE
375 ARM( stmib sp, {r1 - r12} )
376 THUMB( stmia sp, {r0 - r12} )
378 ATRAP( mrc p15, 0, r7, c1, c0, 0)
379 ATRAP( ldr r8, .LCcralign)
382 add r0, sp, #S_PC @ here for interlock avoidance
383 mov r6, #-1 @ "" "" "" ""
385 str r3, [sp] @ save the "real" r0 copied
386 @ from the exception stack
388 ATRAP( ldr r8, [r8, #0])
391 @ We are now ready to fill in the remaining blanks on the stack:
393 @ r4 - lr_<exception>, already fixed up for correct return/restart
394 @ r5 - spsr_<exception>
395 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
397 @ Also, separately save sp_usr and lr_usr
400 ARM( stmdb r0, {sp, lr}^ )
401 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
407 @ Enable the alignment trap while in kernel mode
409 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
412 @ Clear FP to mark the first stack frame
417 #ifdef CONFIG_TRACE_IRQFLAGS
418 bl trace_hardirqs_off
420 ct_user_exit save = 0
424 .macro kuser_cmpxchg_check
425 #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
427 #warning "NPTL on non MMU needs fixing"
429 @ Make sure our user space atomic helper is restarted
430 @ if it was interrupted in a critical region. Here we
431 @ perform a quick test inline since it should be false
432 @ 99.9999% of the time. The rest is done out of line.
434 blhs kuser_cmpxchg64_fixup
456 b ret_to_user_from_irq
469 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
470 @ faulting instruction depending on Thumb mode.
471 @ r3 = regs->ARM_cpsr
473 @ The emulation code returns using r9 if it has emulated the
474 @ instruction, or the more conventional lr if we are to treat
475 @ this as a real undefined instruction
477 badr r9, ret_from_exception
479 @ IRQs must be enabled before attempting to read the instruction from
480 @ user space since that could cause a page/translation fault if the
481 @ page table was modified by another CPU.
484 tst r3, #PSR_T_BIT @ Thumb mode?
486 sub r4, r2, #4 @ ARM instr at LR - 4
488 ARM_BE8(rev r0, r0) @ little endian instruction
492 @ r0 = 32-bit ARM instruction which caused the exception
493 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
494 @ r4 = PC value for the faulting instruction
495 @ lr = 32-bit undefined instruction function
496 badr lr, __und_usr_fault_32
501 sub r4, r2, #2 @ First half of thumb instr at LR - 2
502 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
504 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
505 * can never be supported in a single kernel, this code is not applicable at
506 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
507 * made about .arch directives.
509 #if __LINUX_ARM_ARCH__ < 7
510 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
511 #define NEED_CPU_ARCHITECTURE
512 ldr r5, .LCcpu_architecture
514 cmp r5, #CPU_ARCH_ARMv7
515 blo __und_usr_fault_16 @ 16bit undefined instruction
517 * The following code won't get run unless the running CPU really is v7, so
518 * coding round the lack of ldrht on older arches is pointless. Temporarily
519 * override the assembler target arch with the minimum required instead:
524 ARM_BE8(rev16 r5, r5) @ little endian instruction
525 cmp r5, #0xe800 @ 32bit instruction if xx != 0
526 blo __und_usr_fault_16_pan @ 16bit undefined instruction
528 ARM_BE8(rev16 r0, r0) @ little endian instruction
530 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
531 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
532 orr r0, r0, r5, lsl #16
533 badr lr, __und_usr_fault_32
534 @ r0 = the two 16-bit Thumb instructions which caused the exception
535 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
536 @ r4 = PC value for the first 16-bit Thumb instruction
537 @ lr = 32bit undefined instruction function
539 #if __LINUX_ARM_ARCH__ < 7
540 /* If the target arch was overridden, change it back: */
541 #ifdef CONFIG_CPU_32v6K
546 #endif /* __LINUX_ARM_ARCH__ < 7 */
547 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
554 * The out of line fixup for the ldrt instructions above.
556 .pushsection .text.fixup, "ax"
558 4: str r4, [sp, #S_PC] @ retry current instruction
561 .pushsection __ex_table,"a"
563 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
570 * Check whether the instruction is a co-processor instruction.
571 * If yes, we need to call the relevant co-processor handler.
573 * Note that we don't do a full check here for the co-processor
574 * instructions; all instructions with bit 27 set are well
575 * defined. The only instructions that should fault are the
576 * co-processor instructions. However, we have to watch out
577 * for the ARM6/ARM7 SWI bug.
579 * NEON is a special case that has to be handled here. Not all
580 * NEON instructions are co-processor instructions, so we have
581 * to make a special case of checking for them. Plus, there's
582 * five groups of them, so we have a table of mask/opcode pairs
583 * to check against, and if any match then we branch off into the
586 * Emulators may wish to make use of the following registers:
587 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
588 * r2 = PC value to resume execution after successful emulation
589 * r9 = normal "successful" return address
590 * r10 = this threads thread_info structure
591 * lr = unrecognised instruction return address
592 * IRQs enabled, FIQs enabled.
595 @ Fall-through from Thumb-2 __und_usr
598 get_thread_info r10 @ get current thread
599 adr r6, .LCneon_thumb_opcodes
603 get_thread_info r10 @ get current thread
605 adr r6, .LCneon_arm_opcodes
606 2: ldr r5, [r6], #4 @ mask value
607 ldr r7, [r6], #4 @ opcode bits matching in mask
608 cmp r5, #0 @ end mask?
611 cmp r8, r7 @ NEON instruction?
614 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
615 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
616 b do_vfp @ let VFP handler handle this
619 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
620 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
622 and r8, r0, #0x00000f00 @ mask out CP number
624 add r6, r10, r8, lsr #8 @ add used_cp[] array offset first
625 strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[]
627 @ Test if we need to give access to iWMMXt coprocessors
628 ldr r5, [r10, #TI_FLAGS]
629 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
630 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
631 bcs iwmmxt_task_enable
633 ARM( add pc, pc, r8, lsr #6 )
634 THUMB( lsr r8, r8, #6 )
639 W(b) do_fpe @ CP#1 (FPE)
640 W(b) do_fpe @ CP#2 (FPE)
643 b crunch_task_enable @ CP#4 (MaverickCrunch)
644 b crunch_task_enable @ CP#5 (MaverickCrunch)
645 b crunch_task_enable @ CP#6 (MaverickCrunch)
655 W(b) do_vfp @ CP#10 (VFP)
656 W(b) do_vfp @ CP#11 (VFP)
658 ret.w lr @ CP#10 (VFP)
659 ret.w lr @ CP#11 (VFP)
663 ret.w lr @ CP#14 (Debug)
664 ret.w lr @ CP#15 (Control)
666 #ifdef NEED_CPU_ARCHITECTURE
669 .word __cpu_architecture
676 .word 0xfe000000 @ mask
677 .word 0xf2000000 @ opcode
679 .word 0xff100000 @ mask
680 .word 0xf4000000 @ opcode
682 .word 0x00000000 @ mask
683 .word 0x00000000 @ opcode
685 .LCneon_thumb_opcodes:
686 .word 0xef000000 @ mask
687 .word 0xef000000 @ opcode
689 .word 0xff100000 @ mask
690 .word 0xf9000000 @ opcode
692 .word 0x00000000 @ mask
693 .word 0x00000000 @ opcode
698 add r10, r10, #TI_FPSTATE @ r10 = workspace
699 ldr pc, [r4] @ Call FP module USR entry point
702 * The FP module is called with these registers set:
705 * r9 = normal "successful" return address
707 * lr = unrecognised FP instruction return address
723 __und_usr_fault_16_pan:
728 badr lr, ret_from_exception
730 ENDPROC(__und_usr_fault_32)
731 ENDPROC(__und_usr_fault_16)
741 * This is the return code to user mode for abort handlers
743 ENTRY(ret_from_exception)
751 ENDPROC(ret_from_exception)
757 mov r0, sp @ struct pt_regs *regs
760 restore_user_regs fast = 0, offset = 0
765 * Register switch for ARMv3 and ARMv4 processors
766 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
767 * previous and next are guaranteed not to be the same.
772 add ip, r1, #TI_CPU_SAVE
773 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
774 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
775 THUMB( str sp, [ip], #4 )
776 THUMB( str lr, [ip], #4 )
777 ldr r4, [r2, #TI_TP_VALUE]
778 ldr r5, [r2, #TI_TP_VALUE + 4]
779 #ifdef CONFIG_CPU_USE_DOMAINS
780 mrc p15, 0, r6, c3, c0, 0 @ Get domain register
781 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
782 ldr r6, [r2, #TI_CPU_DOMAIN]
784 switch_tls r1, r4, r5, r3, r7
785 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
786 ldr r7, [r2, #TI_TASK]
787 ldr r8, =__stack_chk_guard
788 .if (TSK_STACK_CANARY > IMM12_MASK)
789 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK
791 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK]
793 #ifdef CONFIG_CPU_USE_DOMAINS
794 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
797 add r4, r2, #TI_CPU_SAVE
798 ldr r0, =thread_notify_head
799 mov r1, #THREAD_NOTIFY_SWITCH
800 bl atomic_notifier_call_chain
801 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
806 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
807 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
808 THUMB( ldr sp, [ip], #4 )
809 THUMB( ldr pc, [ip] )
818 * Each segment is 32-byte aligned and will be moved to the top of the high
819 * vector page. New segments (if ever needed) must be added in front of
820 * existing ones. This mechanism should be used only for things that are
821 * really small and justified, and not be abused freely.
823 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
828 #ifdef CONFIG_ARM_THUMB
835 .macro kuser_pad, sym, size
837 .rept 4 - (. - \sym) & 3
841 .rept (\size - (. - \sym)) / 4
846 #ifdef CONFIG_KUSER_HELPERS
848 .globl __kuser_helper_start
849 __kuser_helper_start:
852 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
853 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
856 __kuser_cmpxchg64: @ 0xffff0f60
858 #if defined(CONFIG_CPU_32v6K)
860 stmfd sp!, {r4, r5, r6, r7}
861 ldrd r4, r5, [r0] @ load old val
862 ldrd r6, r7, [r1] @ load new val
864 1: ldrexd r0, r1, [r2] @ load current val
865 eors r3, r0, r4 @ compare with oldval (1)
866 eoreqs r3, r1, r5 @ compare with oldval (2)
867 strexdeq r3, r6, r7, [r2] @ store newval if eq
868 teqeq r3, #1 @ success?
869 beq 1b @ if no then retry
871 rsbs r0, r3, #0 @ set returned val and C flag
872 ldmfd sp!, {r4, r5, r6, r7}
875 #elif !defined(CONFIG_SMP)
880 * The only thing that can break atomicity in this cmpxchg64
881 * implementation is either an IRQ or a data abort exception
882 * causing another process/thread to be scheduled in the middle of
883 * the critical sequence. The same strategy as for cmpxchg is used.
885 stmfd sp!, {r4, r5, r6, lr}
886 ldmia r0, {r4, r5} @ load old val
887 ldmia r1, {r6, lr} @ load new val
888 1: ldmia r2, {r0, r1} @ load current val
889 eors r3, r0, r4 @ compare with oldval (1)
890 eoreqs r3, r1, r5 @ compare with oldval (2)
891 2: stmeqia r2, {r6, lr} @ store newval if eq
892 rsbs r0, r3, #0 @ set return val and C flag
893 ldmfd sp!, {r4, r5, r6, pc}
896 kuser_cmpxchg64_fixup:
897 @ Called from kuser_cmpxchg_fixup.
898 @ r4 = address of interrupted insn (must be preserved).
899 @ sp = saved regs. r7 and r8 are clobbered.
900 @ 1b = first critical insn, 2b = last critical insn.
901 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
903 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
905 rsbcss r8, r8, #(2b - 1b)
906 strcs r7, [sp, #S_PC]
907 #if __LINUX_ARM_ARCH__ < 6
908 bcc kuser_cmpxchg32_fixup
914 #warning "NPTL on non MMU needs fixing"
921 #error "incoherent kernel configuration"
924 kuser_pad __kuser_cmpxchg64, 64
926 __kuser_memory_barrier: @ 0xffff0fa0
930 kuser_pad __kuser_memory_barrier, 32
932 __kuser_cmpxchg: @ 0xffff0fc0
934 #if __LINUX_ARM_ARCH__ < 6
939 * The only thing that can break atomicity in this cmpxchg
940 * implementation is either an IRQ or a data abort exception
941 * causing another process/thread to be scheduled in the middle
942 * of the critical sequence. To prevent this, code is added to
943 * the IRQ and data abort exception handlers to set the pc back
944 * to the beginning of the critical section if it is found to be
945 * within that critical section (see kuser_cmpxchg_fixup).
947 1: ldr r3, [r2] @ load current val
948 subs r3, r3, r0 @ compare with oldval
949 2: streq r1, [r2] @ store newval if eq
950 rsbs r0, r3, #0 @ set return val and C flag
954 kuser_cmpxchg32_fixup:
955 @ Called from kuser_cmpxchg_check macro.
956 @ r4 = address of interrupted insn (must be preserved).
957 @ sp = saved regs. r7 and r8 are clobbered.
958 @ 1b = first critical insn, 2b = last critical insn.
959 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
961 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
963 rsbcss r8, r8, #(2b - 1b)
964 strcs r7, [sp, #S_PC]
969 #warning "NPTL on non MMU needs fixing"
984 /* beware -- each __kuser slot must be 8 instructions max */
985 ALT_SMP(b __kuser_memory_barrier)
990 kuser_pad __kuser_cmpxchg, 32
992 __kuser_get_tls: @ 0xffff0fe0
993 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
995 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
996 kuser_pad __kuser_get_tls, 16
998 .word 0 @ 0xffff0ff0 software TLS value, then
999 .endr @ pad up to __kuser_helper_version
1001 __kuser_helper_version: @ 0xffff0ffc
1002 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1004 .globl __kuser_helper_end
1014 * This code is copied to 0xffff1000 so we can use branches in the
1015 * vectors, rather than ldr's. Note that this code must not exceed
1018 * Common stub entry macro:
1019 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1021 * SP points to a minimal amount of processor-private memory, the address
1022 * of which is copied into r0 for the mode specific abort handler.
1024 .macro vector_stub, name, mode, correction=0
1029 sub lr, lr, #\correction
1032 @ Save r0, lr_<exception> (parent PC)
1033 stmia sp, {r0, lr} @ save r0, lr
1035 @ Save spsr_<exception> (parent CPSR)
1037 str lr, [sp, #8] @ save spsr
1040 @ Prepare for SVC32 mode. IRQs remain disabled.
1043 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1047 @ the branch table must immediately follow this code
1051 THUMB( ldr lr, [r0, lr, lsl #2] )
1053 ARM( ldr lr, [pc, lr, lsl #2] )
1054 movs pc, lr @ branch to handler in SVC mode
1055 ENDPROC(vector_\name)
1057 #ifdef CONFIG_HARDEN_BRANCH_HISTORY
1060 vector_bhb_loop8_\name:
1062 sub lr, lr, #\correction
1065 @ Save r0, lr_<exception> (parent PC)
1076 ENDPROC(vector_bhb_loop8_\name)
1078 vector_bhb_bpiall_\name:
1080 sub lr, lr, #\correction
1083 @ Save r0, lr_<exception> (parent PC)
1087 mcr p15, 0, r0, c7, c5, 6 @ BPIALL
1088 @ isb not needed due to "movs pc, lr" in the vector stub
1089 @ which gives a "context synchronisation".
1091 ENDPROC(vector_bhb_bpiall_\name)
1096 @ handler addresses follow this label
1100 .section .stubs, "ax", %progbits
1101 @ This must be the first word
1103 #ifdef CONFIG_HARDEN_BRANCH_HISTORY
1104 .word vector_bhb_loop8_swi
1105 .word vector_bhb_bpiall_swi
1109 ARM( swi SYS_ERROR0 )
1115 * Interrupt dispatcher
1117 vector_stub irq, IRQ_MODE, 4
1119 .long __irq_usr @ 0 (USR_26 / USR_32)
1120 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1121 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1122 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1123 .long __irq_invalid @ 4
1124 .long __irq_invalid @ 5
1125 .long __irq_invalid @ 6
1126 .long __irq_invalid @ 7
1127 .long __irq_invalid @ 8
1128 .long __irq_invalid @ 9
1129 .long __irq_invalid @ a
1130 .long __irq_invalid @ b
1131 .long __irq_invalid @ c
1132 .long __irq_invalid @ d
1133 .long __irq_invalid @ e
1134 .long __irq_invalid @ f
1137 * Data abort dispatcher
1138 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1140 vector_stub dabt, ABT_MODE, 8
1142 .long __dabt_usr @ 0 (USR_26 / USR_32)
1143 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1144 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1145 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1146 .long __dabt_invalid @ 4
1147 .long __dabt_invalid @ 5
1148 .long __dabt_invalid @ 6
1149 .long __dabt_invalid @ 7
1150 .long __dabt_invalid @ 8
1151 .long __dabt_invalid @ 9
1152 .long __dabt_invalid @ a
1153 .long __dabt_invalid @ b
1154 .long __dabt_invalid @ c
1155 .long __dabt_invalid @ d
1156 .long __dabt_invalid @ e
1157 .long __dabt_invalid @ f
1160 * Prefetch abort dispatcher
1161 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1163 vector_stub pabt, ABT_MODE, 4
1165 .long __pabt_usr @ 0 (USR_26 / USR_32)
1166 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1167 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1168 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1169 .long __pabt_invalid @ 4
1170 .long __pabt_invalid @ 5
1171 .long __pabt_invalid @ 6
1172 .long __pabt_invalid @ 7
1173 .long __pabt_invalid @ 8
1174 .long __pabt_invalid @ 9
1175 .long __pabt_invalid @ a
1176 .long __pabt_invalid @ b
1177 .long __pabt_invalid @ c
1178 .long __pabt_invalid @ d
1179 .long __pabt_invalid @ e
1180 .long __pabt_invalid @ f
1183 * Undef instr entry dispatcher
1184 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1186 vector_stub und, UND_MODE
1188 .long __und_usr @ 0 (USR_26 / USR_32)
1189 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1190 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1191 .long __und_svc @ 3 (SVC_26 / SVC_32)
1192 .long __und_invalid @ 4
1193 .long __und_invalid @ 5
1194 .long __und_invalid @ 6
1195 .long __und_invalid @ 7
1196 .long __und_invalid @ 8
1197 .long __und_invalid @ 9
1198 .long __und_invalid @ a
1199 .long __und_invalid @ b
1200 .long __und_invalid @ c
1201 .long __und_invalid @ d
1202 .long __und_invalid @ e
1203 .long __und_invalid @ f
1207 /*=============================================================================
1208 * Address exception handler
1209 *-----------------------------------------------------------------------------
1210 * These aren't too critical.
1211 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1217 /*=============================================================================
1219 *-----------------------------------------------------------------------------
1220 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1221 * systems. This must be the last vector stub, so lets place it in its own
1225 vector_stub fiq, FIQ_MODE, 4
1227 .long __fiq_usr @ 0 (USR_26 / USR_32)
1228 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1229 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1230 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1246 .section .vectors, "ax", %progbits
1250 W(ldr) pc, .L__vectors_start + 0x1000
1253 W(b) vector_addrexcptn
1257 #ifdef CONFIG_HARDEN_BRANCH_HISTORY
1258 .section .vectors.bhb.loop8, "ax", %progbits
1259 .L__vectors_bhb_loop8_start:
1261 W(b) vector_bhb_loop8_und
1262 W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
1263 W(b) vector_bhb_loop8_pabt
1264 W(b) vector_bhb_loop8_dabt
1265 W(b) vector_addrexcptn
1266 W(b) vector_bhb_loop8_irq
1267 W(b) vector_bhb_loop8_fiq
1269 .section .vectors.bhb.bpiall, "ax", %progbits
1270 .L__vectors_bhb_bpiall_start:
1272 W(b) vector_bhb_bpiall_und
1273 W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
1274 W(b) vector_bhb_bpiall_pabt
1275 W(b) vector_bhb_bpiall_dabt
1276 W(b) vector_addrexcptn
1277 W(b) vector_bhb_bpiall_irq
1278 W(b) vector_bhb_bpiall_fiq