1 // SPDX-License-Identifier: GPL-2.0
3 * arch-independent dma-mapping routines
5 * Copyright (c) 2006 SUSE Linux Products GmbH
6 * Copyright (c) 2006 Tejun Heo <teheo@suse.de>
8 #include <linux/memblock.h> /* for max_pfn */
9 #include <linux/acpi.h>
10 #include <linux/dma-direct.h>
11 #include <linux/dma-noncoherent.h>
12 #include <linux/export.h>
13 #include <linux/gfp.h>
14 #include <linux/of_device.h>
15 #include <linux/slab.h>
16 #include <linux/vmalloc.h>
24 dma_addr_t dma_handle;
28 static void dmam_release(struct device *dev, void *res)
30 struct dma_devres *this = res;
32 dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle,
36 static int dmam_match(struct device *dev, void *res, void *match_data)
38 struct dma_devres *this = res, *match = match_data;
40 if (this->vaddr == match->vaddr) {
41 WARN_ON(this->size != match->size ||
42 this->dma_handle != match->dma_handle);
49 * dmam_free_coherent - Managed dma_free_coherent()
50 * @dev: Device to free coherent memory for
51 * @size: Size of allocation
52 * @vaddr: Virtual address of the memory to free
53 * @dma_handle: DMA handle of the memory to free
55 * Managed dma_free_coherent().
57 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
58 dma_addr_t dma_handle)
60 struct dma_devres match_data = { size, vaddr, dma_handle };
62 dma_free_coherent(dev, size, vaddr, dma_handle);
63 WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data));
65 EXPORT_SYMBOL(dmam_free_coherent);
68 * dmam_alloc_attrs - Managed dma_alloc_attrs()
69 * @dev: Device to allocate non_coherent memory for
70 * @size: Size of allocation
71 * @dma_handle: Out argument for allocated DMA handle
72 * @gfp: Allocation flags
73 * @attrs: Flags in the DMA_ATTR_* namespace.
75 * Managed dma_alloc_attrs(). Memory allocated using this function will be
76 * automatically released on driver detach.
79 * Pointer to allocated memory on success, NULL on failure.
81 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
82 gfp_t gfp, unsigned long attrs)
84 struct dma_devres *dr;
87 dr = devres_alloc(dmam_release, sizeof(*dr), gfp);
91 vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs);
98 dr->dma_handle = *dma_handle;
106 EXPORT_SYMBOL(dmam_alloc_attrs);
109 * Create scatter-list for the already allocated DMA buffer.
111 int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
112 void *cpu_addr, dma_addr_t dma_addr, size_t size,
118 if (!dev_is_dma_coherent(dev)) {
121 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
124 /* If the PFN is not valid, we do not have a struct page */
125 pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
128 page = pfn_to_page(pfn);
130 page = virt_to_page(cpu_addr);
133 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
135 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
140 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems
141 * that the intention is to allow exporting memory allocated via the
142 * coherent DMA APIs through the dma_buf API, which only accepts a
143 * scattertable. This presents a couple of problems:
144 * 1. Not all memory allocated via the coherent DMA APIs is backed by
146 * 2. Passing coherent DMA memory into the streaming APIs is not allowed
147 * as we will try to flush the memory through a different alias to that
148 * actually being used (and the flushes are redundant.)
150 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
151 void *cpu_addr, dma_addr_t dma_addr, size_t size,
154 const struct dma_map_ops *ops = get_dma_ops(dev);
156 if (dma_is_direct(ops))
157 return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr,
159 if (!ops->get_sgtable)
161 return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs);
163 EXPORT_SYMBOL(dma_get_sgtable_attrs);
167 * Return the page attributes used for mapping dma_alloc_* memory, either in
168 * kernel space if remapping is needed, or to userspace through dma_mmap_*.
170 pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
172 if (force_dma_unencrypted(dev))
173 prot = pgprot_decrypted(prot);
174 if (dev_is_dma_coherent(dev) ||
175 (IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) &&
176 (attrs & DMA_ATTR_NON_CONSISTENT)))
178 #ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE
179 if (attrs & DMA_ATTR_WRITE_COMBINE)
180 return pgprot_writecombine(prot);
182 return pgprot_dmacoherent(prot);
184 #endif /* CONFIG_MMU */
187 * Create userspace mapping for the DMA-coherent memory.
189 int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
190 void *cpu_addr, dma_addr_t dma_addr, size_t size,
194 unsigned long user_count = vma_pages(vma);
195 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
196 unsigned long off = vma->vm_pgoff;
200 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
202 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
205 if (off >= count || user_count > count - off)
208 if (!dev_is_dma_coherent(dev)) {
209 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
212 /* If the PFN is not valid, we do not have a struct page */
213 pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
217 pfn = page_to_pfn(virt_to_page(cpu_addr));
220 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
221 user_count << PAGE_SHIFT, vma->vm_page_prot);
224 #endif /* CONFIG_MMU */
228 * dma_can_mmap - check if a given device supports dma_mmap_*
229 * @dev: device to check
231 * Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to
232 * map DMA allocations to userspace.
234 bool dma_can_mmap(struct device *dev)
236 const struct dma_map_ops *ops = get_dma_ops(dev);
238 if (dma_is_direct(ops)) {
239 return IS_ENABLED(CONFIG_MMU) &&
240 (dev_is_dma_coherent(dev) ||
241 IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN));
244 return ops->mmap != NULL;
246 EXPORT_SYMBOL_GPL(dma_can_mmap);
249 * dma_mmap_attrs - map a coherent DMA allocation into user space
250 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
251 * @vma: vm_area_struct describing requested user mapping
252 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
253 * @dma_addr: device-view address returned from dma_alloc_attrs
254 * @size: size of memory originally requested in dma_alloc_attrs
255 * @attrs: attributes of mapping properties requested in dma_alloc_attrs
257 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user
258 * space. The coherent DMA buffer must not be freed by the driver until the
259 * user space mapping has been released.
261 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
262 void *cpu_addr, dma_addr_t dma_addr, size_t size,
265 const struct dma_map_ops *ops = get_dma_ops(dev);
267 if (dma_is_direct(ops))
268 return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size,
272 return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
274 EXPORT_SYMBOL(dma_mmap_attrs);
276 u64 dma_get_required_mask(struct device *dev)
278 const struct dma_map_ops *ops = get_dma_ops(dev);
280 if (dma_is_direct(ops))
281 return dma_direct_get_required_mask(dev);
282 if (ops->get_required_mask)
283 return ops->get_required_mask(dev);
286 * We require every DMA ops implementation to at least support a 32-bit
287 * DMA mask (and use bounce buffering if that isn't supported in
288 * hardware). As the direct mapping code has its own routine to
289 * actually report an optimal mask we default to 32-bit here as that
290 * is the right thing for most IOMMUs, and at least not actively
291 * harmful in general.
293 return DMA_BIT_MASK(32);
295 EXPORT_SYMBOL_GPL(dma_get_required_mask);
297 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
298 gfp_t flag, unsigned long attrs)
300 const struct dma_map_ops *ops = get_dma_ops(dev);
303 WARN_ON_ONCE(!dev->coherent_dma_mask);
305 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr))
308 /* let the implementation decide on the zone to allocate from: */
309 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
311 if (dma_is_direct(ops))
312 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
314 cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
318 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
321 EXPORT_SYMBOL(dma_alloc_attrs);
323 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
324 dma_addr_t dma_handle, unsigned long attrs)
326 const struct dma_map_ops *ops = get_dma_ops(dev);
328 if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
331 * On non-coherent platforms which implement DMA-coherent buffers via
332 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting
333 * this far in IRQ context is a) at risk of a BUG_ON() or trying to
334 * sleep on some machines, and b) an indication that the driver is
335 * probably misusing the coherent API anyway.
337 WARN_ON(irqs_disabled());
342 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
343 if (dma_is_direct(ops))
344 dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
346 ops->free(dev, size, cpu_addr, dma_handle, attrs);
348 EXPORT_SYMBOL(dma_free_attrs);
350 int dma_supported(struct device *dev, u64 mask)
352 const struct dma_map_ops *ops = get_dma_ops(dev);
354 if (dma_is_direct(ops))
355 return dma_direct_supported(dev, mask);
356 if (!ops->dma_supported)
358 return ops->dma_supported(dev, mask);
360 EXPORT_SYMBOL(dma_supported);
362 #ifdef CONFIG_ARCH_HAS_DMA_SET_MASK
363 void arch_dma_set_mask(struct device *dev, u64 mask);
365 #define arch_dma_set_mask(dev, mask) do { } while (0)
368 int dma_set_mask(struct device *dev, u64 mask)
371 * Truncate the mask to the actually supported dma_addr_t width to
372 * avoid generating unsupportable addresses.
374 mask = (dma_addr_t)mask;
376 if (!dev->dma_mask || !dma_supported(dev, mask))
379 arch_dma_set_mask(dev, mask);
380 *dev->dma_mask = mask;
383 EXPORT_SYMBOL(dma_set_mask);
385 #ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
386 int dma_set_coherent_mask(struct device *dev, u64 mask)
389 * Truncate the mask to the actually supported dma_addr_t width to
390 * avoid generating unsupportable addresses.
392 mask = (dma_addr_t)mask;
394 if (!dma_supported(dev, mask))
397 dev->coherent_dma_mask = mask;
400 EXPORT_SYMBOL(dma_set_coherent_mask);
403 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
404 enum dma_data_direction dir)
406 const struct dma_map_ops *ops = get_dma_ops(dev);
408 BUG_ON(!valid_dma_direction(dir));
410 if (dma_is_direct(ops))
411 arch_dma_cache_sync(dev, vaddr, size, dir);
412 else if (ops->cache_sync)
413 ops->cache_sync(dev, vaddr, size, dir);
415 EXPORT_SYMBOL(dma_cache_sync);
417 size_t dma_max_mapping_size(struct device *dev)
419 const struct dma_map_ops *ops = get_dma_ops(dev);
420 size_t size = SIZE_MAX;
422 if (dma_is_direct(ops))
423 size = dma_direct_max_mapping_size(dev);
424 else if (ops && ops->max_mapping_size)
425 size = ops->max_mapping_size(dev);
429 EXPORT_SYMBOL_GPL(dma_max_mapping_size);
431 unsigned long dma_get_merge_boundary(struct device *dev)
433 const struct dma_map_ops *ops = get_dma_ops(dev);
435 if (!ops || !ops->get_merge_boundary)
436 return 0; /* can't merge */
438 return ops->get_merge_boundary(dev);
440 EXPORT_SYMBOL_GPL(dma_get_merge_boundary);