kernel/dma/direct.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018-2020 Christoph Hellwig.
   4  *
   5  * DMA operations that map physical memory directly without using an IOMMU.
   6  */
   7 #include <linux/memblock.h> /* for max_pfn */
   8 #include <linux/export.h>
   9 #include <linux/mm.h>
  10 #include <linux/dma-map-ops.h>
  11 #include <linux/scatterlist.h>
  12 #include <linux/pfn.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/set_memory.h>
  15 #include <linux/slab.h>
  16 #include "direct.h"
  17
  18 /*
  19  * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
  20  * it for entirely different regions. In that case the arch code needs to
  21  * override the variable below for dma-direct to work properly.
  22  */
  23 unsigned int zone_dma_bits __ro_after_init = 24;
  24
  25 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
  26                 phys_addr_t phys)
  27 {
  28         if (force_dma_unencrypted(dev))
  29                 return phys_to_dma_unencrypted(dev, phys);
  30         return phys_to_dma(dev, phys);
  31 }
  32
  33 static inline struct page *dma_direct_to_page(struct device *dev,
  34                 dma_addr_t dma_addr)
  35 {
  36         return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
  37 }
  38
  39 u64 dma_direct_get_required_mask(struct device *dev)
  40 {
  41         phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
  42         u64 max_dma = phys_to_dma_direct(dev, phys);
  43
  44         return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
  45 }
  46
  47 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
  48                                   u64 *phys_limit)
  49 {
  50         u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
  51
  52         /*
  53          * Optimistically try the zone that the physical address mask falls
  54          * into first.  If that returns memory that isn't actually addressable
  55          * we will fallback to the next lower zone and try again.
  56          *
  57          * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
  58          * zones.
  59          */
  60         *phys_limit = dma_to_phys(dev, dma_limit);
  61         if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
  62                 return GFP_DMA;
  63         if (*phys_limit <= DMA_BIT_MASK(32))
  64                 return GFP_DMA32;
  65         return 0;
  66 }
  67
  68 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
  69 {
  70         dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
  71
  72         if (dma_addr == DMA_MAPPING_ERROR)
  73                 return false;
  74         return dma_addr + size - 1 <=
  75                 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
  76 }
  77
  78 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
  79                 gfp_t gfp)
  80 {
  81         int node = dev_to_node(dev);
  82         struct page *page = NULL;
  83         u64 phys_limit;
  84
  85         WARN_ON_ONCE(!PAGE_ALIGNED(size));
  86
  87         gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
  88                                            &phys_limit);
  89         page = dma_alloc_contiguous(dev, size, gfp);
  90         if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  91                 dma_free_contiguous(dev, page, size);
  92                 page = NULL;
  93         }
  94 again:
  95         if (!page)
  96                 page = alloc_pages_node(node, gfp, get_order(size));
  97         if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  98                 dma_free_contiguous(dev, page, size);
  99                 page = NULL;
 100
 101                 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
 102                     phys_limit < DMA_BIT_MASK(64) &&
 103                     !(gfp & (GFP_DMA32 | GFP_DMA))) {
 104                         gfp |= GFP_DMA32;
 105                         goto again;
 106                 }
 107
 108                 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
 109                         gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
 110                         goto again;
 111                 }
 112         }
 113
 114         return page;
 115 }
 116
 117 static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
 118                 dma_addr_t *dma_handle, gfp_t gfp)
 119 {
 120         struct page *page;
 121         u64 phys_mask;
 122         void *ret;
 123
 124         gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
 125                                            &phys_mask);
 126         page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
 127         if (!page)
 128                 return NULL;
 129         *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
 130         return ret;
 131 }
 132
 133 void *dma_direct_alloc(struct device *dev, size_t size,
 134                 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
 135 {
 136         struct page *page;
 137         void *ret;
 138         int err;
 139
 140         size = PAGE_ALIGN(size);
 141         if (attrs & DMA_ATTR_NO_WARN)
 142                 gfp |= __GFP_NOWARN;
 143
 144         if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
 145             !force_dma_unencrypted(dev)) {
 146                 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
 147                 if (!page)
 148                         return NULL;
 149                 /* remove any dirty cache lines on the kernel alias */
 150                 if (!PageHighMem(page))
 151                         arch_dma_prep_coherent(page, size);
 152                 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
 153                 /* return the page pointer as the opaque cookie */
 154                 return page;
 155         }
 156
 157         if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 158             !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 159             !dev_is_dma_coherent(dev))
 160                 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
 161
 162         /*
 163          * Remapping or decrypting memory may block. If either is required and
 164          * we can't block, allocate the memory from the atomic pools.
 165          */
 166         if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
 167             !gfpflags_allow_blocking(gfp) &&
 168             (force_dma_unencrypted(dev) ||
 169              (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
 170                 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
 171
 172         /* we always manually zero the memory once we are done */
 173         page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
 174         if (!page)
 175                 return NULL;
 176
 177         if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 178              !dev_is_dma_coherent(dev)) ||
 179             (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
 180                 /* remove any dirty cache lines on the kernel alias */
 181                 arch_dma_prep_coherent(page, size);
 182
 183                 /* create a coherent mapping */
 184                 ret = dma_common_contiguous_remap(page, size,
 185                                 dma_pgprot(dev, PAGE_KERNEL, attrs),
 186                                 __builtin_return_address(0));
 187                 if (!ret)
 188                         goto out_free_pages;
 189                 if (force_dma_unencrypted(dev)) {
 190                         err = set_memory_decrypted((unsigned long)ret,
 191                                                    PFN_UP(size));
 192                         if (err)
 193                                 goto out_free_pages;
 194                 }
 195                 memset(ret, 0, size);
 196                 goto done;
 197         }
 198
 199         if (PageHighMem(page)) {
 200                 /*
 201                  * Depending on the cma= arguments and per-arch setup
 202                  * dma_alloc_contiguous could return highmem pages.
 203                  * Without remapping there is no way to return them here,
 204                  * so log an error and fail.
 205                  */
 206                 dev_info(dev, "Rejecting highmem page from CMA.\n");
 207                 goto out_free_pages;
 208         }
 209
 210         ret = page_address(page);
 211         if (force_dma_unencrypted(dev)) {
 212                 err = set_memory_decrypted((unsigned long)ret,
 213                                            PFN_UP(size));
 214                 if (err)
 215                         goto out_free_pages;
 216         }
 217
 218         memset(ret, 0, size);
 219
 220         if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 221             !dev_is_dma_coherent(dev)) {
 222                 arch_dma_prep_coherent(page, size);
 223                 ret = arch_dma_set_uncached(ret, size);
 224                 if (IS_ERR(ret))
 225                         goto out_encrypt_pages;
 226         }
 227 done:
 228         *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
 229         return ret;
 230
 231 out_encrypt_pages:
 232         if (force_dma_unencrypted(dev)) {
 233                 err = set_memory_encrypted((unsigned long)page_address(page),
 234                                            PFN_UP(size));
 235                 /* If memory cannot be re-encrypted, it must be leaked */
 236                 if (err)
 237                         return NULL;
 238         }
 239 out_free_pages:
 240         dma_free_contiguous(dev, page, size);
 241         return NULL;
 242 }
 243
 244 void dma_direct_free(struct device *dev, size_t size,
 245                 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
 246 {
 247         if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
 248             !force_dma_unencrypted(dev)) {
 249                 /* cpu_addr is a struct page cookie, not a kernel address */
 250                 dma_free_contiguous(dev, cpu_addr, size);
 251                 return;
 252         }
 253
 254         if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 255             !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 256             !dev_is_dma_coherent(dev)) {
 257                 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
 258                 return;
 259         }
 260
 261         /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
 262         if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
 263             dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
 264                 return;
 265
 266         if (force_dma_unencrypted(dev))
 267                 set_memory_encrypted((unsigned long)cpu_addr, PFN_UP(size));
 268
 269         if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
 270                 vunmap(cpu_addr);
 271         else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
 272                 arch_dma_clear_uncached(cpu_addr, size);
 273
 274         dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
 275 }
 276
 277 struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
 278                 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
 279 {
 280         struct page *page;
 281         void *ret;
 282
 283         if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
 284             force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
 285                 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
 286
 287         page = __dma_direct_alloc_pages(dev, size, gfp);
 288         if (!page)
 289                 return NULL;
 290         if (PageHighMem(page)) {
 291                 /*
 292                  * Depending on the cma= arguments and per-arch setup
 293                  * dma_alloc_contiguous could return highmem pages.
 294                  * Without remapping there is no way to return them here,
 295                  * so log an error and fail.
 296                  */
 297                 dev_info(dev, "Rejecting highmem page from CMA.\n");
 298                 goto out_free_pages;
 299         }
 300
 301         ret = page_address(page);
 302         if (force_dma_unencrypted(dev)) {
 303                 if (set_memory_decrypted((unsigned long)ret, PFN_UP(size)))
 304                         goto out_free_pages;
 305         }
 306         memset(ret, 0, size);
 307         *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
 308         return page;
 309 out_free_pages:
 310         dma_free_contiguous(dev, page, size);
 311         return NULL;
 312 }
 313
 314 void dma_direct_free_pages(struct device *dev, size_t size,
 315                 struct page *page, dma_addr_t dma_addr,
 316                 enum dma_data_direction dir)
 317 {
 318         void *vaddr = page_address(page);
 319
 320         /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
 321         if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
 322             dma_free_from_pool(dev, vaddr, size))
 323                 return;
 324
 325         if (force_dma_unencrypted(dev))
 326                 set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
 327
 328         dma_free_contiguous(dev, page, size);
 329 }
 330
 331 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
 332     defined(CONFIG_SWIOTLB)
 333 void dma_direct_sync_sg_for_device(struct device *dev,
 334                 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
 335 {
 336         struct scatterlist *sg;
 337         int i;
 338
 339         for_each_sg(sgl, sg, nents, i) {
 340                 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
 341
 342                 if (unlikely(is_swiotlb_buffer(paddr)))
 343                         swiotlb_tbl_sync_single(dev, paddr, sg->length,
 344                                         dir, SYNC_FOR_DEVICE);
 345
 346                 if (!dev_is_dma_coherent(dev))
 347                         arch_sync_dma_for_device(paddr, sg->length,
 348                                         dir);
 349         }
 350 }
 351 #endif
 352
 353 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
 354     defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
 355     defined(CONFIG_SWIOTLB)
 356 void dma_direct_sync_sg_for_cpu(struct device *dev,
 357                 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
 358 {
 359         struct scatterlist *sg;
 360         int i;
 361
 362         for_each_sg(sgl, sg, nents, i) {
 363                 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
 364
 365                 if (!dev_is_dma_coherent(dev))
 366                         arch_sync_dma_for_cpu(paddr, sg->length, dir);
 367
 368                 if (unlikely(is_swiotlb_buffer(paddr)))
 369                         swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
 370                                         SYNC_FOR_CPU);
 371
 372                 if (dir == DMA_FROM_DEVICE)
 373                         arch_dma_mark_clean(paddr, sg->length);
 374         }
 375
 376         if (!dev_is_dma_coherent(dev))
 377                 arch_sync_dma_for_cpu_all();
 378 }
 379
 380 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
 381                 int nents, enum dma_data_direction dir, unsigned long attrs)
 382 {
 383         struct scatterlist *sg;
 384         int i;
 385
 386         for_each_sg(sgl, sg, nents, i)
 387                 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
 388                              attrs);
 389 }
 390 #endif
 391
 392 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 393                 enum dma_data_direction dir, unsigned long attrs)
 394 {
 395         int i;
 396         struct scatterlist *sg;
 397
 398         for_each_sg(sgl, sg, nents, i) {
 399                 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
 400                                 sg->offset, sg->length, dir, attrs);
 401                 if (sg->dma_address == DMA_MAPPING_ERROR)
 402                         goto out_unmap;
 403                 sg_dma_len(sg) = sg->length;
 404         }
 405
 406         return nents;
 407
 408 out_unmap:
 409         dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
 410         return 0;
 411 }
 412
 413 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
 414                 size_t size, enum dma_data_direction dir, unsigned long attrs)
 415 {
 416         dma_addr_t dma_addr = paddr;
 417
 418         if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
 419                 dev_err_once(dev,
 420                              "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
 421                              &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
 422                 WARN_ON_ONCE(1);
 423                 return DMA_MAPPING_ERROR;
 424         }
 425
 426         return dma_addr;
 427 }
 428
 429 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
 430                 void *cpu_addr, dma_addr_t dma_addr, size_t size,
 431                 unsigned long attrs)
 432 {
 433         struct page *page = dma_direct_to_page(dev, dma_addr);
 434         int ret;
 435
 436         ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
 437         if (!ret)
 438                 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
 439         return ret;
 440 }
 441
 442 bool dma_direct_can_mmap(struct device *dev)
 443 {
 444         return dev_is_dma_coherent(dev) ||
 445                 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
 446 }
 447
 448 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
 449                 void *cpu_addr, dma_addr_t dma_addr, size_t size,
 450                 unsigned long attrs)
 451 {
 452         unsigned long user_count = vma_pages(vma);
 453         unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 454         unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
 455         int ret = -ENXIO;
 456
 457         vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
 458
 459         if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
 460                 return ret;
 461
 462         if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
 463                 return -ENXIO;
 464         return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
 465                         user_count << PAGE_SHIFT, vma->vm_page_prot);
 466 }
 467
 468 int dma_direct_supported(struct device *dev, u64 mask)
 469 {
 470         u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
 471
 472         /*
 473          * Because 32-bit DMA masks are so common we expect every architecture
 474          * to be able to satisfy them - either by not supporting more physical
 475          * memory, or by providing a ZONE_DMA32.  If neither is the case, the
 476          * architecture needs to use an IOMMU instead of the direct mapping.
 477          */
 478         if (mask >= DMA_BIT_MASK(32))
 479                 return 1;
 480
 481         /*
 482          * This check needs to be against the actual bit mask value, so use
 483          * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
 484          * part of the check.
 485          */
 486         if (IS_ENABLED(CONFIG_ZONE_DMA))
 487                 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
 488         return mask >= phys_to_dma_unencrypted(dev, min_mask);
 489 }
 490
 491 size_t dma_direct_max_mapping_size(struct device *dev)
 492 {
 493         /* If SWIOTLB is active, use its maximum mapping size */
 494         if (is_swiotlb_active() &&
 495             (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
 496                 return swiotlb_max_mapping_size(dev);
 497         return SIZE_MAX;
 498 }
 499
 500 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
 501 {
 502         return !dev_is_dma_coherent(dev) ||
 503                 is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
 504 }
 505
 506 /**
 507  * dma_direct_set_offset - Assign scalar offset for a single DMA range.
 508  * @dev:        device pointer; needed to "own" the alloced memory.
 509  * @cpu_start:  beginning of memory region covered by this offset.
 510  * @dma_start:  beginning of DMA/PCI region covered by this offset.
 511  * @size:       size of the region.
 512  *
 513  * This is for the simple case of a uniform offset which cannot
 514  * be discovered by "dma-ranges".
 515  *
 516  * It returns -ENOMEM if out of memory, -EINVAL if a map
 517  * already exists, 0 otherwise.
 518  *
 519  * Note: any call to this from a driver is a bug.  The mapping needs
 520  * to be described by the device tree or other firmware interfaces.
 521  */
 522 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
 523                          dma_addr_t dma_start, u64 size)
 524 {
 525         struct bus_dma_region *map;
 526         u64 offset = (u64)cpu_start - (u64)dma_start;
 527
 528         if (dev->dma_range_map) {
 529                 dev_err(dev, "attempt to add DMA range to existing map\n");
 530                 return -EINVAL;
 531         }
 532
 533         if (!offset)
 534                 return 0;
 535
 536         map = kcalloc(2, sizeof(*map), GFP_KERNEL);
 537         if (!map)
 538                 return -ENOMEM;
 539         map[0].cpu_start = cpu_start;
 540         map[0].dma_start = dma_start;
 541         map[0].offset = offset;
 542         map[0].size = size;
 543         dev->dma_range_map = map;
 544         return 0;
 545 }
 546 EXPORT_SYMBOL_GPL(dma_direct_set_offset);