1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2020 Christoph Hellwig.
5 * DMA operations that map physical memory directly without using an IOMMU.
7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h>
10 #include <linux/dma-map-ops.h>
11 #include <linux/scatterlist.h>
12 #include <linux/pfn.h>
13 #include <linux/vmalloc.h>
14 #include <linux/set_memory.h>
15 #include <linux/slab.h>
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
20 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct to work properly.
23 unsigned int zone_dma_bits __ro_after_init = 24;
25 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
28 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted(dev, phys);
30 return phys_to_dma(dev, phys);
33 static inline struct page *dma_direct_to_page(struct device *dev,
36 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
39 u64 dma_direct_get_required_mask(struct device *dev)
41 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, phys);
44 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
47 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
50 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
53 * Optimistically try the zone that the physical address mask falls
54 * into first. If that returns memory that isn't actually addressable
55 * we will fallback to the next lower zone and try again.
57 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
60 *phys_limit = dma_to_phys(dev, dma_limit);
61 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
63 if (*phys_limit <= DMA_BIT_MASK(32))
68 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
70 dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
72 if (dma_addr == DMA_MAPPING_ERROR)
74 return dma_addr + size - 1 <=
75 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
78 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
81 int node = dev_to_node(dev);
82 struct page *page = NULL;
85 WARN_ON_ONCE(!PAGE_ALIGNED(size));
87 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
89 page = dma_alloc_contiguous(dev, size, gfp);
90 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
91 dma_free_contiguous(dev, page, size);
96 page = alloc_pages_node(node, gfp, get_order(size));
97 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
98 dma_free_contiguous(dev, page, size);
101 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
102 phys_limit < DMA_BIT_MASK(64) &&
103 !(gfp & (GFP_DMA32 | GFP_DMA))) {
108 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
109 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
117 static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
118 dma_addr_t *dma_handle, gfp_t gfp)
124 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
126 page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
129 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
133 void *dma_direct_alloc(struct device *dev, size_t size,
134 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
140 size = PAGE_ALIGN(size);
141 if (attrs & DMA_ATTR_NO_WARN)
144 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
145 !force_dma_unencrypted(dev)) {
146 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
149 /* remove any dirty cache lines on the kernel alias */
150 if (!PageHighMem(page))
151 arch_dma_prep_coherent(page, size);
152 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
153 /* return the page pointer as the opaque cookie */
157 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
158 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
159 !dev_is_dma_coherent(dev))
160 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
163 * Remapping or decrypting memory may block. If either is required and
164 * we can't block, allocate the memory from the atomic pools.
166 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
167 !gfpflags_allow_blocking(gfp) &&
168 (force_dma_unencrypted(dev) ||
169 (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
170 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
172 /* we always manually zero the memory once we are done */
173 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
177 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
178 !dev_is_dma_coherent(dev)) ||
179 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
180 /* remove any dirty cache lines on the kernel alias */
181 arch_dma_prep_coherent(page, size);
183 /* create a coherent mapping */
184 ret = dma_common_contiguous_remap(page, size,
185 dma_pgprot(dev, PAGE_KERNEL, attrs),
186 __builtin_return_address(0));
189 if (force_dma_unencrypted(dev)) {
190 err = set_memory_decrypted((unsigned long)ret,
195 memset(ret, 0, size);
199 if (PageHighMem(page)) {
201 * Depending on the cma= arguments and per-arch setup
202 * dma_alloc_contiguous could return highmem pages.
203 * Without remapping there is no way to return them here,
204 * so log an error and fail.
206 dev_info(dev, "Rejecting highmem page from CMA.\n");
210 ret = page_address(page);
211 if (force_dma_unencrypted(dev)) {
212 err = set_memory_decrypted((unsigned long)ret,
218 memset(ret, 0, size);
220 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
221 !dev_is_dma_coherent(dev)) {
222 arch_dma_prep_coherent(page, size);
223 ret = arch_dma_set_uncached(ret, size);
225 goto out_encrypt_pages;
228 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
232 if (force_dma_unencrypted(dev)) {
233 err = set_memory_encrypted((unsigned long)page_address(page),
235 /* If memory cannot be re-encrypted, it must be leaked */
240 dma_free_contiguous(dev, page, size);
244 void dma_direct_free(struct device *dev, size_t size,
245 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
247 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
248 !force_dma_unencrypted(dev)) {
249 /* cpu_addr is a struct page cookie, not a kernel address */
250 dma_free_contiguous(dev, cpu_addr, size);
254 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
255 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
256 !dev_is_dma_coherent(dev)) {
257 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
261 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
262 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
263 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
266 if (force_dma_unencrypted(dev))
267 set_memory_encrypted((unsigned long)cpu_addr, PFN_UP(size));
269 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
271 else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
272 arch_dma_clear_uncached(cpu_addr, size);
274 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
277 struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
278 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
283 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
284 force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
285 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
287 page = __dma_direct_alloc_pages(dev, size, gfp);
290 if (PageHighMem(page)) {
292 * Depending on the cma= arguments and per-arch setup
293 * dma_alloc_contiguous could return highmem pages.
294 * Without remapping there is no way to return them here,
295 * so log an error and fail.
297 dev_info(dev, "Rejecting highmem page from CMA.\n");
301 ret = page_address(page);
302 if (force_dma_unencrypted(dev)) {
303 if (set_memory_decrypted((unsigned long)ret, PFN_UP(size)))
306 memset(ret, 0, size);
307 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
310 dma_free_contiguous(dev, page, size);
314 void dma_direct_free_pages(struct device *dev, size_t size,
315 struct page *page, dma_addr_t dma_addr,
316 enum dma_data_direction dir)
318 void *vaddr = page_address(page);
320 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
321 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
322 dma_free_from_pool(dev, vaddr, size))
325 if (force_dma_unencrypted(dev))
326 set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
328 dma_free_contiguous(dev, page, size);
331 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
332 defined(CONFIG_SWIOTLB)
333 void dma_direct_sync_sg_for_device(struct device *dev,
334 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
336 struct scatterlist *sg;
339 for_each_sg(sgl, sg, nents, i) {
340 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
342 if (unlikely(is_swiotlb_buffer(paddr)))
343 swiotlb_tbl_sync_single(dev, paddr, sg->length,
344 dir, SYNC_FOR_DEVICE);
346 if (!dev_is_dma_coherent(dev))
347 arch_sync_dma_for_device(paddr, sg->length,
353 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
354 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
355 defined(CONFIG_SWIOTLB)
356 void dma_direct_sync_sg_for_cpu(struct device *dev,
357 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
359 struct scatterlist *sg;
362 for_each_sg(sgl, sg, nents, i) {
363 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
365 if (!dev_is_dma_coherent(dev))
366 arch_sync_dma_for_cpu(paddr, sg->length, dir);
368 if (unlikely(is_swiotlb_buffer(paddr)))
369 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
372 if (dir == DMA_FROM_DEVICE)
373 arch_dma_mark_clean(paddr, sg->length);
376 if (!dev_is_dma_coherent(dev))
377 arch_sync_dma_for_cpu_all();
380 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
381 int nents, enum dma_data_direction dir, unsigned long attrs)
383 struct scatterlist *sg;
386 for_each_sg(sgl, sg, nents, i)
387 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
392 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
393 enum dma_data_direction dir, unsigned long attrs)
396 struct scatterlist *sg;
398 for_each_sg(sgl, sg, nents, i) {
399 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
400 sg->offset, sg->length, dir, attrs);
401 if (sg->dma_address == DMA_MAPPING_ERROR)
403 sg_dma_len(sg) = sg->length;
409 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
413 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
414 size_t size, enum dma_data_direction dir, unsigned long attrs)
416 dma_addr_t dma_addr = paddr;
418 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
420 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
421 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
423 return DMA_MAPPING_ERROR;
429 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
430 void *cpu_addr, dma_addr_t dma_addr, size_t size,
433 struct page *page = dma_direct_to_page(dev, dma_addr);
436 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
438 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
442 bool dma_direct_can_mmap(struct device *dev)
444 return dev_is_dma_coherent(dev) ||
445 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
448 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
449 void *cpu_addr, dma_addr_t dma_addr, size_t size,
452 unsigned long user_count = vma_pages(vma);
453 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
454 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
457 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
459 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
462 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
464 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
465 user_count << PAGE_SHIFT, vma->vm_page_prot);
468 int dma_direct_supported(struct device *dev, u64 mask)
470 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
473 * Because 32-bit DMA masks are so common we expect every architecture
474 * to be able to satisfy them - either by not supporting more physical
475 * memory, or by providing a ZONE_DMA32. If neither is the case, the
476 * architecture needs to use an IOMMU instead of the direct mapping.
478 if (mask >= DMA_BIT_MASK(32))
482 * This check needs to be against the actual bit mask value, so use
483 * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
486 if (IS_ENABLED(CONFIG_ZONE_DMA))
487 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
488 return mask >= phys_to_dma_unencrypted(dev, min_mask);
491 size_t dma_direct_max_mapping_size(struct device *dev)
493 /* If SWIOTLB is active, use its maximum mapping size */
494 if (is_swiotlb_active() &&
495 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
496 return swiotlb_max_mapping_size(dev);
500 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
502 return !dev_is_dma_coherent(dev) ||
503 is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
507 * dma_direct_set_offset - Assign scalar offset for a single DMA range.
508 * @dev: device pointer; needed to "own" the alloced memory.
509 * @cpu_start: beginning of memory region covered by this offset.
510 * @dma_start: beginning of DMA/PCI region covered by this offset.
511 * @size: size of the region.
513 * This is for the simple case of a uniform offset which cannot
514 * be discovered by "dma-ranges".
516 * It returns -ENOMEM if out of memory, -EINVAL if a map
517 * already exists, 0 otherwise.
519 * Note: any call to this from a driver is a bug. The mapping needs
520 * to be described by the device tree or other firmware interfaces.
522 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
523 dma_addr_t dma_start, u64 size)
525 struct bus_dma_region *map;
526 u64 offset = (u64)cpu_start - (u64)dma_start;
528 if (dev->dma_range_map) {
529 dev_err(dev, "attempt to add DMA range to existing map\n");
536 map = kcalloc(2, sizeof(*map), GFP_KERNEL);
539 map[0].cpu_start = cpu_start;
540 map[0].dma_start = dma_start;
541 map[0].offset = offset;
543 dev->dma_range_map = map;
546 EXPORT_SYMBOL_GPL(dma_direct_set_offset);