1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 ARM Limited
7 #include <linux/init.h>
8 #include <linux/list.h>
9 #include <linux/perf_event.h>
10 #include <linux/sched.h>
11 #include <linux/slab.h>
12 #include <linux/sysctl.h>
13 #include <linux/uaccess.h>
15 #include <asm/cpufeature.h>
17 #include <asm/sysreg.h>
18 #include <asm/system_misc.h>
19 #include <asm/traps.h>
20 #include <asm/kprobes.h>
22 #define CREATE_TRACE_POINTS
23 #include "trace-events-emulation.h"
26 * The runtime support for deprecated instruction support can be in one of
27 * following three states -
30 * 1 = emulate (software emulation)
31 * 2 = hw (supported in hardware)
33 enum insn_emulation_mode {
39 enum legacy_insn_status {
44 struct insn_emulation_ops {
46 enum legacy_insn_status status;
47 struct undef_hook *hooks;
48 int (*set_hw_mode)(bool enable);
51 struct insn_emulation {
52 struct list_head node;
53 struct insn_emulation_ops *ops;
59 static LIST_HEAD(insn_emulation);
60 static int nr_insn_emulated __initdata;
61 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
62 static DEFINE_MUTEX(insn_emulation_mutex);
64 static void register_emulation_hooks(struct insn_emulation_ops *ops)
66 struct undef_hook *hook;
70 for (hook = ops->hooks; hook->instr_mask; hook++)
71 register_undef_hook(hook);
73 pr_notice("Registered %s emulation handler\n", ops->name);
76 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
78 struct undef_hook *hook;
82 for (hook = ops->hooks; hook->instr_mask; hook++)
83 unregister_undef_hook(hook);
85 pr_notice("Removed %s emulation handler\n", ops->name);
88 static void enable_insn_hw_mode(void *data)
90 struct insn_emulation *insn = (struct insn_emulation *)data;
91 if (insn->ops->set_hw_mode)
92 insn->ops->set_hw_mode(true);
95 static void disable_insn_hw_mode(void *data)
97 struct insn_emulation *insn = (struct insn_emulation *)data;
98 if (insn->ops->set_hw_mode)
99 insn->ops->set_hw_mode(false);
102 /* Run set_hw_mode(mode) on all active CPUs */
103 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
105 if (!insn->ops->set_hw_mode)
108 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
110 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
115 * Run set_hw_mode for all insns on a starting CPU.
117 * 0 - If all the hooks ran successfully.
118 * -EINVAL - At least one hook is not supported by the CPU.
120 static int run_all_insn_set_hw_mode(unsigned int cpu)
124 struct insn_emulation *insn;
126 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
127 list_for_each_entry(insn, &insn_emulation, node) {
128 bool enable = (insn->current_mode == INSN_HW);
129 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
130 pr_warn("CPU[%u] cannot support the emulation of %s",
131 cpu, insn->ops->name);
135 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
139 static int update_insn_emulation_mode(struct insn_emulation *insn,
140 enum insn_emulation_mode prev)
145 case INSN_UNDEF: /* Nothing to be done */
148 remove_emulation_hooks(insn->ops);
151 if (!run_all_cpu_set_hw_mode(insn, false))
152 pr_notice("Disabled %s support\n", insn->ops->name);
156 switch (insn->current_mode) {
160 register_emulation_hooks(insn->ops);
163 ret = run_all_cpu_set_hw_mode(insn, true);
165 pr_notice("Enabled %s support\n", insn->ops->name);
172 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
175 struct insn_emulation *insn;
177 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
182 insn->min = INSN_UNDEF;
184 switch (ops->status) {
185 case INSN_DEPRECATED:
186 insn->current_mode = INSN_EMULATE;
187 /* Disable the HW mode if it was turned on at early boot time */
188 run_all_cpu_set_hw_mode(insn, false);
192 insn->current_mode = INSN_UNDEF;
193 insn->max = INSN_EMULATE;
197 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
198 list_add(&insn->node, &insn_emulation);
200 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
202 /* Register any handlers if required */
203 update_insn_emulation_mode(insn, INSN_UNDEF);
206 static int emulation_proc_handler(struct ctl_table *table, int write,
207 void __user *buffer, size_t *lenp,
211 struct insn_emulation *insn;
212 enum insn_emulation_mode prev_mode;
214 mutex_lock(&insn_emulation_mutex);
215 insn = container_of(table->data, struct insn_emulation, current_mode);
216 prev_mode = insn->current_mode;
217 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
219 if (ret || !write || prev_mode == insn->current_mode)
222 ret = update_insn_emulation_mode(insn, prev_mode);
224 /* Mode change failed, revert to previous mode. */
225 insn->current_mode = prev_mode;
226 update_insn_emulation_mode(insn, INSN_UNDEF);
229 mutex_unlock(&insn_emulation_mutex);
233 static void __init register_insn_emulation_sysctl(void)
237 struct insn_emulation *insn;
238 struct ctl_table *insns_sysctl, *sysctl;
240 insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
245 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
246 list_for_each_entry(insn, &insn_emulation, node) {
247 sysctl = &insns_sysctl[i];
250 sysctl->maxlen = sizeof(int);
252 sysctl->procname = insn->ops->name;
253 sysctl->data = &insn->current_mode;
254 sysctl->extra1 = &insn->min;
255 sysctl->extra2 = &insn->max;
256 sysctl->proc_handler = emulation_proc_handler;
259 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
261 register_sysctl("abi", insns_sysctl);
265 * Implement emulation of the SWP/SWPB instructions using load-exclusive and
268 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
269 * Where: Rt = destination
275 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
278 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
279 #define __SWP_LL_SC_LOOPS 4
281 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
284 __asm__ __volatile__( \
286 "0: ldxr"B" %w2, [%4]\n" \
287 "1: stxr"B" %w0, %w1, [%4]\n" \
289 " sub %w3, %w3, #1\n" \
296 " .pushsection .fixup,\"ax\"\n" \
298 "4: mov %w0, %w6\n" \
301 _ASM_EXTABLE(0b, 4b) \
302 _ASM_EXTABLE(1b, 4b) \
303 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
304 : "r" ((unsigned long)addr), "i" (-EAGAIN), \
306 "i" (__SWP_LL_SC_LOOPS) \
311 #define __user_swp_asm(data, addr, res, temp, temp2) \
312 __user_swpX_asm(data, addr, res, temp, temp2, "")
313 #define __user_swpb_asm(data, addr, res, temp, temp2) \
314 __user_swpX_asm(data, addr, res, temp, temp2, "b")
317 * Bit 22 of the instruction encoding distinguishes between
318 * the SWP and SWPB variants (bit set means SWPB).
320 #define TYPE_SWPB (1 << 22)
322 static int emulate_swpX(unsigned int address, unsigned int *data,
325 unsigned int res = 0;
327 if ((type != TYPE_SWPB) && (address & 0x3)) {
328 /* SWP to unaligned address not permitted */
329 pr_debug("SWP instruction on unaligned pointer!\n");
334 unsigned long temp, temp2;
336 if (type == TYPE_SWPB)
337 __user_swpb_asm(*data, address, res, temp, temp2);
339 __user_swp_asm(*data, address, res, temp, temp2);
341 if (likely(res != -EAGAIN) || signal_pending(current))
350 #define ARM_OPCODE_CONDTEST_FAIL 0
351 #define ARM_OPCODE_CONDTEST_PASS 1
352 #define ARM_OPCODE_CONDTEST_UNCOND 2
354 #define ARM_OPCODE_CONDITION_UNCOND 0xf
356 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
358 u32 cc_bits = opcode >> 28;
360 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
361 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
362 return ARM_OPCODE_CONDTEST_PASS;
364 return ARM_OPCODE_CONDTEST_FAIL;
366 return ARM_OPCODE_CONDTEST_UNCOND;
370 * swp_handler logs the id of calling process, dissects the instruction, sanity
371 * checks the memory location, calls emulate_swpX for the actual operation and
372 * deals with fixup/error handling before returning
374 static int swp_handler(struct pt_regs *regs, u32 instr)
376 u32 destreg, data, type, address = 0;
377 const void __user *user_ptr;
378 int rn, rt2, res = 0;
380 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
382 type = instr & TYPE_SWPB;
384 switch (aarch32_check_condition(instr, regs->pstate)) {
385 case ARM_OPCODE_CONDTEST_PASS:
387 case ARM_OPCODE_CONDTEST_FAIL:
388 /* Condition failed - return to next instruction */
390 case ARM_OPCODE_CONDTEST_UNCOND:
391 /* If unconditional encoding - not a SWP, undef */
397 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
398 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
400 address = (u32)regs->user_regs.regs[rn];
401 data = (u32)regs->user_regs.regs[rt2];
402 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
404 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
405 rn, address, destreg,
406 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
408 /* Check access in reasonable access range for both SWP and SWPB */
409 user_ptr = (const void __user *)(unsigned long)(address & ~3);
410 if (!access_ok(user_ptr, 4)) {
411 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
416 res = emulate_swpX(address, &data, type);
420 regs->user_regs.regs[destreg] = data;
423 if (type == TYPE_SWPB)
424 trace_instruction_emulation("swpb", regs->pc);
426 trace_instruction_emulation("swp", regs->pc);
428 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
429 current->comm, (unsigned long)current->pid, regs->pc);
431 arm64_skip_faulting_instruction(regs, 4);
435 pr_debug("SWP{B} emulation: access caused memory abort!\n");
436 arm64_notify_segfault(address);
442 * Only emulate SWP/SWPB executed in ARM state/User mode.
443 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
445 static struct undef_hook swp_hooks[] = {
447 .instr_mask = 0x0fb00ff0,
448 .instr_val = 0x01000090,
449 .pstate_mask = PSR_AA32_MODE_MASK,
450 .pstate_val = PSR_AA32_MODE_USR,
456 static struct insn_emulation_ops swp_ops = {
458 .status = INSN_OBSOLETE,
463 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
465 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
467 switch (aarch32_check_condition(instr, regs->pstate)) {
468 case ARM_OPCODE_CONDTEST_PASS:
470 case ARM_OPCODE_CONDTEST_FAIL:
471 /* Condition failed - return to next instruction */
473 case ARM_OPCODE_CONDTEST_UNCOND:
474 /* If unconditional encoding - not a barrier instruction */
480 switch (aarch32_insn_mcr_extract_crm(instr)) {
483 * dmb - mcr p15, 0, Rt, c7, c10, 5
484 * dsb - mcr p15, 0, Rt, c7, c10, 4
486 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
488 trace_instruction_emulation(
489 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
492 trace_instruction_emulation(
493 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
498 * isb - mcr p15, 0, Rt, c7, c5, 4
500 * Taking an exception or returning from one acts as an
501 * instruction barrier. So no explicit barrier needed here.
503 trace_instruction_emulation(
504 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
509 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
510 current->comm, (unsigned long)current->pid, regs->pc);
512 arm64_skip_faulting_instruction(regs, 4);
516 static int cp15_barrier_set_hw_mode(bool enable)
519 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
521 sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
525 static struct undef_hook cp15_barrier_hooks[] = {
527 .instr_mask = 0x0fff0fdf,
528 .instr_val = 0x0e070f9a,
529 .pstate_mask = PSR_AA32_MODE_MASK,
530 .pstate_val = PSR_AA32_MODE_USR,
531 .fn = cp15barrier_handler,
534 .instr_mask = 0x0fff0fff,
535 .instr_val = 0x0e070f95,
536 .pstate_mask = PSR_AA32_MODE_MASK,
537 .pstate_val = PSR_AA32_MODE_USR,
538 .fn = cp15barrier_handler,
543 static struct insn_emulation_ops cp15_barrier_ops = {
544 .name = "cp15_barrier",
545 .status = INSN_DEPRECATED,
546 .hooks = cp15_barrier_hooks,
547 .set_hw_mode = cp15_barrier_set_hw_mode,
550 static int setend_set_hw_mode(bool enable)
552 if (!cpu_supports_mixed_endian_el0())
556 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
558 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
562 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
566 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
570 regs->pstate |= PSR_AA32_E_BIT;
573 regs->pstate &= ~PSR_AA32_E_BIT;
576 trace_instruction_emulation(insn, regs->pc);
577 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
578 current->comm, (unsigned long)current->pid, regs->pc);
583 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
585 int rc = compat_setend_handler(regs, (instr >> 9) & 1);
586 arm64_skip_faulting_instruction(regs, 4);
590 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
592 int rc = compat_setend_handler(regs, (instr >> 3) & 1);
593 arm64_skip_faulting_instruction(regs, 2);
597 static struct undef_hook setend_hooks[] = {
599 .instr_mask = 0xfffffdff,
600 .instr_val = 0xf1010000,
601 .pstate_mask = PSR_AA32_MODE_MASK,
602 .pstate_val = PSR_AA32_MODE_USR,
603 .fn = a32_setend_handler,
607 .instr_mask = 0xfffffff7,
608 .instr_val = 0x0000b650,
609 .pstate_mask = (PSR_AA32_T_BIT | PSR_AA32_MODE_MASK),
610 .pstate_val = (PSR_AA32_T_BIT | PSR_AA32_MODE_USR),
611 .fn = t16_setend_handler,
616 static struct insn_emulation_ops setend_ops = {
618 .status = INSN_DEPRECATED,
619 .hooks = setend_hooks,
620 .set_hw_mode = setend_set_hw_mode,
624 * Invoked as late_initcall, since not needed before init spawned.
626 static int __init armv8_deprecated_init(void)
628 if (IS_ENABLED(CONFIG_SWP_EMULATION))
629 register_insn_emulation(&swp_ops);
631 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
632 register_insn_emulation(&cp15_barrier_ops);
634 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
635 if(system_supports_mixed_endian_el0())
636 register_insn_emulation(&setend_ops);
638 pr_info("setend instruction emulation is not supported on this system\n");
641 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
642 "arm64/isndep:starting",
643 run_all_insn_set_hw_mode, NULL);
644 register_insn_emulation_sysctl();
649 core_initcall(armv8_deprecated_init);