1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel KeemBay Platform driver
5 * Copyright (C) 2020 Intel Corporation.
9 #ifndef KMB_PLATFORM_H_
10 #define KMB_PLATFORM_H_
12 #include <linux/bits.h>
13 #include <linux/bitfield.h>
14 #include <linux/types.h>
16 /* Register values with reference to KMB databook v1.1 */
17 /* common register for all channel */
26 /* Interrupt status register fields */
27 #define ISR_TXFO BIT(5)
28 #define ISR_TXFE BIT(4)
29 #define ISR_RXFO BIT(1)
30 #define ISR_RXDA BIT(0)
32 /* I2S Tx Rx Registers for all channels */
33 #define LRBR_LTHR(x) (0x40 * (x) + 0x020)
34 #define RRBR_RTHR(x) (0x40 * (x) + 0x024)
35 #define RER(x) (0x40 * (x) + 0x028)
36 #define TER(x) (0x40 * (x) + 0x02C)
37 #define RCR(x) (0x40 * (x) + 0x030)
38 #define TCR(x) (0x40 * (x) + 0x034)
39 #define ISR(x) (0x40 * (x) + 0x038)
40 #define IMR(x) (0x40 * (x) + 0x03C)
41 #define ROR(x) (0x40 * (x) + 0x040)
42 #define TOR(x) (0x40 * (x) + 0x044)
43 #define RFCR(x) (0x40 * (x) + 0x048)
44 #define TFCR(x) (0x40 * (x) + 0x04C)
45 #define RFF(x) (0x40 * (x) + 0x050)
46 #define TFF(x) (0x40 * (x) + 0x054)
48 /* I2S COMP Registers */
49 #define I2S_COMP_PARAM_2 0x01F0
50 #define I2S_COMP_PARAM_1 0x01F4
51 #define I2S_COMP_VERSION 0x01F8
52 #define I2S_COMP_TYPE 0x01FC
54 /* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */
55 #define I2S_GEN_CFG_0 0x000
56 #define PSS_CPR_RST_EN 0x010
57 #define PSS_CPR_RST_SET 0x014
58 #define PSS_CPR_CLK_CLR 0x000
59 #define PSS_CPR_AUX_RST_EN 0x070
61 #define MASTER_MODE BIT(13)
64 #define TX_INT_FLAG GENMASK(5, 4)
65 #define RX_INT_FLAG GENMASK(1, 0)
67 * Component parameter register fields - define the I2S block's
70 #define COMP1_TX_WORDSIZE_3(r) FIELD_GET(GENMASK(27, 25), (r))
71 #define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r))
72 #define COMP1_TX_WORDSIZE_1(r) FIELD_GET(GENMASK(21, 19), (r))
73 #define COMP1_TX_WORDSIZE_0(r) FIELD_GET(GENMASK(18, 16), (r))
74 #define COMP1_RX_ENABLED(r) FIELD_GET(BIT(6), (r))
75 #define COMP1_TX_ENABLED(r) FIELD_GET(BIT(5), (r))
76 #define COMP1_MODE_EN(r) FIELD_GET(BIT(4), (r))
77 #define COMP1_APB_DATA_WIDTH(r) FIELD_GET(GENMASK(1, 0), (r))
78 #define COMP2_RX_WORDSIZE_3(r) FIELD_GET(GENMASK(12, 10), (r))
79 #define COMP2_RX_WORDSIZE_2(r) FIELD_GET(GENMASK(9, 7), (r))
80 #define COMP2_RX_WORDSIZE_1(r) FIELD_GET(GENMASK(5, 3), (r))
81 #define COMP2_RX_WORDSIZE_0(r) FIELD_GET(GENMASK(2, 0), (r))
83 /* Add 1 to the below registers to indicate the actual size */
84 #define COMP1_TX_CHANNELS(r) (FIELD_GET(GENMASK(10, 9), (r)) + 1)
85 #define COMP1_RX_CHANNELS(r) (FIELD_GET(GENMASK(8, 7), (r)) + 1)
86 #define COMP1_FIFO_DEPTH(r) (FIELD_GET(GENMASK(3, 2), (r)) + 1)
88 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
89 #define COMP_MAX_WORDSIZE 8 /* 3 bits register width */
91 #define MAX_CHANNEL_NUM 8
92 #define MIN_CHANNEL_NUM 2
95 #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */
96 #define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */
97 #define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */
98 #define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */
100 #define DWC_I2S_PLAY BIT(0)
101 #define DWC_I2S_RECORD BIT(1)
102 #define DW_I2S_SLAVE BIT(2)
103 #define DW_I2S_MASTER BIT(3)
105 #define I2S_RXDMA 0x01C0
106 #define I2S_TXDMA 0x01C8
109 * struct i2s_clk_config_data - represent i2s clk configuration data
110 * @chan_nr: number of channel
111 * @data_width: number of bits per sample (8/16/24/32 bit)
112 * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz)
114 struct i2s_clk_config_data {
120 struct kmb_i2s_info {
121 void __iomem *i2s_base;
122 void __iomem *pss_base;
126 unsigned int capability;
127 unsigned int i2s_reg_comp1;
128 unsigned int i2s_reg_comp2;
135 struct i2s_clk_config_data config;
136 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
138 /* data related to PIO transfers */
140 struct snd_pcm_substream *tx_substream;
141 struct snd_pcm_substream *rx_substream;
146 #endif /* KMB_PLATFORM_H_ */