2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
17 * This is shared code between Digi's CVS archive and the
18 * Linux Kernel sources.
19 * Changing the source just for reformatting needlessly breaks
20 * our CVS diff history.
22 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
27 #include <linux/delay.h> /* For udelay */
28 #include <linux/io.h> /* For read[bwl]/write[bwl] */
29 #include <linux/serial.h> /* For struct async_serial */
30 #include <linux/serial_reg.h> /* For the various UART offsets */
31 #include <linux/pci.h>
32 #include <linux/tty.h>
34 #include "jsm.h" /* Driver main header file */
61 static void cls_set_cts_flow_control(struct jsm_channel *ch)
63 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
64 u8 ier = readb(&ch->ch_cls_uart->ier);
68 * The Enhanced Register Set may only be accessed when
69 * the Line Control Register is set to 0xBFh.
71 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
73 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
75 /* Turn on CTS flow control, turn off IXON flow control */
76 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
77 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
79 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
81 /* Write old LCR value back out, which turns enhanced access off */
82 writeb(lcrb, &ch->ch_cls_uart->lcr);
85 * Enable interrupts for CTS flow, turn off interrupts for
88 ier |= (UART_EXAR654_IER_CTSDSR);
89 ier &= ~(UART_EXAR654_IER_XOFF);
90 writeb(ier, &ch->ch_cls_uart->ier);
92 /* Set the usual FIFO values */
93 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
95 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
96 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
97 &ch->ch_cls_uart->isr_fcr);
102 static void cls_set_ixon_flow_control(struct jsm_channel *ch)
104 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
105 u8 ier = readb(&ch->ch_cls_uart->ier);
109 * The Enhanced Register Set may only be accessed when
110 * the Line Control Register is set to 0xBFh.
112 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
114 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
116 /* Turn on IXON flow control, turn off CTS flow control */
117 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
118 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
120 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
122 /* Now set our current start/stop chars while in enhanced mode */
123 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
124 writeb(0, &ch->ch_cls_uart->lsr);
125 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
126 writeb(0, &ch->ch_cls_uart->spr);
128 /* Write old LCR value back out, which turns enhanced access off */
129 writeb(lcrb, &ch->ch_cls_uart->lcr);
132 * Disable interrupts for CTS flow, turn on interrupts for
133 * received XOFF chars
135 ier &= ~(UART_EXAR654_IER_CTSDSR);
136 ier |= (UART_EXAR654_IER_XOFF);
137 writeb(ier, &ch->ch_cls_uart->ier);
139 /* Set the usual FIFO values */
140 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
142 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
143 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
144 &ch->ch_cls_uart->isr_fcr);
147 static void cls_set_no_output_flow_control(struct jsm_channel *ch)
149 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
150 u8 ier = readb(&ch->ch_cls_uart->ier);
154 * The Enhanced Register Set may only be accessed when
155 * the Line Control Register is set to 0xBFh.
157 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
159 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
161 /* Turn off IXON flow control, turn off CTS flow control */
162 isr_fcr |= (UART_EXAR654_EFR_ECB);
163 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
165 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
167 /* Write old LCR value back out, which turns enhanced access off */
168 writeb(lcrb, &ch->ch_cls_uart->lcr);
171 * Disable interrupts for CTS flow, turn off interrupts for
172 * received XOFF chars
174 ier &= ~(UART_EXAR654_IER_CTSDSR);
175 ier &= ~(UART_EXAR654_IER_XOFF);
176 writeb(ier, &ch->ch_cls_uart->ier);
178 /* Set the usual FIFO values */
179 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
181 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
182 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
183 &ch->ch_cls_uart->isr_fcr);
185 ch->ch_r_watermark = 0;
186 ch->ch_t_tlevel = 16;
187 ch->ch_r_tlevel = 16;
190 static void cls_set_rts_flow_control(struct jsm_channel *ch)
192 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
193 u8 ier = readb(&ch->ch_cls_uart->ier);
197 * The Enhanced Register Set may only be accessed when
198 * the Line Control Register is set to 0xBFh.
200 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
202 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
204 /* Turn on RTS flow control, turn off IXOFF flow control */
205 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
206 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
208 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
210 /* Write old LCR value back out, which turns enhanced access off */
211 writeb(lcrb, &ch->ch_cls_uart->lcr);
213 /* Enable interrupts for RTS flow */
214 ier |= (UART_EXAR654_IER_RTSDTR);
215 writeb(ier, &ch->ch_cls_uart->ier);
217 /* Set the usual FIFO values */
218 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
220 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
221 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
222 &ch->ch_cls_uart->isr_fcr);
224 ch->ch_r_watermark = 4;
228 static void cls_set_ixoff_flow_control(struct jsm_channel *ch)
230 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
231 u8 ier = readb(&ch->ch_cls_uart->ier);
235 * The Enhanced Register Set may only be accessed when
236 * the Line Control Register is set to 0xBFh.
238 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
240 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
242 /* Turn on IXOFF flow control, turn off RTS flow control */
243 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
244 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
246 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
248 /* Now set our current start/stop chars while in enhanced mode */
249 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
250 writeb(0, &ch->ch_cls_uart->lsr);
251 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
252 writeb(0, &ch->ch_cls_uart->spr);
254 /* Write old LCR value back out, which turns enhanced access off */
255 writeb(lcrb, &ch->ch_cls_uart->lcr);
257 /* Disable interrupts for RTS flow */
258 ier &= ~(UART_EXAR654_IER_RTSDTR);
259 writeb(ier, &ch->ch_cls_uart->ier);
261 /* Set the usual FIFO values */
262 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
264 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
265 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
266 &ch->ch_cls_uart->isr_fcr);
269 static void cls_set_no_input_flow_control(struct jsm_channel *ch)
271 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
272 u8 ier = readb(&ch->ch_cls_uart->ier);
276 * The Enhanced Register Set may only be accessed when
277 * the Line Control Register is set to 0xBFh.
279 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
281 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
283 /* Turn off IXOFF flow control, turn off RTS flow control */
284 isr_fcr |= (UART_EXAR654_EFR_ECB);
285 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
287 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
289 /* Write old LCR value back out, which turns enhanced access off */
290 writeb(lcrb, &ch->ch_cls_uart->lcr);
292 /* Disable interrupts for RTS flow */
293 ier &= ~(UART_EXAR654_IER_RTSDTR);
294 writeb(ier, &ch->ch_cls_uart->ier);
296 /* Set the usual FIFO values */
297 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
299 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
300 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
301 &ch->ch_cls_uart->isr_fcr);
303 ch->ch_t_tlevel = 16;
304 ch->ch_r_tlevel = 16;
309 * Determines whether its time to shut off break condition.
311 * No locks are assumed to be held when calling this function.
312 * channel lock is held and released in this function.
314 static void cls_clear_break(struct jsm_channel *ch)
316 unsigned long lock_flags;
318 spin_lock_irqsave(&ch->ch_lock, lock_flags);
320 /* Turn break off, and unset some variables */
321 if (ch->ch_flags & CH_BREAK_SENDING) {
322 u8 temp = readb(&ch->ch_cls_uart->lcr);
324 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
326 ch->ch_flags &= ~(CH_BREAK_SENDING);
327 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
328 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
331 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
334 static void cls_disable_receiver(struct jsm_channel *ch)
336 u8 tmp = readb(&ch->ch_cls_uart->ier);
338 tmp &= ~(UART_IER_RDI);
339 writeb(tmp, &ch->ch_cls_uart->ier);
342 static void cls_enable_receiver(struct jsm_channel *ch)
344 u8 tmp = readb(&ch->ch_cls_uart->ier);
346 tmp |= (UART_IER_RDI);
347 writeb(tmp, &ch->ch_cls_uart->ier);
350 /* Make the UART raise any of the output signals we want up */
351 static void cls_assert_modem_signals(struct jsm_channel *ch)
356 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);
359 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch)
371 spin_lock_irqsave(&ch->ch_lock, flags);
373 /* cache head and tail of queue */
374 head = ch->ch_r_head & RQUEUEMASK;
375 tail = ch->ch_r_tail & RQUEUEMASK;
377 /* Get our cached LSR */
378 linestatus = ch->ch_cached_lsr;
379 ch->ch_cached_lsr = 0;
381 /* Store how much space we have left in the queue */
382 qleft = tail - head - 1;
384 qleft += RQUEUEMASK + 1;
387 * Create a mask to determine whether we should
388 * insert the character (if any) into our queue.
390 if (ch->ch_c_iflag & IGNBRK)
391 error_mask |= UART_LSR_BI;
395 * Grab the linestatus register, we need to
396 * check to see if there is any data to read
398 linestatus = readb(&ch->ch_cls_uart->lsr);
400 /* Break out if there is no data to fetch */
401 if (!(linestatus & UART_LSR_DR))
405 * Discard character if we are ignoring the error mask
406 * which in this case is the break signal.
408 if (linestatus & error_mask) {
412 discard = readb(&ch->ch_cls_uart->txrx);
417 * If our queue is full, we have no choice but to drop some
418 * data. The assumption is that HWFLOW or SWFLOW should have
419 * stopped things way way before we got to this point.
421 * I decided that I wanted to ditch the oldest data first,
422 * I hope thats okay with everyone? Yes? Good.
425 tail = (tail + 1) & RQUEUEMASK;
426 ch->ch_r_tail = tail;
427 ch->ch_err_overrun++;
431 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
433 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
437 if (ch->ch_equeue[head] & UART_LSR_PE)
439 if (ch->ch_equeue[head] & UART_LSR_BI)
441 if (ch->ch_equeue[head] & UART_LSR_FE)
444 /* Add to, and flip head if needed */
445 head = (head + 1) & RQUEUEMASK;
450 * Write new final heads to channel structure.
452 ch->ch_r_head = head & RQUEUEMASK;
453 ch->ch_e_head = head & EQUEUEMASK;
455 spin_unlock_irqrestore(&ch->ch_lock, flags);
458 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch)
464 struct circ_buf *circ;
469 circ = &ch->uart_port.state->xmit;
471 /* No data to write to the UART */
472 if (uart_circ_empty(circ))
475 /* If port is "stopped", don't send any data to the UART */
476 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
479 /* We have to do it this way, because of the EXAR TXFIFO count bug. */
480 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
485 /* cache tail of queue */
486 tail = circ->tail & (UART_XMIT_SIZE - 1);
487 qlen = uart_circ_chars_pending(circ);
489 /* Find minimum of the FIFO space, versus queue length */
493 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx);
494 tail = (tail + 1) & (UART_XMIT_SIZE - 1);
500 /* Update the final tail */
501 circ->tail = tail & (UART_XMIT_SIZE - 1);
503 if (len_written > ch->ch_t_tlevel)
504 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
506 if (uart_circ_empty(circ))
507 uart_write_wakeup(&ch->uart_port);
510 static void cls_parse_modem(struct jsm_channel *ch, u8 signals)
512 u8 msignals = signals;
514 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
515 "neo_parse_modem: port: %d msignals: %x\n",
516 ch->ch_portnum, msignals);
519 * Scrub off lower bits.
520 * They signify delta's, which I don't care about
521 * Keep DDCD and DDSR though
525 if (msignals & UART_MSR_DDCD)
526 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
527 if (msignals & UART_MSR_DDSR)
528 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);
530 if (msignals & UART_MSR_DCD)
531 ch->ch_mistat |= UART_MSR_DCD;
533 ch->ch_mistat &= ~UART_MSR_DCD;
535 if (msignals & UART_MSR_DSR)
536 ch->ch_mistat |= UART_MSR_DSR;
538 ch->ch_mistat &= ~UART_MSR_DSR;
540 if (msignals & UART_MSR_RI)
541 ch->ch_mistat |= UART_MSR_RI;
543 ch->ch_mistat &= ~UART_MSR_RI;
545 if (msignals & UART_MSR_CTS)
546 ch->ch_mistat |= UART_MSR_CTS;
548 ch->ch_mistat &= ~UART_MSR_CTS;
550 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
551 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
553 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
554 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
555 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
556 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
557 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
558 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
561 /* Parse the ISR register for the specific port */
562 static inline void cls_parse_isr(struct jsm_board *brd, uint port)
564 struct jsm_channel *ch;
569 * No need to verify board pointer, it was already
570 * verified in the interrupt routine.
573 if (port >= brd->nasync)
576 ch = brd->channels[port];
580 /* Here we try to figure out what caused the interrupt to happen */
582 isr = readb(&ch->ch_cls_uart->isr_fcr);
584 /* Bail if no pending interrupt on port */
585 if (isr & UART_IIR_NO_INT)
588 /* Receive Interrupt pending */
589 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
590 /* Read data from uart -> queue */
591 cls_copy_data_from_uart_to_queue(ch);
592 jsm_check_queue_flow_control(ch);
595 /* Transmit Hold register empty pending */
596 if (isr & UART_IIR_THRI) {
597 /* Transfer data (if any) from Write Queue -> UART. */
598 spin_lock_irqsave(&ch->ch_lock, flags);
599 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
600 spin_unlock_irqrestore(&ch->ch_lock, flags);
601 cls_copy_data_from_queue_to_uart(ch);
605 * CTS/RTS change of state:
606 * Don't need to do anything, the cls_parse_modem
607 * below will grab the updated modem signals.
610 /* Parse any modem signal changes */
611 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
615 /* Channel lock MUST be held before calling this function! */
616 static void cls_flush_uart_write(struct jsm_channel *ch)
624 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
625 &ch->ch_cls_uart->isr_fcr);
627 for (i = 0; i < 10; i++) {
628 /* Check to see if the UART feels it completely flushed FIFO */
629 tmp = readb(&ch->ch_cls_uart->isr_fcr);
630 if (tmp & UART_FCR_CLEAR_XMIT) {
631 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
632 "Still flushing TX UART... i: %d\n", i);
638 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
641 /* Channel lock MUST be held before calling this function! */
642 static void cls_flush_uart_read(struct jsm_channel *ch)
648 * For complete POSIX compatibility, we should be purging the
649 * read FIFO in the UART here.
651 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
652 * incorrectly flushes write data as well as just basically trashing the
655 * Presumably, this is a bug in this UART.
661 static void cls_send_start_character(struct jsm_channel *ch)
666 if (ch->ch_startc != __DISABLED_CHAR) {
668 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
672 static void cls_send_stop_character(struct jsm_channel *ch)
677 if (ch->ch_stopc != __DISABLED_CHAR) {
679 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
685 * Send any/all changes to the line to the UART.
687 static void cls_param(struct jsm_channel *ch)
694 struct jsm_board *bd;
703 * If baud rate is zero, flush queues, and set mval to drop DTR.
705 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
711 cls_flush_uart_write(ch);
712 cls_flush_uart_read(ch);
714 /* The baudrate is B0 so all modem lines are to be dropped. */
715 ch->ch_flags |= (CH_BAUD0);
716 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
717 cls_assert_modem_signals(ch);
721 cflag = C_BAUD(ch->uart_port.state->port.tty);
723 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
724 if (baud_rates[i].cflag == cflag) {
725 baud = baud_rates[i].rate;
730 if (ch->ch_flags & CH_BAUD0)
731 ch->ch_flags &= ~(CH_BAUD0);
733 if (ch->ch_c_cflag & PARENB)
734 lcr |= UART_LCR_PARITY;
736 if (!(ch->ch_c_cflag & PARODD))
737 lcr |= UART_LCR_EPAR;
740 * Not all platforms support mark/space parity,
741 * so this will hide behind an ifdef.
744 if (ch->ch_c_cflag & CMSPAR)
745 lcr |= UART_LCR_SPAR;
748 if (ch->ch_c_cflag & CSTOPB)
749 lcr |= UART_LCR_STOP;
751 switch (ch->ch_c_cflag & CSIZE) {
753 lcr |= UART_LCR_WLEN5;
756 lcr |= UART_LCR_WLEN6;
759 lcr |= UART_LCR_WLEN7;
763 lcr |= UART_LCR_WLEN8;
767 ier = readb(&ch->ch_cls_uart->ier);
768 uart_lcr = readb(&ch->ch_cls_uart->lcr);
770 quot = ch->ch_bd->bd_dividend / baud;
773 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
774 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
775 writeb((quot >> 8), &ch->ch_cls_uart->ier);
776 writeb(lcr, &ch->ch_cls_uart->lcr);
780 writeb(lcr, &ch->ch_cls_uart->lcr);
782 if (ch->ch_c_cflag & CREAD)
783 ier |= (UART_IER_RDI | UART_IER_RLSI);
785 ier |= (UART_IER_THRI | UART_IER_MSI);
787 writeb(ier, &ch->ch_cls_uart->ier);
789 if (ch->ch_c_cflag & CRTSCTS)
790 cls_set_cts_flow_control(ch);
791 else if (ch->ch_c_iflag & IXON) {
793 * If start/stop is set to disable,
794 * then we should disable flow control.
796 if ((ch->ch_startc == __DISABLED_CHAR) ||
797 (ch->ch_stopc == __DISABLED_CHAR))
798 cls_set_no_output_flow_control(ch);
800 cls_set_ixon_flow_control(ch);
802 cls_set_no_output_flow_control(ch);
804 if (ch->ch_c_cflag & CRTSCTS)
805 cls_set_rts_flow_control(ch);
806 else if (ch->ch_c_iflag & IXOFF) {
808 * If start/stop is set to disable,
809 * then we should disable flow control.
811 if ((ch->ch_startc == __DISABLED_CHAR) ||
812 (ch->ch_stopc == __DISABLED_CHAR))
813 cls_set_no_input_flow_control(ch);
815 cls_set_ixoff_flow_control(ch);
817 cls_set_no_input_flow_control(ch);
819 cls_assert_modem_signals(ch);
821 /* get current status of the modem signals now */
822 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
828 * Classic specific interrupt handler.
830 static irqreturn_t cls_intr(int irq, void *voidbrd)
832 struct jsm_board *brd = voidbrd;
833 unsigned long lock_flags;
834 unsigned char uart_poll;
837 /* Lock out the slow poller from running on this board. */
838 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
841 * Check the board's global interrupt offset to see if we
842 * acctually do have an interrupt pending on us.
844 uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
846 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
847 __FILE__, __LINE__, uart_poll);
850 jsm_dbg(INTR, &brd->pci_dev,
851 "Kernel interrupted to me, but no pending interrupts...\n");
852 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
856 /* At this point, we have at least SOMETHING to service, dig further. */
858 /* Parse each port to find out what caused the interrupt */
859 for (i = 0; i < brd->nasync; i++)
860 cls_parse_isr(brd, i);
862 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
868 static void cls_uart_init(struct jsm_channel *ch)
870 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
871 unsigned char isr_fcr = 0;
873 writeb(0, &ch->ch_cls_uart->ier);
876 * The Enhanced Register Set may only be accessed when
877 * the Line Control Register is set to 0xBFh.
879 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
881 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
883 /* Turn on Enhanced/Extended controls */
884 isr_fcr |= (UART_EXAR654_EFR_ECB);
886 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
888 /* Write old LCR value back out, which turns enhanced access off */
889 writeb(lcrb, &ch->ch_cls_uart->lcr);
891 /* Clear out UART and FIFO */
892 readb(&ch->ch_cls_uart->txrx);
894 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
895 &ch->ch_cls_uart->isr_fcr);
898 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
900 readb(&ch->ch_cls_uart->lsr);
901 readb(&ch->ch_cls_uart->msr);
907 static void cls_uart_off(struct jsm_channel *ch)
909 /* Stop all interrupts from accurring. */
910 writeb(0, &ch->ch_cls_uart->ier);
914 * cls_get_uarts_bytes_left.
915 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
917 * The channel lock MUST be held by the calling function.
919 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch)
922 u8 lsr = readb(&ch->ch_cls_uart->lsr);
924 /* Determine whether the Transmitter is empty or not */
925 if (!(lsr & UART_LSR_TEMT))
928 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
937 * Starts sending a break thru the UART.
939 * The channel lock MUST be held by the calling function.
941 static void cls_send_break(struct jsm_channel *ch)
943 /* Tell the UART to start sending the break */
944 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
945 u8 temp = readb(&ch->ch_cls_uart->lcr);
947 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
948 ch->ch_flags |= (CH_BREAK_SENDING);
953 * cls_send_immediate_char.
954 * Sends a specific character as soon as possible to the UART,
955 * jumping over any bytes that might be in the write queue.
957 * The channel lock MUST be held by the calling function.
959 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c)
961 writeb(c, &ch->ch_cls_uart->txrx);
964 struct board_ops jsm_cls_ops = {
966 .uart_init = cls_uart_init,
967 .uart_off = cls_uart_off,
969 .assert_modem_signals = cls_assert_modem_signals,
970 .flush_uart_write = cls_flush_uart_write,
971 .flush_uart_read = cls_flush_uart_read,
972 .disable_receiver = cls_disable_receiver,
973 .enable_receiver = cls_enable_receiver,
974 .send_break = cls_send_break,
975 .clear_break = cls_clear_break,
976 .send_start_character = cls_send_start_character,
977 .send_stop_character = cls_send_stop_character,
978 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
979 .get_uart_bytes_left = cls_get_uart_bytes_left,
980 .send_immediate_char = cls_send_immediate_char