1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020-2023 Intel Corporation
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
19 #include "ivpu_mmu_context.h"
22 #define DRIVER_NAME "intel_vpu"
23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24 #define DRIVER_DATE "20230117"
26 #define PCI_DEVICE_ID_MTL 0x7d1d
27 #define PCI_DEVICE_ID_ARL 0xad1d
28 #define PCI_DEVICE_ID_LNL 0x643e
30 #define IVPU_HW_37XX 37
31 #define IVPU_HW_40XX 40
33 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
34 /* SSID 1 is used by the VPU to represent reserved context */
35 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
36 #define IVPU_USER_CONTEXT_MIN_SSID 2
37 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
39 #define IVPU_NUM_ENGINES 2
41 #define IVPU_PLATFORM_SILICON 0
42 #define IVPU_PLATFORM_SIMICS 2
43 #define IVPU_PLATFORM_FPGA 3
44 #define IVPU_PLATFORM_INVALID 8
46 #define IVPU_DBG_REG BIT(0)
47 #define IVPU_DBG_IRQ BIT(1)
48 #define IVPU_DBG_MMU BIT(2)
49 #define IVPU_DBG_FILE BIT(3)
50 #define IVPU_DBG_MISC BIT(4)
51 #define IVPU_DBG_FW_BOOT BIT(5)
52 #define IVPU_DBG_PM BIT(6)
53 #define IVPU_DBG_IPC BIT(7)
54 #define IVPU_DBG_BO BIT(8)
55 #define IVPU_DBG_JOB BIT(9)
56 #define IVPU_DBG_JSM BIT(10)
57 #define IVPU_DBG_KREF BIT(11)
58 #define IVPU_DBG_RPM BIT(12)
59 #define IVPU_DBG_MMU_MAP BIT(13)
61 #define ivpu_err(vdev, fmt, ...) \
62 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
64 #define ivpu_err_ratelimited(vdev, fmt, ...) \
65 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
67 #define ivpu_warn(vdev, fmt, ...) \
68 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
70 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
71 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
73 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
75 #define ivpu_dbg(vdev, type, fmt, args...) do { \
76 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
77 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
80 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
82 #define IVPU_PRINT_WA(wa_name) do { \
83 if (IVPU_WA(wa_name)) \
84 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
87 struct ivpu_wa_table {
89 bool clear_runtime_mem;
90 bool d3hot_after_power_off;
91 bool interrupt_clear_with_0;
92 bool disable_clock_relinquish;
93 bool disable_d0i3_msg;
103 struct drm_device drm;
109 struct ivpu_wa_table wa;
110 struct ivpu_hw_info *hw;
111 struct ivpu_mmu_info *mmu;
112 struct ivpu_fw_info *fw;
113 struct ivpu_ipc_info *ipc;
114 struct ivpu_pm_info *pm;
116 struct ivpu_mmu_context gctx;
117 struct ivpu_mmu_context rctx;
118 struct mutex context_list_lock; /* Protects user context addition/removal */
119 struct xarray context_xa;
120 struct xa_limit context_xa_limit;
122 struct mutex bo_list_lock; /* Protects bo_list */
123 struct list_head bo_list;
125 struct xarray submitted_jobs_xa;
126 struct ivpu_ipc_consumer job_done_consumer;
128 atomic64_t unique_id_counter;
134 int reschedule_suspend;
141 * file_priv has its own refcount (ref) that allows user space to close the fd
142 * without blocking even if VPU is still processing some jobs.
144 struct ivpu_file_priv {
146 struct ivpu_device *vdev;
147 struct mutex lock; /* Protects cmdq */
148 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
149 struct ivpu_mmu_context ctx;
154 extern int ivpu_dbg_mask;
155 extern u8 ivpu_pll_min_ratio;
156 extern u8 ivpu_pll_max_ratio;
157 extern bool ivpu_disable_mmu_cont_pages;
159 #define IVPU_TEST_MODE_FW_TEST BIT(0)
160 #define IVPU_TEST_MODE_NULL_HW BIT(1)
161 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
162 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
163 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
164 extern int ivpu_test_mode;
166 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
167 void ivpu_file_priv_put(struct ivpu_file_priv **link);
169 int ivpu_boot(struct ivpu_device *vdev);
170 int ivpu_shutdown(struct ivpu_device *vdev);
171 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
173 static inline u8 ivpu_revision(struct ivpu_device *vdev)
175 return to_pci_dev(vdev->drm.dev)->revision;
178 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
180 return to_pci_dev(vdev->drm.dev)->device;
183 static inline int ivpu_hw_gen(struct ivpu_device *vdev)
185 switch (ivpu_device_id(vdev)) {
186 case PCI_DEVICE_ID_MTL:
187 case PCI_DEVICE_ID_ARL:
189 case PCI_DEVICE_ID_LNL:
192 ivpu_err(vdev, "Unknown VPU device\n");
197 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
199 return container_of(dev, struct ivpu_device, drm);
202 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
204 struct xa_limit ctx_limit = vdev->context_xa_limit;
206 return (ctx_limit.max - ctx_limit.min + 1);
209 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
211 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
212 return vdev->platform;
215 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
217 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
220 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
222 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
225 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
227 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
230 #endif /* __IVPU_DRV_H__ */