1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
6 #include <linux/firmware.h>
7 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
11 #include <drm/drm_accel.h>
12 #include <drm/drm_file.h>
13 #include <drm/drm_gem.h>
14 #include <drm/drm_ioctl.h>
15 #include <drm/drm_prime.h>
17 #include "vpu_boot_api.h"
18 #include "ivpu_debugfs.h"
21 #include "ivpu_fw_log.h"
26 #include "ivpu_jsm_msg.h"
28 #include "ivpu_mmu_context.h"
31 #ifndef DRIVER_VERSION_STR
32 #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
33 __stringify(DRM_IVPU_DRIVER_MINOR) "."
36 static struct lock_class_key submitted_jobs_xa_lock_class_key;
39 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
40 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
43 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
44 MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
46 u8 ivpu_pll_min_ratio;
47 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
48 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency");
50 u8 ivpu_pll_max_ratio = U8_MAX;
51 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
52 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set VPU frequency");
54 bool ivpu_disable_mmu_cont_pages;
55 module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0644);
56 MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
58 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
60 struct ivpu_device *vdev = file_priv->vdev;
62 kref_get(&file_priv->ref);
64 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
65 file_priv->ctx.id, kref_read(&file_priv->ref));
70 static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv)
72 mutex_lock(&file_priv->lock);
73 if (file_priv->bound) {
74 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
76 ivpu_cmdq_release_all_locked(file_priv);
77 ivpu_jsm_context_release(vdev, file_priv->ctx.id);
78 ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
79 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
80 file_priv->bound = false;
81 drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id));
83 mutex_unlock(&file_priv->lock);
86 static void file_priv_release(struct kref *ref)
88 struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
89 struct ivpu_device *vdev = file_priv->vdev;
91 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n",
92 file_priv->ctx.id, (bool)file_priv->bound);
94 pm_runtime_get_sync(vdev->drm.dev);
95 mutex_lock(&vdev->context_list_lock);
96 file_priv_unbind(vdev, file_priv);
97 mutex_unlock(&vdev->context_list_lock);
98 pm_runtime_put_autosuspend(vdev->drm.dev);
100 mutex_destroy(&file_priv->lock);
104 void ivpu_file_priv_put(struct ivpu_file_priv **link)
106 struct ivpu_file_priv *file_priv = *link;
107 struct ivpu_device *vdev = file_priv->vdev;
109 drm_WARN_ON(&vdev->drm, !file_priv);
111 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
112 file_priv->ctx.id, kref_read(&file_priv->ref));
115 kref_put(&file_priv->ref, file_priv_release);
118 static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param *args)
120 switch (args->index) {
121 case DRM_IVPU_CAP_METRIC_STREAMER:
124 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
134 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
136 struct ivpu_file_priv *file_priv = file->driver_priv;
137 struct ivpu_device *vdev = file_priv->vdev;
138 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
139 struct drm_ivpu_param *args = data;
143 if (!drm_dev_enter(dev, &idx))
146 switch (args->param) {
147 case DRM_IVPU_PARAM_DEVICE_ID:
148 args->value = pdev->device;
150 case DRM_IVPU_PARAM_DEVICE_REVISION:
151 args->value = pdev->revision;
153 case DRM_IVPU_PARAM_PLATFORM_TYPE:
154 args->value = vdev->platform;
156 case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
157 args->value = ivpu_hw_ratio_to_freq(vdev, vdev->hw->pll.max_ratio);
159 case DRM_IVPU_PARAM_NUM_CONTEXTS:
160 args->value = ivpu_get_context_count(vdev);
162 case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
163 args->value = vdev->hw->ranges.user.start;
165 case DRM_IVPU_PARAM_CONTEXT_ID:
166 args->value = file_priv->ctx.id;
168 case DRM_IVPU_PARAM_FW_API_VERSION:
169 if (args->index < VPU_FW_API_VER_NUM) {
170 struct vpu_firmware_header *fw_hdr;
172 fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
173 args->value = fw_hdr->api_version[args->index];
178 case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
179 ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
181 case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
182 args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
184 case DRM_IVPU_PARAM_TILE_CONFIG:
185 args->value = vdev->hw->tile_fuse;
187 case DRM_IVPU_PARAM_SKU:
188 args->value = vdev->hw->sku;
190 case DRM_IVPU_PARAM_CAPABILITIES:
191 ret = ivpu_get_capabilities(vdev, args);
202 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
204 struct drm_ivpu_param *args = data;
207 switch (args->param) {
215 static int ivpu_open(struct drm_device *dev, struct drm_file *file)
217 struct ivpu_device *vdev = to_ivpu_device(dev);
218 struct ivpu_file_priv *file_priv;
222 if (!drm_dev_enter(dev, &idx))
225 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
231 file_priv->vdev = vdev;
232 file_priv->bound = true;
233 kref_init(&file_priv->ref);
234 mutex_init(&file_priv->lock);
236 mutex_lock(&vdev->context_list_lock);
238 ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, file_priv,
239 vdev->context_xa_limit, GFP_KERNEL);
241 ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
245 ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id);
249 mutex_unlock(&vdev->context_list_lock);
252 file->driver_priv = file_priv;
254 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
255 ctx_id, current->comm, task_pid_nr(current));
260 xa_erase_irq(&vdev->context_xa, ctx_id);
262 mutex_unlock(&vdev->context_list_lock);
263 mutex_destroy(&file_priv->lock);
270 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
272 struct ivpu_file_priv *file_priv = file->driver_priv;
273 struct ivpu_device *vdev = to_ivpu_device(dev);
275 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
276 file_priv->ctx.id, current->comm, task_pid_nr(current));
278 ivpu_file_priv_put(&file_priv);
281 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
282 DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
283 DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
284 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
285 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
286 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
287 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
290 static int ivpu_wait_for_ready(struct ivpu_device *vdev)
292 struct ivpu_ipc_consumer cons;
293 struct ivpu_ipc_hdr ipc_hdr;
294 unsigned long timeout;
297 if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST)
300 ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG, NULL);
302 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
304 ivpu_ipc_irq_handler(vdev, NULL);
305 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
306 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
312 ivpu_ipc_consumer_del(vdev, &cons);
314 if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
315 ivpu_err(vdev, "Invalid VPU ready message: 0x%x\n",
321 ivpu_dbg(vdev, PM, "VPU ready message received successfully\n");
327 * ivpu_boot() - Start VPU firmware
330 * This function is paired with ivpu_shutdown() but it doesn't power up the
331 * VPU because power up has to be called very early in ivpu_probe().
333 int ivpu_boot(struct ivpu_device *vdev)
337 /* Update boot params located at first 4KB of FW memory */
338 ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem));
340 ret = ivpu_hw_boot_fw(vdev);
342 ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
346 ret = ivpu_wait_for_ready(vdev);
348 ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
349 ivpu_hw_diagnose_failure(vdev);
350 ivpu_mmu_evtq_dump(vdev);
351 ivpu_fw_log_dump(vdev);
355 ivpu_hw_irq_clear(vdev);
356 enable_irq(vdev->irq);
357 ivpu_hw_irq_enable(vdev);
358 ivpu_ipc_enable(vdev);
362 void ivpu_prepare_for_reset(struct ivpu_device *vdev)
364 ivpu_hw_irq_disable(vdev);
365 disable_irq(vdev->irq);
366 ivpu_ipc_disable(vdev);
367 ivpu_mmu_disable(vdev);
370 int ivpu_shutdown(struct ivpu_device *vdev)
374 ivpu_prepare_for_reset(vdev);
376 ret = ivpu_hw_power_down(vdev);
378 ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
383 static const struct file_operations ivpu_fops = {
384 .owner = THIS_MODULE,
388 static const struct drm_driver driver = {
389 .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
392 .postclose = ivpu_postclose,
394 .gem_create_object = ivpu_gem_create_object,
395 .gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table,
397 .ioctls = ivpu_drm_ioctls,
398 .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
404 .major = DRM_IVPU_DRIVER_MAJOR,
405 .minor = DRM_IVPU_DRIVER_MINOR,
408 static irqreturn_t ivpu_irq_thread_handler(int irq, void *arg)
410 struct ivpu_device *vdev = arg;
412 return ivpu_ipc_irq_thread_handler(vdev);
415 static int ivpu_irq_init(struct ivpu_device *vdev)
417 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
420 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
422 ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
426 vdev->irq = pci_irq_vector(pdev, 0);
428 ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler,
429 ivpu_irq_thread_handler, IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
431 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
436 static int ivpu_pci_init(struct ivpu_device *vdev)
438 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
439 struct resource *bar0 = &pdev->resource[0];
440 struct resource *bar4 = &pdev->resource[4];
443 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
444 vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
445 if (IS_ERR(vdev->regv)) {
446 ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
447 return PTR_ERR(vdev->regv);
450 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
451 vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
452 if (IS_ERR(vdev->regb)) {
453 ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
454 return PTR_ERR(vdev->regb);
457 ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
459 ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
462 dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
464 /* Clear any pending errors */
465 pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
467 /* NPU does not require 10m D3hot delay */
468 pdev->d3hot_delay = 0;
470 ret = pcim_enable_device(pdev);
472 ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
476 pci_set_master(pdev);
481 static int ivpu_dev_init(struct ivpu_device *vdev)
485 vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
489 vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
493 vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
497 vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
501 vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
505 if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX) {
506 vdev->hw->ops = &ivpu_hw_40xx_ops;
507 vdev->hw->dma_bits = 48;
509 vdev->hw->ops = &ivpu_hw_37xx_ops;
510 vdev->hw->dma_bits = 38;
513 vdev->platform = IVPU_PLATFORM_INVALID;
514 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
515 vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
516 atomic64_set(&vdev->unique_id_counter, 0);
517 xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
518 xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
519 lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key);
520 INIT_LIST_HEAD(&vdev->bo_list);
522 ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
526 ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock);
530 ret = ivpu_pci_init(vdev);
534 ret = ivpu_irq_init(vdev);
538 /* Init basic HW info based on buttress registers which are accessible before power up */
539 ret = ivpu_hw_info_init(vdev);
543 /* Power up early so the rest of init code can access VPU registers */
544 ret = ivpu_hw_power_up(vdev);
548 ret = ivpu_mmu_global_context_init(vdev);
552 ret = ivpu_mmu_init(vdev);
554 goto err_mmu_gctx_fini;
556 ret = ivpu_mmu_reserved_context_init(vdev);
558 goto err_mmu_gctx_fini;
560 ret = ivpu_fw_init(vdev);
562 goto err_mmu_rctx_fini;
564 ret = ivpu_ipc_init(vdev);
570 ret = ivpu_boot(vdev);
574 ivpu_job_done_consumer_init(vdev);
575 ivpu_pm_enable(vdev);
584 ivpu_mmu_reserved_context_fini(vdev);
586 ivpu_mmu_global_context_fini(vdev);
588 ivpu_hw_power_down(vdev);
589 if (IVPU_WA(d3hot_after_power_off))
590 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
592 xa_destroy(&vdev->submitted_jobs_xa);
593 xa_destroy(&vdev->context_xa);
597 static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
599 struct ivpu_file_priv *file_priv;
600 unsigned long ctx_id;
602 mutex_lock(&vdev->context_list_lock);
604 xa_for_each(&vdev->context_xa, ctx_id, file_priv)
605 file_priv_unbind(vdev, file_priv);
607 mutex_unlock(&vdev->context_list_lock);
610 static void ivpu_dev_fini(struct ivpu_device *vdev)
612 ivpu_pm_disable(vdev);
614 if (IVPU_WA(d3hot_after_power_off))
615 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
617 ivpu_jobs_abort_all(vdev);
618 ivpu_job_done_consumer_fini(vdev);
619 ivpu_pm_cancel_recovery(vdev);
620 ivpu_bo_unbind_all_user_contexts(vdev);
624 ivpu_mmu_reserved_context_fini(vdev);
625 ivpu_mmu_global_context_fini(vdev);
627 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
628 xa_destroy(&vdev->submitted_jobs_xa);
629 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
630 xa_destroy(&vdev->context_xa);
633 static struct pci_device_id ivpu_pci_ids[] = {
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
639 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
641 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
643 struct ivpu_device *vdev;
646 vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
648 return PTR_ERR(vdev);
650 pci_set_drvdata(pdev, vdev);
652 ret = ivpu_dev_init(vdev);
656 ivpu_debugfs_init(vdev);
658 ret = drm_dev_register(&vdev->drm, 0);
660 dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
667 static void ivpu_remove(struct pci_dev *pdev)
669 struct ivpu_device *vdev = pci_get_drvdata(pdev);
671 drm_dev_unplug(&vdev->drm);
675 static const struct dev_pm_ops ivpu_drv_pci_pm = {
676 SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
677 SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
680 static const struct pci_error_handlers ivpu_drv_pci_err = {
681 .reset_prepare = ivpu_pm_reset_prepare_cb,
682 .reset_done = ivpu_pm_reset_done_cb,
685 static struct pci_driver ivpu_pci_driver = {
686 .name = KBUILD_MODNAME,
687 .id_table = ivpu_pci_ids,
689 .remove = ivpu_remove,
691 .pm = &ivpu_drv_pci_pm,
693 .err_handler = &ivpu_drv_pci_err,
696 module_pci_driver(ivpu_pci_driver);
698 MODULE_AUTHOR("Intel Corporation");
699 MODULE_DESCRIPTION(DRIVER_DESC);
700 MODULE_LICENSE("GPL and additional rights");
701 MODULE_VERSION(DRIVER_VERSION_STR);