2 * Support for Versatile FPGA-based IRQ controllers
4 #include <linux/bitops.h>
7 #include <linux/irqchip.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqchip/versatile-fpga.h>
10 #include <linux/irqdomain.h>
11 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
16 #include <asm/exception.h>
17 #include <asm/mach/irq.h>
19 #define IRQ_STATUS 0x00
20 #define IRQ_RAW_STATUS 0x04
21 #define IRQ_ENABLE_SET 0x08
22 #define IRQ_ENABLE_CLEAR 0x0c
23 #define INT_SOFT_SET 0x10
24 #define INT_SOFT_CLEAR 0x14
25 #define FIQ_STATUS 0x20
26 #define FIQ_RAW_STATUS 0x24
27 #define FIQ_ENABLE 0x28
28 #define FIQ_ENABLE_SET 0x28
29 #define FIQ_ENABLE_CLEAR 0x2C
31 #define PIC_ENABLES 0x20 /* set interrupt pass through bits */
34 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
35 * @base: memory offset in virtual memory
36 * @chip: chip container for this instance
37 * @domain: IRQ domain for this instance
38 * @valid: mask for valid IRQs on this controller
39 * @used_irqs: number of active IRQs on this controller
41 struct fpga_irq_data {
45 struct irq_domain *domain;
49 /* we cannot allocate memory when the controllers are initially registered */
50 static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
51 static int fpga_irq_id;
53 static void fpga_irq_mask(struct irq_data *d)
55 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
56 u32 mask = 1 << d->hwirq;
58 writel(mask, f->base + IRQ_ENABLE_CLEAR);
61 static void fpga_irq_unmask(struct irq_data *d)
63 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
64 u32 mask = 1 << d->hwirq;
66 writel(mask, f->base + IRQ_ENABLE_SET);
69 static void fpga_irq_handle(struct irq_desc *desc)
71 struct irq_chip *chip = irq_desc_get_chip(desc);
72 struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
75 chained_irq_enter(chip, desc);
77 status = readl(f->base + IRQ_STATUS);
84 unsigned int irq = ffs(status) - 1;
86 status &= ~(1 << irq);
87 generic_handle_irq(irq_find_mapping(f->domain, irq));
91 chained_irq_exit(chip, desc);
95 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
96 * if we've handled at least one interrupt. This does a single read of the
97 * status register and handles all interrupts in order from LSB first.
99 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
105 while ((status = readl(f->base + IRQ_STATUS))) {
106 irq = ffs(status) - 1;
107 handle_domain_irq(f->domain, irq, regs);
115 * Keep iterating over all registered FPGA IRQ controllers until there are
116 * no pending interrupts.
118 asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
123 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
124 handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
128 static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
129 irq_hw_number_t hwirq)
131 struct fpga_irq_data *f = d->host_data;
133 /* Skip invalid IRQs, only register handlers for the real ones */
134 if (!(f->valid & BIT(hwirq)))
136 irq_set_chip_data(irq, f);
137 irq_set_chip_and_handler(irq, &f->chip,
143 static const struct irq_domain_ops fpga_irqdomain_ops = {
144 .map = fpga_irqdomain_map,
145 .xlate = irq_domain_xlate_onetwocell,
148 void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
149 int parent_irq, u32 valid, struct device_node *node)
151 struct fpga_irq_data *f;
154 if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
155 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
158 f = &fpga_irq_devices[fpga_irq_id];
161 f->chip.irq_ack = fpga_irq_mask;
162 f->chip.irq_mask = fpga_irq_mask;
163 f->chip.irq_unmask = fpga_irq_unmask;
166 if (parent_irq != -1) {
167 irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
171 /* This will also allocate irq descriptors */
172 f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
173 &fpga_irqdomain_ops, f);
175 /* This will allocate all valid descriptors in the linear case */
176 for (i = 0; i < fls(valid); i++)
177 if (valid & BIT(i)) {
179 irq_create_mapping(f->domain, i);
183 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
184 fpga_irq_id, name, base, f->used_irqs);
185 if (parent_irq != -1)
186 pr_cont(", parent IRQ: %d\n", parent_irq);
194 int __init fpga_irq_of_init(struct device_node *node,
195 struct device_node *parent)
205 base = of_iomap(node, 0);
206 WARN(!base, "unable to map fpga irq registers\n");
208 if (of_property_read_u32(node, "clear-mask", &clear_mask))
211 if (of_property_read_u32(node, "valid-mask", &valid_mask))
214 writel(clear_mask, base + IRQ_ENABLE_CLEAR);
215 writel(clear_mask, base + FIQ_ENABLE_CLEAR);
217 /* Some chips are cascaded from a parent IRQ */
218 parent_irq = irq_of_parse_and_map(node, 0);
220 set_handle_irq(fpga_handle_irq);
224 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
227 * On Versatile AB/PB, some secondary interrupts have a direct
228 * pass-thru to the primary controller for IRQs 20 and 22-31 which need
229 * to be enabled. See section 3.10 of the Versatile AB user guide.
231 if (of_device_is_compatible(node, "arm,versatile-sic"))
232 writel(0xffd00000, base + PIC_ENABLES);
236 IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
237 IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
238 IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);