irq-renesas-rzg2l.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RZ/G2L IRQC Driver
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corporation.
   6  *
   7  * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/irqdomain.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/reset.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/syscore_ops.h>
  22
  23 #define IRQC_IRQ_START                  1
  24 #define IRQC_IRQ_COUNT                  8
  25 #define IRQC_TINT_START                 (IRQC_IRQ_START + IRQC_IRQ_COUNT)
  26 #define IRQC_TINT_COUNT                 32
  27 #define IRQC_NUM_IRQ                    (IRQC_TINT_START + IRQC_TINT_COUNT)
  28
  29 #define ISCR                            0x10
  30 #define IITSR                           0x14
  31 #define TSCR                            0x20
  32 #define TITSR(n)                        (0x24 + (n) * 4)
  33 #define TITSR0_MAX_INT                  16
  34 #define TITSEL_WIDTH                    0x2
  35 #define TSSR(n)                         (0x30 + ((n) * 4))
  36 #define TIEN                            BIT(7)
  37 #define TSSEL_SHIFT(n)                  (8 * (n))
  38 #define TSSEL_MASK                      GENMASK(7, 0)
  39 #define IRQ_MASK                        0x3
  40
  41 #define TSSR_OFFSET(n)                  ((n) % 4)
  42 #define TSSR_INDEX(n)                   ((n) / 4)
  43
  44 #define TITSR_TITSEL_EDGE_RISING        0
  45 #define TITSR_TITSEL_EDGE_FALLING       1
  46 #define TITSR_TITSEL_LEVEL_HIGH         2
  47 #define TITSR_TITSEL_LEVEL_LOW          3
  48
  49 #define IITSR_IITSEL(n, sense)          ((sense) << ((n) * 2))
  50 #define IITSR_IITSEL_LEVEL_LOW          0
  51 #define IITSR_IITSEL_EDGE_FALLING       1
  52 #define IITSR_IITSEL_EDGE_RISING        2
  53 #define IITSR_IITSEL_EDGE_BOTH          3
  54 #define IITSR_IITSEL_MASK(n)            IITSR_IITSEL((n), 3)
  55
  56 #define TINT_EXTRACT_HWIRQ(x)           FIELD_GET(GENMASK(15, 0), (x))
  57 #define TINT_EXTRACT_GPIOINT(x)         FIELD_GET(GENMASK(31, 16), (x))
  58
  59 /**
  60  * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
  61  * @iitsr: IITSR register
  62  * @titsr: TITSR registers
  63  */
  64 struct rzg2l_irqc_reg_cache {
  65         u32     iitsr;
  66         u32     titsr[2];
  67 };
  68
  69 /**
  70  * struct rzg2l_irqc_priv - IRQ controller private data structure
  71  * @base:       Controller's base address
  72  * @fwspec:     IRQ firmware specific data
  73  * @lock:       Lock to serialize access to hardware registers
  74  * @cache:      Registers cache for suspend/resume
  75  */
  76 static struct rzg2l_irqc_priv {
  77         void __iomem                    *base;
  78         struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
  79         raw_spinlock_t                  lock;
  80         struct rzg2l_irqc_reg_cache     cache;
  81 } *rzg2l_irqc_data;
  82
  83 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
  84 {
  85         return data->domain->host_data;
  86 }
  87
  88 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
  89 {
  90         unsigned int hw_irq = hwirq - IRQC_IRQ_START;
  91         u32 bit = BIT(hw_irq);
  92         u32 iitsr, iscr;
  93
  94         iscr = readl_relaxed(priv->base + ISCR);
  95         iitsr = readl_relaxed(priv->base + IITSR);
  96
  97         /*
  98          * ISCR can only be cleared if the type is falling-edge, rising-edge or
  99          * falling/rising-edge.
 100          */
 101         if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) {
 102                 writel_relaxed(iscr & ~bit, priv->base + ISCR);
 103                 /*
 104                  * Enforce that the posted write is flushed to prevent that the
 105                  * just handled interrupt is raised again.
 106                  */
 107                 readl_relaxed(priv->base + ISCR);
 108         }
 109 }
 110
 111 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
 112 {
 113         u32 bit = BIT(hwirq - IRQC_TINT_START);
 114         u32 reg;
 115
 116         reg = readl_relaxed(priv->base + TSCR);
 117         if (reg & bit) {
 118                 writel_relaxed(reg & ~bit, priv->base + TSCR);
 119                 /*
 120                  * Enforce that the posted write is flushed to prevent that the
 121                  * just handled interrupt is raised again.
 122                  */
 123                 readl_relaxed(priv->base + TSCR);
 124         }
 125 }
 126
 127 static void rzg2l_irqc_eoi(struct irq_data *d)
 128 {
 129         struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 130         unsigned int hw_irq = irqd_to_hwirq(d);
 131
 132         raw_spin_lock(&priv->lock);
 133         if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 134                 rzg2l_clear_irq_int(priv, hw_irq);
 135         else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
 136                 rzg2l_clear_tint_int(priv, hw_irq);
 137         raw_spin_unlock(&priv->lock);
 138         irq_chip_eoi_parent(d);
 139 }
 140
 141 static void rzg2l_irqc_irq_disable(struct irq_data *d)
 142 {
 143         unsigned int hw_irq = irqd_to_hwirq(d);
 144
 145         if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
 146                 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 147                 u32 offset = hw_irq - IRQC_TINT_START;
 148                 u32 tssr_offset = TSSR_OFFSET(offset);
 149                 u8 tssr_index = TSSR_INDEX(offset);
 150                 u32 reg;
 151
 152                 raw_spin_lock(&priv->lock);
 153                 reg = readl_relaxed(priv->base + TSSR(tssr_index));
 154                 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
 155                 writel_relaxed(reg, priv->base + TSSR(tssr_index));
 156                 raw_spin_unlock(&priv->lock);
 157         }
 158         irq_chip_disable_parent(d);
 159 }
 160
 161 static void rzg2l_irqc_irq_enable(struct irq_data *d)
 162 {
 163         unsigned int hw_irq = irqd_to_hwirq(d);
 164
 165         if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
 166                 unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d);
 167                 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 168                 u32 offset = hw_irq - IRQC_TINT_START;
 169                 u32 tssr_offset = TSSR_OFFSET(offset);
 170                 u8 tssr_index = TSSR_INDEX(offset);
 171                 u32 reg;
 172
 173                 raw_spin_lock(&priv->lock);
 174                 reg = readl_relaxed(priv->base + TSSR(tssr_index));
 175                 reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
 176                 writel_relaxed(reg, priv->base + TSSR(tssr_index));
 177                 raw_spin_unlock(&priv->lock);
 178         }
 179         irq_chip_enable_parent(d);
 180 }
 181
 182 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
 183 {
 184         struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 185         unsigned int hwirq = irqd_to_hwirq(d);
 186         u32 iitseln = hwirq - IRQC_IRQ_START;
 187         bool clear_irq_int = false;
 188         u16 sense, tmp;
 189
 190         switch (type & IRQ_TYPE_SENSE_MASK) {
 191         case IRQ_TYPE_LEVEL_LOW:
 192                 sense = IITSR_IITSEL_LEVEL_LOW;
 193                 break;
 194
 195         case IRQ_TYPE_EDGE_FALLING:
 196                 sense = IITSR_IITSEL_EDGE_FALLING;
 197                 clear_irq_int = true;
 198                 break;
 199
 200         case IRQ_TYPE_EDGE_RISING:
 201                 sense = IITSR_IITSEL_EDGE_RISING;
 202                 clear_irq_int = true;
 203                 break;
 204
 205         case IRQ_TYPE_EDGE_BOTH:
 206                 sense = IITSR_IITSEL_EDGE_BOTH;
 207                 clear_irq_int = true;
 208                 break;
 209
 210         default:
 211                 return -EINVAL;
 212         }
 213
 214         raw_spin_lock(&priv->lock);
 215         tmp = readl_relaxed(priv->base + IITSR);
 216         tmp &= ~IITSR_IITSEL_MASK(iitseln);
 217         tmp |= IITSR_IITSEL(iitseln, sense);
 218         if (clear_irq_int)
 219                 rzg2l_clear_irq_int(priv, hwirq);
 220         writel_relaxed(tmp, priv->base + IITSR);
 221         raw_spin_unlock(&priv->lock);
 222
 223         return 0;
 224 }
 225
 226 static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv,
 227                                                   u32 reg, u32 tssr_offset, u8 tssr_index)
 228 {
 229         u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
 230         u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
 231
 232         /* Clear the relevant byte in reg */
 233         reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
 234         /* Set TINT and leave TIEN clear */
 235         reg |= tint << TSSEL_SHIFT(tssr_offset);
 236         writel_relaxed(reg, priv->base + TSSR(tssr_index));
 237
 238         return reg | tien;
 239 }
 240
 241 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
 242 {
 243         struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 244         unsigned int hwirq = irqd_to_hwirq(d);
 245         u32 titseln = hwirq - IRQC_TINT_START;
 246         u32 tssr_offset = TSSR_OFFSET(titseln);
 247         u8 tssr_index = TSSR_INDEX(titseln);
 248         u8 index, sense;
 249         u32 reg, tssr;
 250
 251         switch (type & IRQ_TYPE_SENSE_MASK) {
 252         case IRQ_TYPE_EDGE_RISING:
 253                 sense = TITSR_TITSEL_EDGE_RISING;
 254                 break;
 255
 256         case IRQ_TYPE_EDGE_FALLING:
 257                 sense = TITSR_TITSEL_EDGE_FALLING;
 258                 break;
 259
 260         default:
 261                 return -EINVAL;
 262         }
 263
 264         index = 0;
 265         if (titseln >= TITSR0_MAX_INT) {
 266                 titseln -= TITSR0_MAX_INT;
 267                 index = 1;
 268         }
 269
 270         raw_spin_lock(&priv->lock);
 271         tssr = readl_relaxed(priv->base + TSSR(tssr_index));
 272         tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index);
 273         reg = readl_relaxed(priv->base + TITSR(index));
 274         reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
 275         reg |= sense << (titseln * TITSEL_WIDTH);
 276         writel_relaxed(reg, priv->base + TITSR(index));
 277         rzg2l_clear_tint_int(priv, hwirq);
 278         writel_relaxed(tssr, priv->base + TSSR(tssr_index));
 279         raw_spin_unlock(&priv->lock);
 280
 281         return 0;
 282 }
 283
 284 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
 285 {
 286         unsigned int hw_irq = irqd_to_hwirq(d);
 287         int ret = -EINVAL;
 288
 289         if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
 290                 ret = rzg2l_irq_set_type(d, type);
 291         else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
 292                 ret = rzg2l_tint_set_edge(d, type);
 293         if (ret)
 294                 return ret;
 295
 296         return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
 297 }
 298
 299 static int rzg2l_irqc_irq_suspend(void)
 300 {
 301         struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
 302         void __iomem *base = rzg2l_irqc_data->base;
 303
 304         cache->iitsr = readl_relaxed(base + IITSR);
 305         for (u8 i = 0; i < 2; i++)
 306                 cache->titsr[i] = readl_relaxed(base + TITSR(i));
 307
 308         return 0;
 309 }
 310
 311 static void rzg2l_irqc_irq_resume(void)
 312 {
 313         struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
 314         void __iomem *base = rzg2l_irqc_data->base;
 315
 316         /*
 317          * Restore only interrupt type. TSSRx will be restored at the
 318          * request of pin controller to avoid spurious interrupts due
 319          * to invalid PIN states.
 320          */
 321         for (u8 i = 0; i < 2; i++)
 322                 writel_relaxed(cache->titsr[i], base + TITSR(i));
 323         writel_relaxed(cache->iitsr, base + IITSR);
 324 }
 325
 326 static struct syscore_ops rzg2l_irqc_syscore_ops = {
 327         .suspend        = rzg2l_irqc_irq_suspend,
 328         .resume         = rzg2l_irqc_irq_resume,
 329 };
 330
 331 static const struct irq_chip irqc_chip = {
 332         .name                   = "rzg2l-irqc",
 333         .irq_eoi                = rzg2l_irqc_eoi,
 334         .irq_mask               = irq_chip_mask_parent,
 335         .irq_unmask             = irq_chip_unmask_parent,
 336         .irq_disable            = rzg2l_irqc_irq_disable,
 337         .irq_enable             = rzg2l_irqc_irq_enable,
 338         .irq_get_irqchip_state  = irq_chip_get_parent_state,
 339         .irq_set_irqchip_state  = irq_chip_set_parent_state,
 340         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 341         .irq_set_type           = rzg2l_irqc_set_type,
 342         .irq_set_affinity       = irq_chip_set_affinity_parent,
 343         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 344                                   IRQCHIP_SET_TYPE_MASKED |
 345                                   IRQCHIP_SKIP_SET_WAKE,
 346 };
 347
 348 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
 349                             unsigned int nr_irqs, void *arg)
 350 {
 351         struct rzg2l_irqc_priv *priv = domain->host_data;
 352         unsigned long tint = 0;
 353         irq_hw_number_t hwirq;
 354         unsigned int type;
 355         int ret;
 356
 357         ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
 358         if (ret)
 359                 return ret;
 360
 361         /*
 362          * For TINT interrupts ie where pinctrl driver is child of irqc domain
 363          * the hwirq and TINT are encoded in fwspec->param[0].
 364          * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
 365          * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
 366          * in IRQC registers to enable a given gpio pin as interrupt.
 367          */
 368         if (hwirq > IRQC_IRQ_COUNT) {
 369                 tint = TINT_EXTRACT_GPIOINT(hwirq);
 370                 hwirq = TINT_EXTRACT_HWIRQ(hwirq);
 371
 372                 if (hwirq < IRQC_TINT_START)
 373                         return -EINVAL;
 374         }
 375
 376         if (hwirq > (IRQC_NUM_IRQ - 1))
 377                 return -EINVAL;
 378
 379         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
 380                                             (void *)(uintptr_t)tint);
 381         if (ret)
 382                 return ret;
 383
 384         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
 385 }
 386
 387 static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
 388         .alloc = rzg2l_irqc_alloc,
 389         .free = irq_domain_free_irqs_common,
 390         .translate = irq_domain_translate_twocell,
 391 };
 392
 393 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
 394                                        struct device_node *np)
 395 {
 396         struct of_phandle_args map;
 397         unsigned int i;
 398         int ret;
 399
 400         for (i = 0; i < IRQC_NUM_IRQ; i++) {
 401                 ret = of_irq_parse_one(np, i, &map);
 402                 if (ret)
 403                         return ret;
 404                 of_phandle_args_to_fwspec(np, map.args, map.args_count,
 405                                           &priv->fwspec[i]);
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
 412 {
 413         struct irq_domain *irq_domain, *parent_domain;
 414         struct platform_device *pdev;
 415         struct reset_control *resetn;
 416         int ret;
 417
 418         pdev = of_find_device_by_node(node);
 419         if (!pdev)
 420                 return -ENODEV;
 421
 422         parent_domain = irq_find_host(parent);
 423         if (!parent_domain) {
 424                 dev_err(&pdev->dev, "cannot find parent domain\n");
 425                 return -ENODEV;
 426         }
 427
 428         rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
 429         if (!rzg2l_irqc_data)
 430                 return -ENOMEM;
 431
 432         rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
 433         if (IS_ERR(rzg2l_irqc_data->base))
 434                 return PTR_ERR(rzg2l_irqc_data->base);
 435
 436         ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
 437         if (ret) {
 438                 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
 439                 return ret;
 440         }
 441
 442         resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 443         if (IS_ERR(resetn))
 444                 return PTR_ERR(resetn);
 445
 446         ret = reset_control_deassert(resetn);
 447         if (ret) {
 448                 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
 449                 return ret;
 450         }
 451
 452         pm_runtime_enable(&pdev->dev);
 453         ret = pm_runtime_resume_and_get(&pdev->dev);
 454         if (ret < 0) {
 455                 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
 456                 goto pm_disable;
 457         }
 458
 459         raw_spin_lock_init(&rzg2l_irqc_data->lock);
 460
 461         irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
 462                                               node, &rzg2l_irqc_domain_ops,
 463                                               rzg2l_irqc_data);
 464         if (!irq_domain) {
 465                 dev_err(&pdev->dev, "failed to add irq domain\n");
 466                 ret = -ENOMEM;
 467                 goto pm_put;
 468         }
 469
 470         register_syscore_ops(&rzg2l_irqc_syscore_ops);
 471
 472         return 0;
 473
 474 pm_put:
 475         pm_runtime_put(&pdev->dev);
 476 pm_disable:
 477         pm_runtime_disable(&pdev->dev);
 478         reset_control_assert(resetn);
 479         return ret;
 480 }
 481
 482 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
 483 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
 484 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
 485 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
 486 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");