2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/cpu.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/irqdomain.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/msi.h>
32 #include <asm/mach/arch.h>
33 #include <asm/exception.h>
34 #include <asm/smp_plat.h>
35 #include <asm/mach/irq.h>
38 * Overall diagram of the Armada XP interrupt controller:
44 * +---------------+ +---------------+
46 * | per-CPU | | per-CPU |
47 * | mask/unmask | | mask/unmask |
50 * +---------------+ +---------------+
53 * \\_______________________//
55 * +-------------------+
57 * | Global interrupt |
60 * +-------------------+
66 * The "global interrupt mask/unmask" is modified using the
67 * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
68 * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
71 * The "per-CPU mask/unmask" is modified using the
72 * ARMADA_370_XP_INT_SET_MASK_OFFS and
73 * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
74 * "per_cpu_int_base". This base address points to a special address,
75 * which automatically accesses the registers of the current CPU.
77 * The per-CPU mask/unmask can also be adjusted using the global
78 * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
79 * to configure interrupt affinity.
81 * Due to this model, all interrupts need to be mask/unmasked at two
82 * different levels: at the global level and at the per-CPU level.
84 * This driver takes the following approach to deal with this:
86 * - For global interrupts:
88 * At ->map() time, a global interrupt is unmasked at the per-CPU
89 * mask/unmask level. It is therefore unmasked at this level for
90 * the current CPU, running the ->map() code. This allows to have
91 * the interrupt unmasked at this level in non-SMP
92 * configurations. In SMP configurations, the ->set_affinity()
93 * callback is called, which using the
94 * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
97 * The ->mask() and ->unmask() operations only mask/unmask the
98 * interrupt at the "global" level.
100 * So, a global interrupt is enabled at the per-CPU level as soon
101 * as it is mapped. At run time, the masking/unmasking takes place
102 * at the global level.
104 * - For per-CPU interrupts
106 * At ->map() time, a per-CPU interrupt is unmasked at the global
109 * The ->mask() and ->unmask() operations mask/unmask the interrupt
110 * at the per-CPU level.
112 * So, a per-CPU interrupt is enabled at the global level as soon
113 * as it is mapped. At run time, the masking/unmasking takes place
114 * at the per-CPU level.
117 /* Registers relative to main_int_base */
118 #define ARMADA_370_XP_INT_CONTROL (0x00)
119 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04)
120 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
121 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
122 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
123 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
124 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
126 /* Registers relative to per_cpu_int_base */
127 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08)
128 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c)
129 #define ARMADA_375_PPI_CAUSE (0x10)
130 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
131 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
132 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
133 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
136 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
138 #define IPI_DOORBELL_START (0)
139 #define IPI_DOORBELL_END (8)
140 #define IPI_DOORBELL_MASK 0xFF
141 #define PCI_MSI_DOORBELL_START (16)
142 #define PCI_MSI_DOORBELL_NR (16)
143 #define PCI_MSI_DOORBELL_END (32)
144 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
146 static void __iomem *per_cpu_int_base;
147 static void __iomem *main_int_base;
148 static struct irq_domain *armada_370_xp_mpic_domain;
149 static u32 doorbell_mask_reg;
150 static int parent_irq;
151 #ifdef CONFIG_PCI_MSI
152 static struct irq_domain *armada_370_xp_msi_domain;
153 static struct irq_domain *armada_370_xp_msi_inner_domain;
154 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
155 static DEFINE_MUTEX(msi_used_lock);
156 static phys_addr_t msi_doorbell_addr;
159 static inline bool is_percpu_irq(irq_hw_number_t irq)
161 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
169 * For shared global interrupts, mask/unmask global enable bit
170 * For CPU interrupts, mask/unmask the calling CPU's bit
172 static void armada_370_xp_irq_mask(struct irq_data *d)
174 irq_hw_number_t hwirq = irqd_to_hwirq(d);
176 if (!is_percpu_irq(hwirq))
177 writel(hwirq, main_int_base +
178 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
180 writel(hwirq, per_cpu_int_base +
181 ARMADA_370_XP_INT_SET_MASK_OFFS);
184 static void armada_370_xp_irq_unmask(struct irq_data *d)
186 irq_hw_number_t hwirq = irqd_to_hwirq(d);
188 if (!is_percpu_irq(hwirq))
189 writel(hwirq, main_int_base +
190 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
192 writel(hwirq, per_cpu_int_base +
193 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
196 #ifdef CONFIG_PCI_MSI
198 static struct irq_chip armada_370_xp_msi_irq_chip = {
200 .irq_mask = pci_msi_mask_irq,
201 .irq_unmask = pci_msi_unmask_irq,
204 static struct msi_domain_info armada_370_xp_msi_domain_info = {
205 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
206 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
207 .chip = &armada_370_xp_msi_irq_chip,
210 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
212 msg->address_lo = lower_32_bits(msi_doorbell_addr);
213 msg->address_hi = upper_32_bits(msi_doorbell_addr);
214 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
217 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
218 const struct cpumask *mask, bool force)
223 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
225 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
226 .irq_set_affinity = armada_370_xp_msi_set_affinity,
229 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
230 unsigned int nr_irqs, void *args)
234 mutex_lock(&msi_used_lock);
235 hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
236 order_base_2(nr_irqs));
237 mutex_unlock(&msi_used_lock);
242 for (i = 0; i < nr_irqs; i++) {
243 irq_domain_set_info(domain, virq + i, hwirq + i,
244 &armada_370_xp_msi_bottom_irq_chip,
245 domain->host_data, handle_simple_irq,
252 static void armada_370_xp_msi_free(struct irq_domain *domain,
253 unsigned int virq, unsigned int nr_irqs)
255 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
257 mutex_lock(&msi_used_lock);
258 bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
259 mutex_unlock(&msi_used_lock);
262 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
263 .alloc = armada_370_xp_msi_alloc,
264 .free = armada_370_xp_msi_free,
267 static int armada_370_xp_msi_init(struct device_node *node,
268 phys_addr_t main_int_phys_base)
272 msi_doorbell_addr = main_int_phys_base +
273 ARMADA_370_XP_SW_TRIG_INT_OFFS;
275 armada_370_xp_msi_inner_domain =
276 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
277 &armada_370_xp_msi_domain_ops, NULL);
278 if (!armada_370_xp_msi_inner_domain)
281 armada_370_xp_msi_domain =
282 pci_msi_create_irq_domain(of_node_to_fwnode(node),
283 &armada_370_xp_msi_domain_info,
284 armada_370_xp_msi_inner_domain);
285 if (!armada_370_xp_msi_domain) {
286 irq_domain_remove(armada_370_xp_msi_inner_domain);
290 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
291 | PCI_MSI_DOORBELL_MASK;
293 writel(reg, per_cpu_int_base +
294 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
296 /* Unmask IPI interrupt */
297 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
302 static inline int armada_370_xp_msi_init(struct device_node *node,
303 phys_addr_t main_int_phys_base)
309 static void armada_xp_mpic_perf_init(void)
314 * This Performance Counter Overflow interrupt is specific for
315 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
317 if (!of_machine_is_compatible("marvell,armada-370-xp"))
320 cpuid = cpu_logical_map(smp_processor_id());
322 /* Enable Performance Counter Overflow interrupts */
323 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
324 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
328 static struct irq_domain *ipi_domain;
330 static void armada_370_xp_ipi_mask(struct irq_data *d)
333 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
334 reg &= ~BIT(d->hwirq);
335 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
338 static void armada_370_xp_ipi_unmask(struct irq_data *d)
341 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
342 reg |= BIT(d->hwirq);
343 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
346 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
347 const struct cpumask *mask)
349 unsigned long map = 0;
352 /* Convert our logical CPU mask into a physical one. */
353 for_each_cpu(cpu, mask)
354 map |= 1 << cpu_logical_map(cpu);
357 * Ensure that stores to Normal memory are visible to the
358 * other CPUs before issuing the IPI.
363 writel((map << 8) | d->hwirq, main_int_base +
364 ARMADA_370_XP_SW_TRIG_INT_OFFS);
367 static void armada_370_xp_ipi_eoi(struct irq_data *d)
369 writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
372 static struct irq_chip ipi_irqchip = {
374 .irq_mask = armada_370_xp_ipi_mask,
375 .irq_unmask = armada_370_xp_ipi_unmask,
376 .irq_eoi = armada_370_xp_ipi_eoi,
377 .ipi_send_mask = armada_370_xp_ipi_send_mask,
380 static int armada_370_xp_ipi_alloc(struct irq_domain *d,
382 unsigned int nr_irqs, void *args)
386 for (i = 0; i < nr_irqs; i++) {
387 irq_set_percpu_devid(virq + i);
388 irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
390 handle_percpu_devid_fasteoi_ipi,
397 static void armada_370_xp_ipi_free(struct irq_domain *d,
399 unsigned int nr_irqs)
401 /* Not freeing IPIs */
404 static const struct irq_domain_ops ipi_domain_ops = {
405 .alloc = armada_370_xp_ipi_alloc,
406 .free = armada_370_xp_ipi_free,
409 static void ipi_resume(void)
413 for (i = 0; i < IPI_DOORBELL_END; i++) {
416 irq = irq_find_mapping(ipi_domain, i);
419 if (irq_percpu_is_enabled(irq)) {
421 d = irq_domain_get_irq_data(ipi_domain, irq);
422 armada_370_xp_ipi_unmask(d);
427 static __init void armada_xp_ipi_init(struct device_node *node)
431 ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
433 &ipi_domain_ops, NULL);
434 if (WARN_ON(!ipi_domain))
437 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
438 base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,
439 NUMA_NO_NODE, NULL, false, NULL);
440 if (WARN_ON(!base_ipi))
443 set_smp_ipi_range(base_ipi, IPI_DOORBELL_END);
446 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
448 static int armada_xp_set_affinity(struct irq_data *d,
449 const struct cpumask *mask_val, bool force)
451 irq_hw_number_t hwirq = irqd_to_hwirq(d);
452 unsigned long reg, mask;
455 /* Select a single core from the affinity mask which is online */
456 cpu = cpumask_any_and(mask_val, cpu_online_mask);
457 mask = 1UL << cpu_logical_map(cpu);
459 raw_spin_lock(&irq_controller_lock);
460 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
461 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
462 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
463 raw_spin_unlock(&irq_controller_lock);
465 irq_data_update_effective_affinity(d, cpumask_of(cpu));
467 return IRQ_SET_MASK_OK;
470 static void armada_xp_mpic_smp_cpu_init(void)
475 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
476 nr_irqs = (control >> 2) & 0x3ff;
478 for (i = 0; i < nr_irqs; i++)
479 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
481 /* Disable all IPIs */
482 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
484 /* Clear pending IPIs */
485 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
487 /* Unmask IPI interrupt */
488 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
491 static void armada_xp_mpic_reenable_percpu(void)
495 /* Re-enable per-CPU interrupts that were enabled before suspend */
496 for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
497 struct irq_data *data;
500 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
504 data = irq_get_irq_data(virq);
506 if (!irq_percpu_is_enabled(virq))
509 armada_370_xp_irq_unmask(data);
515 static int armada_xp_mpic_starting_cpu(unsigned int cpu)
517 armada_xp_mpic_perf_init();
518 armada_xp_mpic_smp_cpu_init();
519 armada_xp_mpic_reenable_percpu();
523 static int mpic_cascaded_starting_cpu(unsigned int cpu)
525 armada_xp_mpic_perf_init();
526 armada_xp_mpic_reenable_percpu();
527 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
531 static void armada_xp_mpic_smp_cpu_init(void) {}
532 static void ipi_resume(void) {}
535 static struct irq_chip armada_370_xp_irq_chip = {
537 .irq_mask = armada_370_xp_irq_mask,
538 .irq_mask_ack = armada_370_xp_irq_mask,
539 .irq_unmask = armada_370_xp_irq_unmask,
541 .irq_set_affinity = armada_xp_set_affinity,
543 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
546 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
547 unsigned int virq, irq_hw_number_t hw)
549 armada_370_xp_irq_mask(irq_get_irq_data(virq));
550 if (!is_percpu_irq(hw))
551 writel(hw, per_cpu_int_base +
552 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
554 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
555 irq_set_status_flags(virq, IRQ_LEVEL);
557 if (is_percpu_irq(hw)) {
558 irq_set_percpu_devid(virq);
559 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
560 handle_percpu_devid_irq);
562 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
564 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
571 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
572 .map = armada_370_xp_mpic_irq_map,
573 .xlate = irq_domain_xlate_onecell,
576 #ifdef CONFIG_PCI_MSI
577 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
581 msimask = readl_relaxed(per_cpu_int_base +
582 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
583 & PCI_MSI_DOORBELL_MASK;
585 writel(~msimask, per_cpu_int_base +
586 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
588 for (msinr = PCI_MSI_DOORBELL_START;
589 msinr < PCI_MSI_DOORBELL_END; msinr++) {
592 if (!(msimask & BIT(msinr)))
596 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
597 msinr - PCI_MSI_DOORBELL_START);
598 generic_handle_irq(irq);
600 irq = msinr - PCI_MSI_DOORBELL_START;
601 handle_domain_irq(armada_370_xp_msi_inner_domain,
607 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
610 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
612 struct irq_chip *chip = irq_desc_get_chip(desc);
613 unsigned long irqmap, irqn, irqsrc, cpuid;
614 unsigned int cascade_irq;
616 chained_irq_enter(chip, desc);
618 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
619 cpuid = cpu_logical_map(smp_processor_id());
621 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
622 irqsrc = readl_relaxed(main_int_base +
623 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
625 /* Check if the interrupt is not masked on current CPU.
626 * Test IRQ (0-1) and FIQ (8-9) mask bits.
628 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
632 armada_370_xp_handle_msi_irq(NULL, true);
636 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
637 generic_handle_irq(cascade_irq);
640 chained_irq_exit(chip, desc);
643 static void __exception_irq_entry
644 armada_370_xp_handle_irq(struct pt_regs *regs)
649 irqstat = readl_relaxed(per_cpu_int_base +
650 ARMADA_370_XP_CPU_INTACK_OFFS);
651 irqnr = irqstat & 0x3FF;
657 handle_domain_irq(armada_370_xp_mpic_domain,
664 armada_370_xp_handle_msi_irq(regs, false);
669 unsigned long ipimask;
672 ipimask = readl_relaxed(per_cpu_int_base +
673 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
676 for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
677 handle_domain_irq(ipi_domain, ipi, regs);
684 static int armada_370_xp_mpic_suspend(void)
686 doorbell_mask_reg = readl(per_cpu_int_base +
687 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
691 static void armada_370_xp_mpic_resume(void)
696 /* Re-enable interrupts */
697 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
698 for (irq = 0; irq < nirqs; irq++) {
699 struct irq_data *data;
702 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
706 data = irq_get_irq_data(virq);
708 if (!is_percpu_irq(irq)) {
709 /* Non per-CPU interrupts */
710 writel(irq, per_cpu_int_base +
711 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
712 if (!irqd_irq_disabled(data))
713 armada_370_xp_irq_unmask(data);
715 /* Per-CPU interrupts */
716 writel(irq, main_int_base +
717 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
720 * Re-enable on the current CPU,
721 * armada_xp_mpic_reenable_percpu() will take
722 * care of secondary CPUs when they come up.
724 if (irq_percpu_is_enabled(virq))
725 armada_370_xp_irq_unmask(data);
729 /* Reconfigure doorbells for IPIs and MSIs */
730 writel(doorbell_mask_reg,
731 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
732 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
733 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
734 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
735 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
740 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
741 .suspend = armada_370_xp_mpic_suspend,
742 .resume = armada_370_xp_mpic_resume,
745 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
746 struct device_node *parent)
748 struct resource main_int_res, per_cpu_int_res;
752 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
753 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
755 BUG_ON(!request_mem_region(main_int_res.start,
756 resource_size(&main_int_res),
758 BUG_ON(!request_mem_region(per_cpu_int_res.start,
759 resource_size(&per_cpu_int_res),
762 main_int_base = ioremap(main_int_res.start,
763 resource_size(&main_int_res));
764 BUG_ON(!main_int_base);
766 per_cpu_int_base = ioremap(per_cpu_int_res.start,
767 resource_size(&per_cpu_int_res));
768 BUG_ON(!per_cpu_int_base);
770 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
771 nr_irqs = (control >> 2) & 0x3ff;
773 for (i = 0; i < nr_irqs; i++)
774 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
776 armada_370_xp_mpic_domain =
777 irq_domain_add_linear(node, nr_irqs,
778 &armada_370_xp_mpic_irq_ops, NULL);
779 BUG_ON(!armada_370_xp_mpic_domain);
780 irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
782 /* Setup for the boot CPU */
783 armada_xp_mpic_perf_init();
784 armada_xp_mpic_smp_cpu_init();
786 armada_370_xp_msi_init(node, main_int_res.start);
788 parent_irq = irq_of_parse_and_map(node, 0);
789 if (parent_irq <= 0) {
790 irq_set_default_host(armada_370_xp_mpic_domain);
791 set_handle_irq(armada_370_xp_handle_irq);
793 armada_xp_ipi_init(node);
794 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
795 "irqchip/armada/ipi:starting",
796 armada_xp_mpic_starting_cpu, NULL);
800 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
801 "irqchip/armada/cascade:starting",
802 mpic_cascaded_starting_cpu, NULL);
804 irq_set_chained_handler(parent_irq,
805 armada_370_xp_mpic_handle_cascade_irq);
808 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
813 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);