1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/bootmem.h>
52 #include <asm/irqdomain.h>
57 #include <asm/proto.h>
60 #include <asm/timer.h>
61 #include <asm/i8259.h>
62 #include <asm/setup.h>
63 #include <asm/irq_remapping.h>
64 #include <asm/hw_irq.h>
68 #define for_each_ioapic(idx) \
69 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
70 #define for_each_ioapic_reverse(idx) \
71 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
72 #define for_each_pin(idx, pin) \
73 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
74 #define for_each_ioapic_pin(idx, pin) \
75 for_each_ioapic((idx)) \
76 for_each_pin((idx), (pin))
77 #define for_each_irq_pin(entry, head) \
78 list_for_each_entry(entry, &head, list)
80 static DEFINE_RAW_SPINLOCK(ioapic_lock);
81 static DEFINE_MUTEX(ioapic_mutex);
82 static unsigned int ioapic_dynirq_base;
83 static int ioapic_initialized;
86 struct list_head list;
91 struct list_head irq_2_pin;
92 struct IO_APIC_route_entry entry;
99 struct mp_ioapic_gsi {
104 static struct ioapic {
106 * # of IRQ routing registers
110 * Saved state during suspend/resume, or while enabling intr-remap.
112 struct IO_APIC_route_entry *saved_registers;
113 /* I/O APIC config */
114 struct mpc_ioapic mp_config;
115 /* IO APIC gsi routing info */
116 struct mp_ioapic_gsi gsi_config;
117 struct ioapic_domain_cfg irqdomain_cfg;
118 struct irq_domain *irqdomain;
119 struct resource *iomem_res;
120 } ioapics[MAX_IO_APICS];
122 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124 int mpc_ioapic_id(int ioapic_idx)
126 return ioapics[ioapic_idx].mp_config.apicid;
129 unsigned int mpc_ioapic_addr(int ioapic_idx)
131 return ioapics[ioapic_idx].mp_config.apicaddr;
134 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136 return &ioapics[ioapic_idx].gsi_config;
139 static inline int mp_ioapic_pin_count(int ioapic)
141 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
146 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
151 static inline bool mp_is_legacy_irq(int irq)
153 return irq >= 0 && irq < nr_legacy_irqs();
157 * Initialize all legacy IRQs and all pins on the first IOAPIC
158 * if we have legacy interrupt controller. Kernel boot option "pirq="
159 * may rely on non-legacy pins on the first IOAPIC.
161 static inline int mp_init_irq_at_boot(int ioapic, int irq)
163 if (!nr_legacy_irqs())
166 return ioapic == 0 || mp_is_legacy_irq(irq);
169 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
171 return ioapics[ioapic].irqdomain;
176 /* The one past the highest gsi number used */
179 /* MP IRQ source entries */
180 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
182 /* # of MP IRQ source entries */
186 int mp_bus_id_to_type[MAX_MP_BUSSES];
189 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
191 int skip_ioapic_setup;
194 * disable_ioapic_support() - disables ioapic support at runtime
196 void disable_ioapic_support(void)
200 noioapicreroute = -1;
202 skip_ioapic_setup = 1;
205 static int __init parse_noapic(char *str)
207 /* disable IO-APIC */
208 disable_ioapic_support();
211 early_param("noapic", parse_noapic);
213 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
214 void mp_save_irq(struct mpc_intsrc *m)
218 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
219 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
220 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
221 m->srcbusirq, m->dstapic, m->dstirq);
223 for (i = 0; i < mp_irq_entries; i++) {
224 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
228 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
229 if (++mp_irq_entries == MAX_IRQ_SOURCES)
230 panic("Max # of irq sources exceeded!!\n");
233 static void alloc_ioapic_saved_registers(int idx)
237 if (ioapics[idx].saved_registers)
240 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
241 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
242 if (!ioapics[idx].saved_registers)
243 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
246 static void free_ioapic_saved_registers(int idx)
248 kfree(ioapics[idx].saved_registers);
249 ioapics[idx].saved_registers = NULL;
252 int __init arch_early_ioapic_init(void)
256 if (!nr_legacy_irqs())
260 alloc_ioapic_saved_registers(i);
267 unsigned int unused[3];
269 unsigned int unused2[11];
273 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
275 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
276 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
279 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
281 struct io_apic __iomem *io_apic = io_apic_base(apic);
282 writel(vector, &io_apic->eoi);
285 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
287 struct io_apic __iomem *io_apic = io_apic_base(apic);
288 writel(reg, &io_apic->index);
289 return readl(&io_apic->data);
292 static void io_apic_write(unsigned int apic, unsigned int reg,
295 struct io_apic __iomem *io_apic = io_apic_base(apic);
297 writel(reg, &io_apic->index);
298 writel(value, &io_apic->data);
302 struct { u32 w1, w2; };
303 struct IO_APIC_route_entry entry;
306 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
308 union entry_union eu;
310 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
311 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
316 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
318 union entry_union eu;
321 raw_spin_lock_irqsave(&ioapic_lock, flags);
322 eu.entry = __ioapic_read_entry(apic, pin);
323 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
329 * When we write a new IO APIC routing entry, we need to write the high
330 * word first! If the mask bit in the low word is clear, we will enable
331 * the interrupt, and we need to make sure the entry is fully populated
332 * before that happens.
334 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
336 union entry_union eu = {{0, 0}};
339 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
340 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
343 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
347 raw_spin_lock_irqsave(&ioapic_lock, flags);
348 __ioapic_write_entry(apic, pin, e);
349 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
353 * When we mask an IO APIC routing entry, we need to write the low
354 * word first, in order to set the mask bit before we change the
357 static void ioapic_mask_entry(int apic, int pin)
360 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
362 raw_spin_lock_irqsave(&ioapic_lock, flags);
363 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
364 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
369 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
370 * shared ISA-space IRQs, so we have to support them. We are super
371 * fast in the common case, and fast for shared ISA-space IRQs.
373 static int __add_pin_to_irq_node(struct mp_chip_data *data,
374 int node, int apic, int pin)
376 struct irq_pin_list *entry;
378 /* don't allow duplicates */
379 for_each_irq_pin(entry, data->irq_2_pin)
380 if (entry->apic == apic && entry->pin == pin)
383 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
385 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
391 list_add_tail(&entry->list, &data->irq_2_pin);
396 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
398 struct irq_pin_list *tmp, *entry;
400 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
401 if (entry->apic == apic && entry->pin == pin) {
402 list_del(&entry->list);
408 static void add_pin_to_irq_node(struct mp_chip_data *data,
409 int node, int apic, int pin)
411 if (__add_pin_to_irq_node(data, node, apic, pin))
412 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
416 * Reroute an IRQ to a different pin.
418 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
419 int oldapic, int oldpin,
420 int newapic, int newpin)
422 struct irq_pin_list *entry;
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 if (entry->apic == oldapic && entry->pin == oldpin) {
426 entry->apic = newapic;
428 /* every one is different, right? */
433 /* old apic/pin didn't exist, so just add new ones */
434 add_pin_to_irq_node(data, node, newapic, newpin);
437 static void io_apic_modify_irq(struct mp_chip_data *data,
438 int mask_and, int mask_or,
439 void (*final)(struct irq_pin_list *entry))
441 union entry_union eu;
442 struct irq_pin_list *entry;
444 eu.entry = data->entry;
447 data->entry = eu.entry;
449 for_each_irq_pin(entry, data->irq_2_pin) {
450 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
456 static void io_apic_sync(struct irq_pin_list *entry)
459 * Synchronize the IO-APIC and the CPU by doing
460 * a dummy read from the IO-APIC
462 struct io_apic __iomem *io_apic;
464 io_apic = io_apic_base(entry->apic);
465 readl(&io_apic->data);
468 static void mask_ioapic_irq(struct irq_data *irq_data)
470 struct mp_chip_data *data = irq_data->chip_data;
473 raw_spin_lock_irqsave(&ioapic_lock, flags);
474 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
475 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
478 static void __unmask_ioapic(struct mp_chip_data *data)
480 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
483 static void unmask_ioapic_irq(struct irq_data *irq_data)
485 struct mp_chip_data *data = irq_data->chip_data;
488 raw_spin_lock_irqsave(&ioapic_lock, flags);
489 __unmask_ioapic(data);
490 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
494 * IO-APIC versions below 0x20 don't support EOI register.
495 * For the record, here is the information about various versions:
497 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
498 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
501 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
502 * version as 0x2. This is an error with documentation and these ICH chips
503 * use io-apic's of version 0x20.
505 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
506 * Otherwise, we simulate the EOI message manually by changing the trigger
507 * mode to edge and then back to level, with RTE being masked during this.
509 static void __eoi_ioapic_pin(int apic, int pin, int vector)
511 if (mpc_ioapic_ver(apic) >= 0x20) {
512 io_apic_eoi(apic, vector);
514 struct IO_APIC_route_entry entry, entry1;
516 entry = entry1 = __ioapic_read_entry(apic, pin);
519 * Mask the entry and change the trigger mode to edge.
521 entry1.mask = IOAPIC_MASKED;
522 entry1.trigger = IOAPIC_EDGE;
524 __ioapic_write_entry(apic, pin, entry1);
527 * Restore the previous level triggered entry.
529 __ioapic_write_entry(apic, pin, entry);
533 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
536 struct irq_pin_list *entry;
538 raw_spin_lock_irqsave(&ioapic_lock, flags);
539 for_each_irq_pin(entry, data->irq_2_pin)
540 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
541 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
544 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
546 struct IO_APIC_route_entry entry;
548 /* Check delivery_mode to be sure we're not clearing an SMI pin */
549 entry = ioapic_read_entry(apic, pin);
550 if (entry.delivery_mode == dest_SMI)
554 * Make sure the entry is masked and re-read the contents to check
555 * if it is a level triggered pin and if the remote-IRR is set.
557 if (entry.mask == IOAPIC_UNMASKED) {
558 entry.mask = IOAPIC_MASKED;
559 ioapic_write_entry(apic, pin, entry);
560 entry = ioapic_read_entry(apic, pin);
567 * Make sure the trigger mode is set to level. Explicit EOI
568 * doesn't clear the remote-IRR if the trigger mode is not
571 if (entry.trigger == IOAPIC_EDGE) {
572 entry.trigger = IOAPIC_LEVEL;
573 ioapic_write_entry(apic, pin, entry);
575 raw_spin_lock_irqsave(&ioapic_lock, flags);
576 __eoi_ioapic_pin(apic, pin, entry.vector);
577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
581 * Clear the rest of the bits in the IO-APIC RTE except for the mask
584 ioapic_mask_entry(apic, pin);
585 entry = ioapic_read_entry(apic, pin);
587 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
588 mpc_ioapic_id(apic), pin);
591 static void clear_IO_APIC (void)
595 for_each_ioapic_pin(apic, pin)
596 clear_IO_APIC_pin(apic, pin);
601 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
602 * specific CPU-side IRQs.
606 static int pirq_entries[MAX_PIRQS] = {
607 [0 ... MAX_PIRQS - 1] = -1
610 static int __init ioapic_pirq_setup(char *str)
613 int ints[MAX_PIRQS+1];
615 get_options(str, ARRAY_SIZE(ints), ints);
617 apic_printk(APIC_VERBOSE, KERN_INFO
618 "PIRQ redirection, working around broken MP-BIOS.\n");
620 if (ints[0] < MAX_PIRQS)
623 for (i = 0; i < max; i++) {
624 apic_printk(APIC_VERBOSE, KERN_DEBUG
625 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
627 * PIRQs are mapped upside down, usually.
629 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
634 __setup("pirq=", ioapic_pirq_setup);
635 #endif /* CONFIG_X86_32 */
638 * Saves all the IO-APIC RTE's
640 int save_ioapic_entries(void)
645 for_each_ioapic(apic) {
646 if (!ioapics[apic].saved_registers) {
651 for_each_pin(apic, pin)
652 ioapics[apic].saved_registers[pin] =
653 ioapic_read_entry(apic, pin);
660 * Mask all IO APIC entries.
662 void mask_ioapic_entries(void)
666 for_each_ioapic(apic) {
667 if (!ioapics[apic].saved_registers)
670 for_each_pin(apic, pin) {
671 struct IO_APIC_route_entry entry;
673 entry = ioapics[apic].saved_registers[pin];
674 if (entry.mask == IOAPIC_UNMASKED) {
675 entry.mask = IOAPIC_MASKED;
676 ioapic_write_entry(apic, pin, entry);
683 * Restore IO APIC entries which was saved in the ioapic structure.
685 int restore_ioapic_entries(void)
689 for_each_ioapic(apic) {
690 if (!ioapics[apic].saved_registers)
693 for_each_pin(apic, pin)
694 ioapic_write_entry(apic, pin,
695 ioapics[apic].saved_registers[pin]);
701 * Find the IRQ entry number of a certain pin.
703 static int find_irq_entry(int ioapic_idx, int pin, int type)
707 for (i = 0; i < mp_irq_entries; i++)
708 if (mp_irqs[i].irqtype == type &&
709 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
710 mp_irqs[i].dstapic == MP_APIC_ALL) &&
711 mp_irqs[i].dstirq == pin)
718 * Find the pin to which IRQ[irq] (ISA) is connected
720 static int __init find_isa_irq_pin(int irq, int type)
724 for (i = 0; i < mp_irq_entries; i++) {
725 int lbus = mp_irqs[i].srcbus;
727 if (test_bit(lbus, mp_bus_not_pci) &&
728 (mp_irqs[i].irqtype == type) &&
729 (mp_irqs[i].srcbusirq == irq))
731 return mp_irqs[i].dstirq;
736 static int __init find_isa_irq_apic(int irq, int type)
740 for (i = 0; i < mp_irq_entries; i++) {
741 int lbus = mp_irqs[i].srcbus;
743 if (test_bit(lbus, mp_bus_not_pci) &&
744 (mp_irqs[i].irqtype == type) &&
745 (mp_irqs[i].srcbusirq == irq))
749 if (i < mp_irq_entries) {
752 for_each_ioapic(ioapic_idx)
753 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
762 * EISA Edge/Level control register, ELCR
764 static int EISA_ELCR(unsigned int irq)
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = 0x4d0 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
777 /* ISA interrupts are always active high edge triggered,
778 * when listed as conforming in the MP table. */
780 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
781 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
783 /* EISA interrupts are always polarity zero and can be edge or level
784 * trigger depending on the ELCR value. If an interrupt is listed as
785 * EISA conforming in the MP table, that means its trigger type must
786 * be read in from the ELCR */
788 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
789 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
791 /* PCI interrupts are always active low level triggered,
792 * when listed as conforming in the MP table. */
794 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
795 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
797 static int irq_polarity(int idx)
799 int bus = mp_irqs[idx].srcbus;
802 * Determine IRQ line polarity (high active or low active):
804 switch (mp_irqs[idx].irqflag & 0x03) {
806 /* conforms to spec, ie. bus-type dependent polarity */
807 if (test_bit(bus, mp_bus_not_pci))
808 return default_ISA_polarity(idx);
810 return default_PCI_polarity(idx);
812 return IOAPIC_POL_HIGH;
814 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
816 default: /* Pointless default required due to do gcc stupidity */
817 return IOAPIC_POL_LOW;
822 static int eisa_irq_trigger(int idx, int bus, int trigger)
824 switch (mp_bus_id_to_type[bus]) {
829 return default_EISA_trigger(idx);
831 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
835 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
841 static int irq_trigger(int idx)
843 int bus = mp_irqs[idx].srcbus;
847 * Determine IRQ trigger mode (edge or level sensitive):
849 switch ((mp_irqs[idx].irqflag >> 2) & 0x03) {
851 /* conforms to spec, ie. bus-type dependent trigger mode */
852 if (test_bit(bus, mp_bus_not_pci))
853 trigger = default_ISA_trigger(idx);
855 trigger = default_PCI_trigger(idx);
856 /* Take EISA into account */
857 return eisa_irq_trigger(idx, bus, trigger);
861 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
863 default: /* Pointless default required due to do gcc stupidity */
868 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
869 int trigger, int polarity)
871 init_irq_alloc_info(info, NULL);
872 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
873 info->ioapic_node = node;
874 info->ioapic_trigger = trigger;
875 info->ioapic_polarity = polarity;
876 info->ioapic_valid = 1;
880 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
883 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
884 struct irq_alloc_info *src,
885 u32 gsi, int ioapic_idx, int pin)
887 int trigger, polarity;
889 copy_irq_alloc_info(dst, src);
890 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
891 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
892 dst->ioapic_pin = pin;
893 dst->ioapic_valid = 1;
894 if (src && src->ioapic_valid) {
895 dst->ioapic_node = src->ioapic_node;
896 dst->ioapic_trigger = src->ioapic_trigger;
897 dst->ioapic_polarity = src->ioapic_polarity;
899 dst->ioapic_node = NUMA_NO_NODE;
900 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
901 dst->ioapic_trigger = trigger;
902 dst->ioapic_polarity = polarity;
905 * PCI interrupts are always active low level
908 dst->ioapic_trigger = IOAPIC_LEVEL;
909 dst->ioapic_polarity = IOAPIC_POL_LOW;
914 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
916 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
919 static void mp_register_handler(unsigned int irq, unsigned long trigger)
921 irq_flow_handler_t hdl;
925 irq_set_status_flags(irq, IRQ_LEVEL);
928 irq_clear_status_flags(irq, IRQ_LEVEL);
932 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
933 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
936 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
938 struct mp_chip_data *data = irq_get_chip_data(irq);
941 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
942 * and polarity attirbutes. So allow the first user to reprogram the
943 * pin with real trigger and polarity attributes.
945 if (irq < nr_legacy_irqs() && data->count == 1) {
946 if (info->ioapic_trigger != data->trigger)
947 mp_register_handler(irq, info->ioapic_trigger);
948 data->entry.trigger = data->trigger = info->ioapic_trigger;
949 data->entry.polarity = data->polarity = info->ioapic_polarity;
952 return data->trigger == info->ioapic_trigger &&
953 data->polarity == info->ioapic_polarity;
956 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
957 struct irq_alloc_info *info)
961 int type = ioapics[ioapic].irqdomain_cfg.type;
964 case IOAPIC_DOMAIN_LEGACY:
966 * Dynamically allocate IRQ number for non-ISA IRQs in the first
967 * 16 GSIs on some weird platforms.
969 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
971 legacy = mp_is_legacy_irq(irq);
973 case IOAPIC_DOMAIN_STRICT:
976 case IOAPIC_DOMAIN_DYNAMIC:
979 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
983 return __irq_domain_alloc_irqs(domain, irq, 1,
984 ioapic_alloc_attr_node(info),
989 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
990 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
991 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
992 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
993 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
994 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
995 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
996 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
998 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
999 int irq, int ioapic, int pin,
1000 struct irq_alloc_info *info)
1002 struct mp_chip_data *data;
1003 struct irq_data *irq_data = irq_get_irq_data(irq);
1004 int node = ioapic_alloc_attr_node(info);
1007 * Legacy ISA IRQ has already been allocated, just add pin to
1008 * the pin list assoicated with this IRQ and program the IOAPIC
1009 * entry. The IOAPIC entry
1011 if (irq_data && irq_data->parent_data) {
1012 if (!mp_check_pin_attr(irq, info))
1014 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1018 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1021 irq_data = irq_domain_get_irq_data(domain, irq);
1022 data = irq_data->chip_data;
1023 data->isa_irq = true;
1030 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1031 unsigned int flags, struct irq_alloc_info *info)
1034 bool legacy = false;
1035 struct irq_alloc_info tmp;
1036 struct mp_chip_data *data;
1037 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1042 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1043 irq = mp_irqs[idx].srcbusirq;
1044 legacy = mp_is_legacy_irq(irq);
1046 * IRQ2 is unusable for historical reasons on systems which
1047 * have a legacy PIC. See the comment vs. IRQ2 further down.
1049 * If this gets removed at some point then the related code
1050 * in lapic_assign_system_vectors() needs to be adjusted as
1053 if (legacy && irq == PIC_CASCADE_IR)
1057 mutex_lock(&ioapic_mutex);
1058 if (!(flags & IOAPIC_MAP_ALLOC)) {
1060 irq = irq_find_mapping(domain, pin);
1065 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1067 irq = alloc_isa_irq_from_domain(domain, irq,
1069 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1070 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1071 else if (!mp_check_pin_attr(irq, &tmp))
1074 data = irq_get_chip_data(irq);
1078 mutex_unlock(&ioapic_mutex);
1083 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1085 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1088 * Debugging check, we are in big trouble if this message pops up!
1090 if (mp_irqs[idx].dstirq != pin)
1091 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1093 #ifdef CONFIG_X86_32
1095 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1097 if ((pin >= 16) && (pin <= 23)) {
1098 if (pirq_entries[pin-16] != -1) {
1099 if (!pirq_entries[pin-16]) {
1100 apic_printk(APIC_VERBOSE, KERN_DEBUG
1101 "disabling PIRQ%d\n", pin-16);
1103 int irq = pirq_entries[pin-16];
1104 apic_printk(APIC_VERBOSE, KERN_DEBUG
1105 "using PIRQ%d -> IRQ %d\n",
1113 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1116 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1118 int ioapic, pin, idx;
1120 ioapic = mp_find_ioapic(gsi);
1124 pin = mp_find_ioapic_pin(ioapic, gsi);
1125 idx = find_irq_entry(ioapic, pin, mp_INT);
1126 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1129 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1132 void mp_unmap_irq(int irq)
1134 struct irq_data *irq_data = irq_get_irq_data(irq);
1135 struct mp_chip_data *data;
1137 if (!irq_data || !irq_data->domain)
1140 data = irq_data->chip_data;
1141 if (!data || data->isa_irq)
1144 mutex_lock(&ioapic_mutex);
1145 if (--data->count == 0)
1146 irq_domain_free_irqs(irq, 1);
1147 mutex_unlock(&ioapic_mutex);
1151 * Find a specific PCI IRQ entry.
1152 * Not an __init, possibly needed by modules
1154 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1156 int irq, i, best_ioapic = -1, best_idx = -1;
1158 apic_printk(APIC_DEBUG,
1159 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1161 if (test_bit(bus, mp_bus_not_pci)) {
1162 apic_printk(APIC_VERBOSE,
1163 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1167 for (i = 0; i < mp_irq_entries; i++) {
1168 int lbus = mp_irqs[i].srcbus;
1169 int ioapic_idx, found = 0;
1171 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1172 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1175 for_each_ioapic(ioapic_idx)
1176 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1177 mp_irqs[i].dstapic == MP_APIC_ALL) {
1185 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1186 if (irq > 0 && !IO_APIC_IRQ(irq))
1189 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1191 best_ioapic = ioapic_idx;
1196 * Use the first all-but-pin matching entry as a
1197 * best-guess fuzzy result for broken mptables.
1201 best_ioapic = ioapic_idx;
1208 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1211 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1213 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1215 static void __init setup_IO_APIC_irqs(void)
1217 unsigned int ioapic, pin;
1220 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1222 for_each_ioapic_pin(ioapic, pin) {
1223 idx = find_irq_entry(ioapic, pin, mp_INT);
1225 apic_printk(APIC_VERBOSE,
1226 KERN_DEBUG " apic %d pin %d not connected\n",
1227 mpc_ioapic_id(ioapic), pin);
1229 pin_2_irq(idx, ioapic, pin,
1230 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1234 void ioapic_zap_locks(void)
1236 raw_spin_lock_init(&ioapic_lock);
1239 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1243 struct IO_APIC_route_entry entry;
1244 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1246 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1247 for (i = 0; i <= nr_entries; i++) {
1248 entry = ioapic_read_entry(apic, i);
1249 snprintf(buf, sizeof(buf),
1250 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1252 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1253 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1254 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1255 entry.vector, entry.irr, entry.delivery_status);
1256 if (ir_entry->format)
1257 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1258 buf, (ir_entry->index2 << 15) | ir_entry->index,
1261 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1263 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1264 "logical " : "physical",
1265 entry.dest, entry.delivery_mode);
1269 static void __init print_IO_APIC(int ioapic_idx)
1271 union IO_APIC_reg_00 reg_00;
1272 union IO_APIC_reg_01 reg_01;
1273 union IO_APIC_reg_02 reg_02;
1274 union IO_APIC_reg_03 reg_03;
1275 unsigned long flags;
1277 raw_spin_lock_irqsave(&ioapic_lock, flags);
1278 reg_00.raw = io_apic_read(ioapic_idx, 0);
1279 reg_01.raw = io_apic_read(ioapic_idx, 1);
1280 if (reg_01.bits.version >= 0x10)
1281 reg_02.raw = io_apic_read(ioapic_idx, 2);
1282 if (reg_01.bits.version >= 0x20)
1283 reg_03.raw = io_apic_read(ioapic_idx, 3);
1284 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1286 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1287 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1288 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1289 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1290 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1292 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1293 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1294 reg_01.bits.entries);
1296 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1297 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1298 reg_01.bits.version);
1301 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1302 * but the value of reg_02 is read as the previous read register
1303 * value, so ignore it if reg_02 == reg_01.
1305 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1306 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1307 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1311 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1312 * or reg_03, but the value of reg_0[23] is read as the previous read
1313 * register value, so ignore it if reg_03 == reg_0[12].
1315 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1316 reg_03.raw != reg_01.raw) {
1317 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1318 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1321 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1322 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1325 void __init print_IO_APICs(void)
1330 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1331 for_each_ioapic(ioapic_idx)
1332 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1333 mpc_ioapic_id(ioapic_idx),
1334 ioapics[ioapic_idx].nr_registers);
1337 * We are a bit conservative about what we expect. We have to
1338 * know about every hardware change ASAP.
1340 printk(KERN_INFO "testing the IO APIC.......................\n");
1342 for_each_ioapic(ioapic_idx)
1343 print_IO_APIC(ioapic_idx);
1345 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1346 for_each_active_irq(irq) {
1347 struct irq_pin_list *entry;
1348 struct irq_chip *chip;
1349 struct mp_chip_data *data;
1351 chip = irq_get_chip(irq);
1352 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1354 data = irq_get_chip_data(irq);
1357 if (list_empty(&data->irq_2_pin))
1360 printk(KERN_DEBUG "IRQ%d ", irq);
1361 for_each_irq_pin(entry, data->irq_2_pin)
1362 pr_cont("-> %d:%d", entry->apic, entry->pin);
1366 printk(KERN_INFO ".................................... done.\n");
1369 /* Where if anywhere is the i8259 connect in external int mode */
1370 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1372 void __init enable_IO_APIC(void)
1374 int i8259_apic, i8259_pin;
1377 if (skip_ioapic_setup)
1380 if (!nr_legacy_irqs() || !nr_ioapics)
1383 for_each_ioapic_pin(apic, pin) {
1384 /* See if any of the pins is in ExtINT mode */
1385 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1387 /* If the interrupt line is enabled and in ExtInt mode
1388 * I have found the pin where the i8259 is connected.
1390 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1391 ioapic_i8259.apic = apic;
1392 ioapic_i8259.pin = pin;
1397 /* Look to see what if the MP table has reported the ExtINT */
1398 /* If we could not find the appropriate pin by looking at the ioapic
1399 * the i8259 probably is not connected the ioapic but give the
1400 * mptable a chance anyway.
1402 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1403 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1404 /* Trust the MP table if nothing is setup in the hardware */
1405 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1406 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1407 ioapic_i8259.pin = i8259_pin;
1408 ioapic_i8259.apic = i8259_apic;
1410 /* Complain if the MP table and the hardware disagree */
1411 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1412 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1414 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1418 * Do not trust the IO-APIC being empty at bootup
1423 void native_disable_io_apic(void)
1426 * If the i8259 is routed through an IOAPIC
1427 * Put that IOAPIC in virtual wire mode
1428 * so legacy interrupts can be delivered.
1430 if (ioapic_i8259.pin != -1) {
1431 struct IO_APIC_route_entry entry;
1433 memset(&entry, 0, sizeof(entry));
1434 entry.mask = IOAPIC_UNMASKED;
1435 entry.trigger = IOAPIC_EDGE;
1436 entry.polarity = IOAPIC_POL_HIGH;
1437 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1438 entry.delivery_mode = dest_ExtINT;
1439 entry.dest = read_apic_id();
1442 * Add it to the IO-APIC irq-routing table:
1444 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1447 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1448 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1452 * Not an __init, needed by the reboot code
1454 void disable_IO_APIC(void)
1457 * Clear the IO-APIC before rebooting:
1461 if (!nr_legacy_irqs())
1464 x86_io_apic_ops.disable();
1467 #ifdef CONFIG_X86_32
1469 * function to set the IO-APIC physical IDs based on the
1470 * values stored in the MPC table.
1472 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1474 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1476 union IO_APIC_reg_00 reg_00;
1477 physid_mask_t phys_id_present_map;
1480 unsigned char old_id;
1481 unsigned long flags;
1484 * This is broken; anything with a real cpu count has to
1485 * circumvent this idiocy regardless.
1487 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1490 * Set the IOAPIC ID to the value stored in the MPC table.
1492 for_each_ioapic(ioapic_idx) {
1493 /* Read the register 0 value */
1494 raw_spin_lock_irqsave(&ioapic_lock, flags);
1495 reg_00.raw = io_apic_read(ioapic_idx, 0);
1496 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1498 old_id = mpc_ioapic_id(ioapic_idx);
1500 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1501 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1502 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1503 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1505 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1509 * Sanity check, is the ID really free? Every APIC in a
1510 * system must have a unique ID or we get lots of nice
1511 * 'stuck on smp_invalidate_needed IPI wait' messages.
1513 if (apic->check_apicid_used(&phys_id_present_map,
1514 mpc_ioapic_id(ioapic_idx))) {
1515 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1516 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1517 for (i = 0; i < get_physical_broadcast(); i++)
1518 if (!physid_isset(i, phys_id_present_map))
1520 if (i >= get_physical_broadcast())
1521 panic("Max APIC ID exceeded!\n");
1522 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1524 physid_set(i, phys_id_present_map);
1525 ioapics[ioapic_idx].mp_config.apicid = i;
1528 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1530 apic_printk(APIC_VERBOSE, "Setting %d in the "
1531 "phys_id_present_map\n",
1532 mpc_ioapic_id(ioapic_idx));
1533 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1537 * We need to adjust the IRQ routing table
1538 * if the ID changed.
1540 if (old_id != mpc_ioapic_id(ioapic_idx))
1541 for (i = 0; i < mp_irq_entries; i++)
1542 if (mp_irqs[i].dstapic == old_id)
1544 = mpc_ioapic_id(ioapic_idx);
1547 * Update the ID register according to the right value
1548 * from the MPC table if they are different.
1550 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1553 apic_printk(APIC_VERBOSE, KERN_INFO
1554 "...changing IO-APIC physical APIC ID to %d ...",
1555 mpc_ioapic_id(ioapic_idx));
1557 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1558 raw_spin_lock_irqsave(&ioapic_lock, flags);
1559 io_apic_write(ioapic_idx, 0, reg_00.raw);
1560 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1565 raw_spin_lock_irqsave(&ioapic_lock, flags);
1566 reg_00.raw = io_apic_read(ioapic_idx, 0);
1567 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1568 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1569 pr_cont("could not set ID!\n");
1571 apic_printk(APIC_VERBOSE, " ok.\n");
1575 void __init setup_ioapic_ids_from_mpc(void)
1581 * Don't check I/O APIC IDs for xAPIC systems. They have
1582 * no meaning without the serial APIC bus.
1584 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1585 || APIC_XAPIC(boot_cpu_apic_version))
1587 setup_ioapic_ids_from_mpc_nocheck();
1591 int no_timer_check __initdata;
1593 static int __init notimercheck(char *s)
1598 __setup("no_timer_check", notimercheck);
1601 * There is a nasty bug in some older SMP boards, their mptable lies
1602 * about the timer IRQ. We do the following to work around the situation:
1604 * - timer IRQ defaults to IO-APIC IRQ
1605 * - if this function detects that timer IRQs are defunct, then we fall
1606 * back to ISA timer IRQs
1608 static int __init timer_irq_works(void)
1610 unsigned long t1 = jiffies;
1611 unsigned long flags;
1616 local_save_flags(flags);
1618 /* Let ten ticks pass... */
1619 mdelay((10 * 1000) / HZ);
1620 local_irq_restore(flags);
1623 * Expect a few ticks at least, to be sure some possible
1624 * glue logic does not lock up after one or two first
1625 * ticks in a non-ExtINT mode. Also the local APIC
1626 * might have cached one ExtINT interrupt. Finally, at
1627 * least one tick may be lost due to delays.
1631 if (time_after(jiffies, t1 + 4))
1637 * In the SMP+IOAPIC case it might happen that there are an unspecified
1638 * number of pending IRQ events unhandled. These cases are very rare,
1639 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1640 * better to do it this way as thus we do not have to be aware of
1641 * 'pending' interrupts in the IRQ path, except at this point.
1644 * Edge triggered needs to resend any interrupt
1645 * that was delayed but this is now handled in the device
1650 * Starting up a edge-triggered IO-APIC interrupt is
1651 * nasty - we need to make sure that we get the edge.
1652 * If it is already asserted for some reason, we need
1653 * return 1 to indicate that is was pending.
1655 * This is not complete - we should be able to fake
1656 * an edge even if it isn't on the 8259A...
1658 static unsigned int startup_ioapic_irq(struct irq_data *data)
1660 int was_pending = 0, irq = data->irq;
1661 unsigned long flags;
1663 raw_spin_lock_irqsave(&ioapic_lock, flags);
1664 if (irq < nr_legacy_irqs()) {
1665 legacy_pic->mask(irq);
1666 if (legacy_pic->irq_pending(irq))
1669 __unmask_ioapic(data->chip_data);
1670 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1675 atomic_t irq_mis_count;
1677 #ifdef CONFIG_GENERIC_PENDING_IRQ
1678 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1680 struct irq_pin_list *entry;
1681 unsigned long flags;
1683 raw_spin_lock_irqsave(&ioapic_lock, flags);
1684 for_each_irq_pin(entry, data->irq_2_pin) {
1689 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1690 /* Is the remote IRR bit set? */
1691 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1692 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1696 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1701 static inline bool ioapic_irqd_mask(struct irq_data *data)
1703 /* If we are moving the IRQ we need to mask it */
1704 if (unlikely(irqd_is_setaffinity_pending(data))) {
1705 if (!irqd_irq_masked(data))
1706 mask_ioapic_irq(data);
1712 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1714 if (unlikely(masked)) {
1715 /* Only migrate the irq if the ack has been received.
1717 * On rare occasions the broadcast level triggered ack gets
1718 * delayed going to ioapics, and if we reprogram the
1719 * vector while Remote IRR is still set the irq will never
1722 * To prevent this scenario we read the Remote IRR bit
1723 * of the ioapic. This has two effects.
1724 * - On any sane system the read of the ioapic will
1725 * flush writes (and acks) going to the ioapic from
1727 * - We get to see if the ACK has actually been delivered.
1729 * Based on failed experiments of reprogramming the
1730 * ioapic entry from outside of irq context starting
1731 * with masking the ioapic entry and then polling until
1732 * Remote IRR was clear before reprogramming the
1733 * ioapic I don't trust the Remote IRR bit to be
1734 * completey accurate.
1736 * However there appears to be no other way to plug
1737 * this race, so if the Remote IRR bit is not
1738 * accurate and is causing problems then it is a hardware bug
1739 * and you can go talk to the chipset vendor about it.
1741 if (!io_apic_level_ack_pending(data->chip_data))
1742 irq_move_masked_irq(data);
1743 /* If the IRQ is masked in the core, leave it: */
1744 if (!irqd_irq_masked(data))
1745 unmask_ioapic_irq(data);
1749 static inline bool ioapic_irqd_mask(struct irq_data *data)
1753 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1758 static void ioapic_ack_level(struct irq_data *irq_data)
1760 struct irq_cfg *cfg = irqd_cfg(irq_data);
1765 irq_complete_move(cfg);
1766 masked = ioapic_irqd_mask(irq_data);
1769 * It appears there is an erratum which affects at least version 0x11
1770 * of I/O APIC (that's the 82093AA and cores integrated into various
1771 * chipsets). Under certain conditions a level-triggered interrupt is
1772 * erroneously delivered as edge-triggered one but the respective IRR
1773 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1774 * message but it will never arrive and further interrupts are blocked
1775 * from the source. The exact reason is so far unknown, but the
1776 * phenomenon was observed when two consecutive interrupt requests
1777 * from a given source get delivered to the same CPU and the source is
1778 * temporarily disabled in between.
1780 * A workaround is to simulate an EOI message manually. We achieve it
1781 * by setting the trigger mode to edge and then to level when the edge
1782 * trigger mode gets detected in the TMR of a local APIC for a
1783 * level-triggered interrupt. We mask the source for the time of the
1784 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1785 * The idea is from Manfred Spraul. --macro
1787 * Also in the case when cpu goes offline, fixup_irqs() will forward
1788 * any unhandled interrupt on the offlined cpu to the new cpu
1789 * destination that is handling the corresponding interrupt. This
1790 * interrupt forwarding is done via IPI's. Hence, in this case also
1791 * level-triggered io-apic interrupt will be seen as an edge
1792 * interrupt in the IRR. And we can't rely on the cpu's EOI
1793 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1794 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1795 * supporting EOI register, we do an explicit EOI to clear the
1796 * remote IRR and on IO-APIC's which don't have an EOI register,
1797 * we use the above logic (mask+edge followed by unmask+level) from
1798 * Manfred Spraul to clear the remote IRR.
1801 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1804 * We must acknowledge the irq before we move it or the acknowledge will
1805 * not propagate properly.
1810 * Tail end of clearing remote IRR bit (either by delivering the EOI
1811 * message via io-apic EOI register write or simulating it using
1812 * mask+edge followed by unnask+level logic) manually when the
1813 * level triggered interrupt is seen as the edge triggered interrupt
1816 if (!(v & (1 << (i & 0x1f)))) {
1817 atomic_inc(&irq_mis_count);
1818 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1821 ioapic_irqd_unmask(irq_data, masked);
1824 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1826 struct mp_chip_data *data = irq_data->chip_data;
1829 * Intr-remapping uses pin number as the virtual vector
1830 * in the RTE. Actual vector is programmed in
1831 * intr-remapping table entry. Hence for the io-apic
1832 * EOI we use the pin number.
1835 eoi_ioapic_pin(data->entry.vector, data);
1838 static int ioapic_set_affinity(struct irq_data *irq_data,
1839 const struct cpumask *mask, bool force)
1841 struct irq_data *parent = irq_data->parent_data;
1842 struct mp_chip_data *data = irq_data->chip_data;
1843 struct irq_pin_list *entry;
1844 struct irq_cfg *cfg;
1845 unsigned long flags;
1848 ret = parent->chip->irq_set_affinity(parent, mask, force);
1849 raw_spin_lock_irqsave(&ioapic_lock, flags);
1850 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1851 cfg = irqd_cfg(irq_data);
1852 data->entry.dest = cfg->dest_apicid;
1853 data->entry.vector = cfg->vector;
1854 for_each_irq_pin(entry, data->irq_2_pin)
1855 __ioapic_write_entry(entry->apic, entry->pin,
1858 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1863 static struct irq_chip ioapic_chip __read_mostly = {
1865 .irq_startup = startup_ioapic_irq,
1866 .irq_mask = mask_ioapic_irq,
1867 .irq_unmask = unmask_ioapic_irq,
1868 .irq_ack = irq_chip_ack_parent,
1869 .irq_eoi = ioapic_ack_level,
1870 .irq_set_affinity = ioapic_set_affinity,
1871 .irq_retrigger = irq_chip_retrigger_hierarchy,
1872 .flags = IRQCHIP_SKIP_SET_WAKE,
1875 static struct irq_chip ioapic_ir_chip __read_mostly = {
1876 .name = "IR-IO-APIC",
1877 .irq_startup = startup_ioapic_irq,
1878 .irq_mask = mask_ioapic_irq,
1879 .irq_unmask = unmask_ioapic_irq,
1880 .irq_ack = irq_chip_ack_parent,
1881 .irq_eoi = ioapic_ir_ack_level,
1882 .irq_set_affinity = ioapic_set_affinity,
1883 .irq_retrigger = irq_chip_retrigger_hierarchy,
1884 .flags = IRQCHIP_SKIP_SET_WAKE,
1887 static inline void init_IO_APIC_traps(void)
1889 struct irq_cfg *cfg;
1892 for_each_active_irq(irq) {
1894 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1896 * Hmm.. We don't have an entry for this,
1897 * so default to an old-fashioned 8259
1898 * interrupt if we can..
1900 if (irq < nr_legacy_irqs())
1901 legacy_pic->make_irq(irq);
1903 /* Strange. Oh, well.. */
1904 irq_set_chip(irq, &no_irq_chip);
1910 * The local APIC irq-chip implementation:
1913 static void mask_lapic_irq(struct irq_data *data)
1917 v = apic_read(APIC_LVT0);
1918 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1921 static void unmask_lapic_irq(struct irq_data *data)
1925 v = apic_read(APIC_LVT0);
1926 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1929 static void ack_lapic_irq(struct irq_data *data)
1934 static struct irq_chip lapic_chip __read_mostly = {
1935 .name = "local-APIC",
1936 .irq_mask = mask_lapic_irq,
1937 .irq_unmask = unmask_lapic_irq,
1938 .irq_ack = ack_lapic_irq,
1941 static void lapic_register_intr(int irq)
1943 irq_clear_status_flags(irq, IRQ_LEVEL);
1944 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1949 * This looks a bit hackish but it's about the only one way of sending
1950 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1951 * not support the ExtINT mode, unfortunately. We need to send these
1952 * cycles as some i82489DX-based boards have glue logic that keeps the
1953 * 8259A interrupt line asserted until INTA. --macro
1955 static inline void __init unlock_ExtINT_logic(void)
1958 struct IO_APIC_route_entry entry0, entry1;
1959 unsigned char save_control, save_freq_select;
1961 pin = find_isa_irq_pin(8, mp_INT);
1966 apic = find_isa_irq_apic(8, mp_INT);
1972 entry0 = ioapic_read_entry(apic, pin);
1973 clear_IO_APIC_pin(apic, pin);
1975 memset(&entry1, 0, sizeof(entry1));
1977 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1978 entry1.mask = IOAPIC_UNMASKED;
1979 entry1.dest = hard_smp_processor_id();
1980 entry1.delivery_mode = dest_ExtINT;
1981 entry1.polarity = entry0.polarity;
1982 entry1.trigger = IOAPIC_EDGE;
1985 ioapic_write_entry(apic, pin, entry1);
1987 save_control = CMOS_READ(RTC_CONTROL);
1988 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1989 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1991 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1996 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2000 CMOS_WRITE(save_control, RTC_CONTROL);
2001 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2002 clear_IO_APIC_pin(apic, pin);
2004 ioapic_write_entry(apic, pin, entry0);
2007 static int disable_timer_pin_1 __initdata;
2008 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2009 static int __init disable_timer_pin_setup(char *arg)
2011 disable_timer_pin_1 = 1;
2014 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2016 static int mp_alloc_timer_irq(int ioapic, int pin)
2019 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2022 struct irq_alloc_info info;
2024 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2025 info.ioapic_id = mpc_ioapic_id(ioapic);
2026 info.ioapic_pin = pin;
2027 mutex_lock(&ioapic_mutex);
2028 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2029 mutex_unlock(&ioapic_mutex);
2036 * This code may look a bit paranoid, but it's supposed to cooperate with
2037 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2038 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2039 * fanatically on his truly buggy board.
2041 * FIXME: really need to revamp this for all platforms.
2043 static inline void __init check_timer(void)
2045 struct irq_data *irq_data = irq_get_irq_data(0);
2046 struct mp_chip_data *data = irq_data->chip_data;
2047 struct irq_cfg *cfg = irqd_cfg(irq_data);
2048 int node = cpu_to_node(0);
2049 int apic1, pin1, apic2, pin2;
2050 unsigned long flags;
2053 local_irq_save(flags);
2056 * get/set the timer IRQ vector:
2058 legacy_pic->mask(0);
2061 * As IRQ0 is to be enabled in the 8259A, the virtual
2062 * wire has to be disabled in the local APIC. Also
2063 * timer interrupts need to be acknowledged manually in
2064 * the 8259A for the i82489DX when using the NMI
2065 * watchdog as that APIC treats NMIs as level-triggered.
2066 * The AEOI mode will finish them in the 8259A
2069 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2070 legacy_pic->init(1);
2072 pin1 = find_isa_irq_pin(0, mp_INT);
2073 apic1 = find_isa_irq_apic(0, mp_INT);
2074 pin2 = ioapic_i8259.pin;
2075 apic2 = ioapic_i8259.apic;
2077 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2078 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2079 cfg->vector, apic1, pin1, apic2, pin2);
2082 * Some BIOS writers are clueless and report the ExtINTA
2083 * I/O APIC input from the cascaded 8259A as the timer
2084 * interrupt input. So just in case, if only one pin
2085 * was found above, try it both directly and through the
2089 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2093 } else if (pin2 == -1) {
2099 /* Ok, does IRQ0 through the IOAPIC work? */
2101 mp_alloc_timer_irq(apic1, pin1);
2104 * for edge trigger, it's already unmasked,
2105 * so only need to unmask if it is level-trigger
2106 * do we really have level trigger timer?
2109 idx = find_irq_entry(apic1, pin1, mp_INT);
2110 if (idx != -1 && irq_trigger(idx))
2111 unmask_ioapic_irq(irq_get_irq_data(0));
2113 irq_domain_deactivate_irq(irq_data);
2114 irq_domain_activate_irq(irq_data);
2115 if (timer_irq_works()) {
2116 if (disable_timer_pin_1 > 0)
2117 clear_IO_APIC_pin(0, pin1);
2120 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2121 local_irq_disable();
2122 clear_IO_APIC_pin(apic1, pin1);
2124 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2125 "8254 timer not connected to IO-APIC\n");
2127 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2128 "(IRQ0) through the 8259A ...\n");
2129 apic_printk(APIC_QUIET, KERN_INFO
2130 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2132 * legacy devices should be connected to IO APIC #0
2134 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2135 irq_domain_deactivate_irq(irq_data);
2136 irq_domain_activate_irq(irq_data);
2137 legacy_pic->unmask(0);
2138 if (timer_irq_works()) {
2139 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2143 * Cleanup, just in case ...
2145 local_irq_disable();
2146 legacy_pic->mask(0);
2147 clear_IO_APIC_pin(apic2, pin2);
2148 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2151 apic_printk(APIC_QUIET, KERN_INFO
2152 "...trying to set up timer as Virtual Wire IRQ...\n");
2154 lapic_register_intr(0);
2155 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2156 legacy_pic->unmask(0);
2158 if (timer_irq_works()) {
2159 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2162 local_irq_disable();
2163 legacy_pic->mask(0);
2164 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2165 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2167 apic_printk(APIC_QUIET, KERN_INFO
2168 "...trying to set up timer as ExtINT IRQ...\n");
2170 legacy_pic->init(0);
2171 legacy_pic->make_irq(0);
2172 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2173 legacy_pic->unmask(0);
2175 unlock_ExtINT_logic();
2177 if (timer_irq_works()) {
2178 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2181 local_irq_disable();
2182 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2183 if (apic_is_x2apic_enabled())
2184 apic_printk(APIC_QUIET, KERN_INFO
2185 "Perhaps problem with the pre-enabled x2apic mode\n"
2186 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2187 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2188 "report. Then try booting with the 'noapic' option.\n");
2190 local_irq_restore(flags);
2194 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2195 * to devices. However there may be an I/O APIC pin available for
2196 * this interrupt regardless. The pin may be left unconnected, but
2197 * typically it will be reused as an ExtINT cascade interrupt for
2198 * the master 8259A. In the MPS case such a pin will normally be
2199 * reported as an ExtINT interrupt in the MP table. With ACPI
2200 * there is no provision for ExtINT interrupts, and in the absence
2201 * of an override it would be treated as an ordinary ISA I/O APIC
2202 * interrupt, that is edge-triggered and unmasked by default. We
2203 * used to do this, but it caused problems on some systems because
2204 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2205 * the same ExtINT cascade interrupt to drive the local APIC of the
2206 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2207 * the I/O APIC in all cases now. No actual device should request
2208 * it anyway. --macro
2210 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2212 static int mp_irqdomain_create(int ioapic)
2214 struct irq_alloc_info info;
2215 struct irq_domain *parent;
2216 int hwirqs = mp_ioapic_pin_count(ioapic);
2217 struct ioapic *ip = &ioapics[ioapic];
2218 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2219 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2220 struct fwnode_handle *fn;
2221 char *name = "IO-APIC";
2223 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2226 init_irq_alloc_info(&info, NULL);
2227 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2228 info.ioapic_id = mpc_ioapic_id(ioapic);
2229 parent = irq_remapping_get_ir_irq_domain(&info);
2231 parent = x86_vector_domain;
2233 name = "IO-APIC-IR";
2235 /* Handle device tree enumerated APICs proper */
2237 fn = of_node_to_fwnode(cfg->dev);
2239 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2244 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2245 (void *)(long)ioapic);
2247 if (!ip->irqdomain) {
2248 /* Release fw handle if it was allocated above */
2250 irq_domain_free_fwnode(fn);
2254 ip->irqdomain->parent = parent;
2256 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2257 cfg->type == IOAPIC_DOMAIN_STRICT)
2258 ioapic_dynirq_base = max(ioapic_dynirq_base,
2259 gsi_cfg->gsi_end + 1);
2264 static void ioapic_destroy_irqdomain(int idx)
2266 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2267 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2269 if (ioapics[idx].irqdomain) {
2270 irq_domain_remove(ioapics[idx].irqdomain);
2272 irq_domain_free_fwnode(fn);
2273 ioapics[idx].irqdomain = NULL;
2277 void __init setup_IO_APIC(void)
2281 if (skip_ioapic_setup || !nr_ioapics)
2284 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2286 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2287 for_each_ioapic(ioapic)
2288 BUG_ON(mp_irqdomain_create(ioapic));
2291 * Set up IO-APIC IRQ routing.
2293 x86_init.mpparse.setup_ioapic_ids();
2296 setup_IO_APIC_irqs();
2297 init_IO_APIC_traps();
2298 if (nr_legacy_irqs())
2301 ioapic_initialized = 1;
2304 static void resume_ioapic_id(int ioapic_idx)
2306 unsigned long flags;
2307 union IO_APIC_reg_00 reg_00;
2309 raw_spin_lock_irqsave(&ioapic_lock, flags);
2310 reg_00.raw = io_apic_read(ioapic_idx, 0);
2311 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2312 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2313 io_apic_write(ioapic_idx, 0, reg_00.raw);
2315 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2318 static void ioapic_resume(void)
2322 for_each_ioapic_reverse(ioapic_idx)
2323 resume_ioapic_id(ioapic_idx);
2325 restore_ioapic_entries();
2328 static struct syscore_ops ioapic_syscore_ops = {
2329 .suspend = save_ioapic_entries,
2330 .resume = ioapic_resume,
2333 static int __init ioapic_init_ops(void)
2335 register_syscore_ops(&ioapic_syscore_ops);
2340 device_initcall(ioapic_init_ops);
2342 static int io_apic_get_redir_entries(int ioapic)
2344 union IO_APIC_reg_01 reg_01;
2345 unsigned long flags;
2347 raw_spin_lock_irqsave(&ioapic_lock, flags);
2348 reg_01.raw = io_apic_read(ioapic, 1);
2349 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2351 /* The register returns the maximum index redir index
2352 * supported, which is one less than the total number of redir
2355 return reg_01.bits.entries + 1;
2358 unsigned int arch_dynirq_lower_bound(unsigned int from)
2361 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2362 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2364 if (!ioapic_initialized)
2367 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2368 * updated. So simply return @from if ioapic_dynirq_base == 0.
2370 return ioapic_dynirq_base ? : from;
2373 #ifdef CONFIG_X86_32
2374 static int io_apic_get_unique_id(int ioapic, int apic_id)
2376 union IO_APIC_reg_00 reg_00;
2377 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2379 unsigned long flags;
2383 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2384 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2385 * supports up to 16 on one shared APIC bus.
2387 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2388 * advantage of new APIC bus architecture.
2391 if (physids_empty(apic_id_map))
2392 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2394 raw_spin_lock_irqsave(&ioapic_lock, flags);
2395 reg_00.raw = io_apic_read(ioapic, 0);
2396 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2398 if (apic_id >= get_physical_broadcast()) {
2399 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2400 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2401 apic_id = reg_00.bits.ID;
2405 * Every APIC in a system must have a unique ID or we get lots of nice
2406 * 'stuck on smp_invalidate_needed IPI wait' messages.
2408 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2410 for (i = 0; i < get_physical_broadcast(); i++) {
2411 if (!apic->check_apicid_used(&apic_id_map, i))
2415 if (i == get_physical_broadcast())
2416 panic("Max apic_id exceeded!\n");
2418 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2419 "trying %d\n", ioapic, apic_id, i);
2424 apic->apicid_to_cpu_present(apic_id, &tmp);
2425 physids_or(apic_id_map, apic_id_map, tmp);
2427 if (reg_00.bits.ID != apic_id) {
2428 reg_00.bits.ID = apic_id;
2430 raw_spin_lock_irqsave(&ioapic_lock, flags);
2431 io_apic_write(ioapic, 0, reg_00.raw);
2432 reg_00.raw = io_apic_read(ioapic, 0);
2433 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2436 if (reg_00.bits.ID != apic_id) {
2437 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2443 apic_printk(APIC_VERBOSE, KERN_INFO
2444 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2449 static u8 io_apic_unique_id(int idx, u8 id)
2451 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2452 !APIC_XAPIC(boot_cpu_apic_version))
2453 return io_apic_get_unique_id(idx, id);
2458 static u8 io_apic_unique_id(int idx, u8 id)
2460 union IO_APIC_reg_00 reg_00;
2461 DECLARE_BITMAP(used, 256);
2462 unsigned long flags;
2466 bitmap_zero(used, 256);
2468 __set_bit(mpc_ioapic_id(i), used);
2470 /* Hand out the requested id if available */
2471 if (!test_bit(id, used))
2475 * Read the current id from the ioapic and keep it if
2478 raw_spin_lock_irqsave(&ioapic_lock, flags);
2479 reg_00.raw = io_apic_read(idx, 0);
2480 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2481 new_id = reg_00.bits.ID;
2482 if (!test_bit(new_id, used)) {
2483 apic_printk(APIC_VERBOSE, KERN_INFO
2484 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2490 * Get the next free id and write it to the ioapic.
2492 new_id = find_first_zero_bit(used, 256);
2493 reg_00.bits.ID = new_id;
2494 raw_spin_lock_irqsave(&ioapic_lock, flags);
2495 io_apic_write(idx, 0, reg_00.raw);
2496 reg_00.raw = io_apic_read(idx, 0);
2497 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2499 BUG_ON(reg_00.bits.ID != new_id);
2505 static int io_apic_get_version(int ioapic)
2507 union IO_APIC_reg_01 reg_01;
2508 unsigned long flags;
2510 raw_spin_lock_irqsave(&ioapic_lock, flags);
2511 reg_01.raw = io_apic_read(ioapic, 1);
2512 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2514 return reg_01.bits.version;
2517 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2519 int ioapic, pin, idx;
2521 if (skip_ioapic_setup)
2524 ioapic = mp_find_ioapic(gsi);
2528 pin = mp_find_ioapic_pin(ioapic, gsi);
2532 idx = find_irq_entry(ioapic, pin, mp_INT);
2536 *trigger = irq_trigger(idx);
2537 *polarity = irq_polarity(idx);
2542 * This function currently is only a helper for the i386 smp boot process where
2543 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2544 * so mask in all cases should simply be apic->target_cpus()
2547 void __init setup_ioapic_dest(void)
2549 int pin, ioapic, irq, irq_entry;
2550 const struct cpumask *mask;
2551 struct irq_desc *desc;
2552 struct irq_data *idata;
2553 struct irq_chip *chip;
2555 if (skip_ioapic_setup == 1)
2558 for_each_ioapic_pin(ioapic, pin) {
2559 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2560 if (irq_entry == -1)
2563 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2564 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2567 desc = irq_to_desc(irq);
2568 raw_spin_lock_irq(&desc->lock);
2569 idata = irq_desc_get_irq_data(desc);
2572 * Honour affinities which have been set in early boot
2574 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2575 mask = irq_data_get_affinity_mask(idata);
2577 mask = apic->target_cpus();
2579 chip = irq_data_get_irq_chip(idata);
2580 /* Might be lapic_chip for irq 0 */
2581 if (chip->irq_set_affinity)
2582 chip->irq_set_affinity(idata, mask, false);
2583 raw_spin_unlock_irq(&desc->lock);
2588 #define IOAPIC_RESOURCE_NAME_SIZE 11
2590 static struct resource *ioapic_resources;
2592 static struct resource * __init ioapic_setup_resources(void)
2595 struct resource *res;
2599 if (nr_ioapics == 0)
2602 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2605 mem = alloc_bootmem(n);
2608 mem += sizeof(struct resource) * nr_ioapics;
2610 for_each_ioapic(i) {
2612 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2613 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2614 mem += IOAPIC_RESOURCE_NAME_SIZE;
2615 ioapics[i].iomem_res = &res[i];
2618 ioapic_resources = res;
2623 void __init io_apic_init_mappings(void)
2625 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2626 struct resource *ioapic_res;
2629 ioapic_res = ioapic_setup_resources();
2630 for_each_ioapic(i) {
2631 if (smp_found_config) {
2632 ioapic_phys = mpc_ioapic_addr(i);
2633 #ifdef CONFIG_X86_32
2636 "WARNING: bogus zero IO-APIC "
2637 "address found in MPTABLE, "
2638 "disabling IO/APIC support!\n");
2639 smp_found_config = 0;
2640 skip_ioapic_setup = 1;
2641 goto fake_ioapic_page;
2645 #ifdef CONFIG_X86_32
2648 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2649 ioapic_phys = __pa(ioapic_phys);
2651 set_fixmap_nocache(idx, ioapic_phys);
2652 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2653 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2657 ioapic_res->start = ioapic_phys;
2658 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2663 void __init ioapic_insert_resources(void)
2666 struct resource *r = ioapic_resources;
2671 "IO APIC resources couldn't be allocated.\n");
2675 for_each_ioapic(i) {
2676 insert_resource(&iomem_resource, r);
2681 int mp_find_ioapic(u32 gsi)
2685 if (nr_ioapics == 0)
2688 /* Find the IOAPIC that manages this GSI. */
2689 for_each_ioapic(i) {
2690 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2691 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2695 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2699 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2701 struct mp_ioapic_gsi *gsi_cfg;
2703 if (WARN_ON(ioapic < 0))
2706 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2707 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2710 return gsi - gsi_cfg->gsi_base;
2713 static int bad_ioapic_register(int idx)
2715 union IO_APIC_reg_00 reg_00;
2716 union IO_APIC_reg_01 reg_01;
2717 union IO_APIC_reg_02 reg_02;
2719 reg_00.raw = io_apic_read(idx, 0);
2720 reg_01.raw = io_apic_read(idx, 1);
2721 reg_02.raw = io_apic_read(idx, 2);
2723 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2724 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2725 mpc_ioapic_addr(idx));
2732 static int find_free_ioapic_entry(void)
2736 for (idx = 0; idx < MAX_IO_APICS; idx++)
2737 if (ioapics[idx].nr_registers == 0)
2740 return MAX_IO_APICS;
2744 * mp_register_ioapic - Register an IOAPIC device
2745 * @id: hardware IOAPIC ID
2746 * @address: physical address of IOAPIC register area
2747 * @gsi_base: base of GSI associated with the IOAPIC
2748 * @cfg: configuration information for the IOAPIC
2750 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2751 struct ioapic_domain_cfg *cfg)
2753 bool hotplug = !!ioapic_initialized;
2754 struct mp_ioapic_gsi *gsi_cfg;
2755 int idx, ioapic, entries;
2759 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2762 for_each_ioapic(ioapic)
2763 if (ioapics[ioapic].mp_config.apicaddr == address) {
2764 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2769 idx = find_free_ioapic_entry();
2770 if (idx >= MAX_IO_APICS) {
2771 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2776 ioapics[idx].mp_config.type = MP_IOAPIC;
2777 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2778 ioapics[idx].mp_config.apicaddr = address;
2780 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2781 if (bad_ioapic_register(idx)) {
2782 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2786 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2787 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2790 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2791 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2793 entries = io_apic_get_redir_entries(idx);
2794 gsi_end = gsi_base + entries - 1;
2795 for_each_ioapic(ioapic) {
2796 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2797 if ((gsi_base >= gsi_cfg->gsi_base &&
2798 gsi_base <= gsi_cfg->gsi_end) ||
2799 (gsi_end >= gsi_cfg->gsi_base &&
2800 gsi_end <= gsi_cfg->gsi_end)) {
2801 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2803 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2804 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2808 gsi_cfg = mp_ioapic_gsi_routing(idx);
2809 gsi_cfg->gsi_base = gsi_base;
2810 gsi_cfg->gsi_end = gsi_end;
2812 ioapics[idx].irqdomain = NULL;
2813 ioapics[idx].irqdomain_cfg = *cfg;
2816 * If mp_register_ioapic() is called during early boot stage when
2817 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2818 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2821 if (mp_irqdomain_create(idx)) {
2822 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2825 alloc_ioapic_saved_registers(idx);
2828 if (gsi_cfg->gsi_end >= gsi_top)
2829 gsi_top = gsi_cfg->gsi_end + 1;
2830 if (nr_ioapics <= idx)
2831 nr_ioapics = idx + 1;
2833 /* Set nr_registers to mark entry present */
2834 ioapics[idx].nr_registers = entries;
2836 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2837 idx, mpc_ioapic_id(idx),
2838 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2839 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2844 int mp_unregister_ioapic(u32 gsi_base)
2849 for_each_ioapic(ioapic)
2850 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2855 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2859 for_each_pin(ioapic, pin) {
2860 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2861 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2862 struct mp_chip_data *data;
2865 data = irq_get_chip_data(irq);
2866 if (data && data->count) {
2867 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2874 /* Mark entry not present */
2875 ioapics[ioapic].nr_registers = 0;
2876 ioapic_destroy_irqdomain(ioapic);
2877 free_ioapic_saved_registers(ioapic);
2878 if (ioapics[ioapic].iomem_res)
2879 release_resource(ioapics[ioapic].iomem_res);
2880 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2881 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2886 int mp_ioapic_registered(u32 gsi_base)
2890 for_each_ioapic(ioapic)
2891 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2897 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2898 struct irq_alloc_info *info)
2900 if (info && info->ioapic_valid) {
2901 data->trigger = info->ioapic_trigger;
2902 data->polarity = info->ioapic_polarity;
2903 } else if (acpi_get_override_irq(gsi, &data->trigger,
2904 &data->polarity) < 0) {
2905 /* PCI interrupts are always active low level triggered. */
2906 data->trigger = IOAPIC_LEVEL;
2907 data->polarity = IOAPIC_POL_LOW;
2911 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2912 struct IO_APIC_route_entry *entry)
2914 memset(entry, 0, sizeof(*entry));
2915 entry->delivery_mode = apic->irq_delivery_mode;
2916 entry->dest_mode = apic->irq_dest_mode;
2917 entry->dest = cfg->dest_apicid;
2918 entry->vector = cfg->vector;
2919 entry->trigger = data->trigger;
2920 entry->polarity = data->polarity;
2922 * Mask level triggered irqs. Edge triggered irqs are masked
2923 * by the irq core code in case they fire.
2925 if (data->trigger == IOAPIC_LEVEL)
2926 entry->mask = IOAPIC_MASKED;
2928 entry->mask = IOAPIC_UNMASKED;
2931 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2932 unsigned int nr_irqs, void *arg)
2934 int ret, ioapic, pin;
2935 struct irq_cfg *cfg;
2936 struct irq_data *irq_data;
2937 struct mp_chip_data *data;
2938 struct irq_alloc_info *info = arg;
2939 unsigned long flags;
2941 if (!info || nr_irqs > 1)
2943 irq_data = irq_domain_get_irq_data(domain, virq);
2947 ioapic = mp_irqdomain_ioapic_idx(domain);
2948 pin = info->ioapic_pin;
2949 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2952 data = kzalloc(sizeof(*data), GFP_KERNEL);
2956 info->ioapic_entry = &data->entry;
2957 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2963 INIT_LIST_HEAD(&data->irq_2_pin);
2964 irq_data->hwirq = info->ioapic_pin;
2965 irq_data->chip = (domain->parent == x86_vector_domain) ?
2966 &ioapic_chip : &ioapic_ir_chip;
2967 irq_data->chip_data = data;
2968 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2970 cfg = irqd_cfg(irq_data);
2971 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2973 local_irq_save(flags);
2974 if (info->ioapic_entry)
2975 mp_setup_entry(cfg, data, info->ioapic_entry);
2976 mp_register_handler(virq, data->trigger);
2977 if (virq < nr_legacy_irqs())
2978 legacy_pic->mask(virq);
2979 local_irq_restore(flags);
2981 apic_printk(APIC_VERBOSE, KERN_DEBUG
2982 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2983 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2984 virq, data->trigger, data->polarity, cfg->dest_apicid);
2989 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2990 unsigned int nr_irqs)
2992 struct irq_data *irq_data;
2993 struct mp_chip_data *data;
2995 BUG_ON(nr_irqs != 1);
2996 irq_data = irq_domain_get_irq_data(domain, virq);
2997 if (irq_data && irq_data->chip_data) {
2998 data = irq_data->chip_data;
2999 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3000 (int)irq_data->hwirq);
3001 WARN_ON(!list_empty(&data->irq_2_pin));
3002 kfree(irq_data->chip_data);
3004 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3007 void mp_irqdomain_activate(struct irq_domain *domain,
3008 struct irq_data *irq_data)
3010 unsigned long flags;
3011 struct irq_pin_list *entry;
3012 struct mp_chip_data *data = irq_data->chip_data;
3014 raw_spin_lock_irqsave(&ioapic_lock, flags);
3015 for_each_irq_pin(entry, data->irq_2_pin)
3016 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
3017 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3020 void mp_irqdomain_deactivate(struct irq_domain *domain,
3021 struct irq_data *irq_data)
3023 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3024 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3025 (int)irq_data->hwirq);
3028 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3030 return (int)(long)domain->host_data;
3033 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3034 .alloc = mp_irqdomain_alloc,
3035 .free = mp_irqdomain_free,
3036 .activate = mp_irqdomain_activate,
3037 .deactivate = mp_irqdomain_deactivate,