1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
11 * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
20 * All CPUs have same idle states as boot CPU
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-states
25 * CPU will flush caches as needed when entering a C-state via MWAIT
26 * (in contrast to entering ACPI C3, in which case the WBINVD
27 * instruction needs to be executed to flush the caches)
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
34 * to avoid complications with the lapic timer workaround.
35 * Have not seen issues with suspend, but may need same workaround here.
39 /* un-comment DEBUG to enable pr_debug() statements */
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/acpi.h>
45 #include <linux/kernel.h>
46 #include <linux/cpuidle.h>
47 #include <linux/tick.h>
48 #include <trace/events/power.h>
49 #include <linux/sched.h>
50 #include <linux/sched/smt.h>
51 #include <linux/notifier.h>
52 #include <linux/cpu.h>
53 #include <linux/moduleparam.h>
54 #include <asm/cpu_device_id.h>
55 #include <asm/intel-family.h>
56 #include <asm/nospec-branch.h>
57 #include <asm/mwait.h>
60 #define INTEL_IDLE_VERSION "0.5.1"
62 static struct cpuidle_driver intel_idle_driver = {
66 /* intel_idle.max_cstate=0 disables driver */
67 static int max_cstate = CPUIDLE_STATE_MAX - 1;
68 static unsigned int disabled_states_mask;
70 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
72 static unsigned long auto_demotion_disable_flags;
73 static bool disable_promotion_to_c1e;
76 struct cpuidle_state *state_table;
79 * Hardware C-state auto-demotion may not always be optimal.
80 * Indicate which enable bits to clear here.
82 unsigned long auto_demotion_disable_flags;
83 bool byt_auto_demotion_disable_flag;
84 bool disable_promotion_to_c1e;
88 static const struct idle_cpu *icpu __initdata;
89 static struct cpuidle_state *cpuidle_state_table __initdata;
91 static unsigned int mwait_substates __initdata;
94 * Enable this state by default even if the ACPI _CST does not list it.
96 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
99 * Disable IBRS across idle (when KERNEL_IBRS), is exclusive vs IRQ_ENABLE
102 #define CPUIDLE_FLAG_IBRS BIT(16)
105 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
106 * the C-state (top nibble) and sub-state (bottom nibble)
107 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
109 * We store the hint at the top of our "flags" for each state.
111 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
112 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
115 * intel_idle - Ask the processor to enter the given idle state.
116 * @dev: cpuidle device of the target CPU.
117 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
118 * @index: Target idle state index.
120 * Use the MWAIT instruction to notify the processor that the CPU represented by
121 * @dev is idle and it can try to enter the idle state corresponding to @index.
123 * If the local APIC timer is not known to be reliable in the target idle state,
124 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
126 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
127 * flushing user TLBs.
129 * Must be called under local_irq_disable().
131 static __cpuidle int intel_idle(struct cpuidle_device *dev,
132 struct cpuidle_driver *drv, int index)
134 struct cpuidle_state *state = &drv->states[index];
135 unsigned long eax = flg2MWAIT(state->flags);
136 unsigned long ecx = 1; /* break on interrupt flag */
138 mwait_idle_with_hints(eax, ecx);
143 static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
144 struct cpuidle_driver *drv, int index)
146 bool smt_active = sched_smt_active();
147 u64 spec_ctrl = spec_ctrl_current();
151 wrmsrl(MSR_IA32_SPEC_CTRL, 0);
153 ret = intel_idle(dev, drv, index);
156 wrmsrl(MSR_IA32_SPEC_CTRL, spec_ctrl);
162 * intel_idle_s2idle - Ask the processor to enter the given idle state.
163 * @dev: cpuidle device of the target CPU.
164 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
165 * @index: Target idle state index.
167 * Use the MWAIT instruction to notify the processor that the CPU represented by
168 * @dev is idle and it can try to enter the idle state corresponding to @index.
170 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
171 * scheduler tick and suspended scheduler clock on the target CPU.
173 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
174 struct cpuidle_driver *drv, int index)
176 unsigned long eax = flg2MWAIT(drv->states[index].flags);
177 unsigned long ecx = 1; /* break on interrupt flag */
179 mwait_idle_with_hints(eax, ecx);
185 * States are indexed by the cstate number,
186 * which is also the index into the MWAIT hint array.
187 * Thus C0 is a dummy.
189 static struct cpuidle_state nehalem_cstates[] __initdata = {
192 .desc = "MWAIT 0x00",
193 .flags = MWAIT2flg(0x00),
195 .target_residency = 6,
196 .enter = &intel_idle,
197 .enter_s2idle = intel_idle_s2idle, },
200 .desc = "MWAIT 0x01",
201 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
203 .target_residency = 20,
204 .enter = &intel_idle,
205 .enter_s2idle = intel_idle_s2idle, },
208 .desc = "MWAIT 0x10",
209 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
211 .target_residency = 80,
212 .enter = &intel_idle,
213 .enter_s2idle = intel_idle_s2idle, },
216 .desc = "MWAIT 0x20",
217 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
219 .target_residency = 800,
220 .enter = &intel_idle,
221 .enter_s2idle = intel_idle_s2idle, },
226 static struct cpuidle_state snb_cstates[] __initdata = {
229 .desc = "MWAIT 0x00",
230 .flags = MWAIT2flg(0x00),
232 .target_residency = 2,
233 .enter = &intel_idle,
234 .enter_s2idle = intel_idle_s2idle, },
237 .desc = "MWAIT 0x01",
238 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
240 .target_residency = 20,
241 .enter = &intel_idle,
242 .enter_s2idle = intel_idle_s2idle, },
245 .desc = "MWAIT 0x10",
246 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
248 .target_residency = 211,
249 .enter = &intel_idle,
250 .enter_s2idle = intel_idle_s2idle, },
253 .desc = "MWAIT 0x20",
254 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
256 .target_residency = 345,
257 .enter = &intel_idle,
258 .enter_s2idle = intel_idle_s2idle, },
261 .desc = "MWAIT 0x30",
262 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
264 .target_residency = 345,
265 .enter = &intel_idle,
266 .enter_s2idle = intel_idle_s2idle, },
271 static struct cpuidle_state byt_cstates[] __initdata = {
274 .desc = "MWAIT 0x00",
275 .flags = MWAIT2flg(0x00),
277 .target_residency = 1,
278 .enter = &intel_idle,
279 .enter_s2idle = intel_idle_s2idle, },
282 .desc = "MWAIT 0x58",
283 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
285 .target_residency = 275,
286 .enter = &intel_idle,
287 .enter_s2idle = intel_idle_s2idle, },
290 .desc = "MWAIT 0x52",
291 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
293 .target_residency = 560,
294 .enter = &intel_idle,
295 .enter_s2idle = intel_idle_s2idle, },
298 .desc = "MWAIT 0x60",
299 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
300 .exit_latency = 1200,
301 .target_residency = 4000,
302 .enter = &intel_idle,
303 .enter_s2idle = intel_idle_s2idle, },
306 .desc = "MWAIT 0x64",
307 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
308 .exit_latency = 10000,
309 .target_residency = 20000,
310 .enter = &intel_idle,
311 .enter_s2idle = intel_idle_s2idle, },
316 static struct cpuidle_state cht_cstates[] __initdata = {
319 .desc = "MWAIT 0x00",
320 .flags = MWAIT2flg(0x00),
322 .target_residency = 1,
323 .enter = &intel_idle,
324 .enter_s2idle = intel_idle_s2idle, },
327 .desc = "MWAIT 0x58",
328 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
330 .target_residency = 275,
331 .enter = &intel_idle,
332 .enter_s2idle = intel_idle_s2idle, },
335 .desc = "MWAIT 0x52",
336 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
338 .target_residency = 560,
339 .enter = &intel_idle,
340 .enter_s2idle = intel_idle_s2idle, },
343 .desc = "MWAIT 0x60",
344 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
345 .exit_latency = 1200,
346 .target_residency = 4000,
347 .enter = &intel_idle,
348 .enter_s2idle = intel_idle_s2idle, },
351 .desc = "MWAIT 0x64",
352 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
353 .exit_latency = 10000,
354 .target_residency = 20000,
355 .enter = &intel_idle,
356 .enter_s2idle = intel_idle_s2idle, },
361 static struct cpuidle_state ivb_cstates[] __initdata = {
364 .desc = "MWAIT 0x00",
365 .flags = MWAIT2flg(0x00),
367 .target_residency = 1,
368 .enter = &intel_idle,
369 .enter_s2idle = intel_idle_s2idle, },
372 .desc = "MWAIT 0x01",
373 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
375 .target_residency = 20,
376 .enter = &intel_idle,
377 .enter_s2idle = intel_idle_s2idle, },
380 .desc = "MWAIT 0x10",
381 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
383 .target_residency = 156,
384 .enter = &intel_idle,
385 .enter_s2idle = intel_idle_s2idle, },
388 .desc = "MWAIT 0x20",
389 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
391 .target_residency = 300,
392 .enter = &intel_idle,
393 .enter_s2idle = intel_idle_s2idle, },
396 .desc = "MWAIT 0x30",
397 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
399 .target_residency = 300,
400 .enter = &intel_idle,
401 .enter_s2idle = intel_idle_s2idle, },
406 static struct cpuidle_state ivt_cstates[] __initdata = {
409 .desc = "MWAIT 0x00",
410 .flags = MWAIT2flg(0x00),
412 .target_residency = 1,
413 .enter = &intel_idle,
414 .enter_s2idle = intel_idle_s2idle, },
417 .desc = "MWAIT 0x01",
418 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
420 .target_residency = 80,
421 .enter = &intel_idle,
422 .enter_s2idle = intel_idle_s2idle, },
425 .desc = "MWAIT 0x10",
426 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
428 .target_residency = 156,
429 .enter = &intel_idle,
430 .enter_s2idle = intel_idle_s2idle, },
433 .desc = "MWAIT 0x20",
434 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
436 .target_residency = 300,
437 .enter = &intel_idle,
438 .enter_s2idle = intel_idle_s2idle, },
443 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
446 .desc = "MWAIT 0x00",
447 .flags = MWAIT2flg(0x00),
449 .target_residency = 1,
450 .enter = &intel_idle,
451 .enter_s2idle = intel_idle_s2idle, },
454 .desc = "MWAIT 0x01",
455 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
457 .target_residency = 250,
458 .enter = &intel_idle,
459 .enter_s2idle = intel_idle_s2idle, },
462 .desc = "MWAIT 0x10",
463 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
465 .target_residency = 300,
466 .enter = &intel_idle,
467 .enter_s2idle = intel_idle_s2idle, },
470 .desc = "MWAIT 0x20",
471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
473 .target_residency = 400,
474 .enter = &intel_idle,
475 .enter_s2idle = intel_idle_s2idle, },
480 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
483 .desc = "MWAIT 0x00",
484 .flags = MWAIT2flg(0x00),
486 .target_residency = 1,
487 .enter = &intel_idle,
488 .enter_s2idle = intel_idle_s2idle, },
491 .desc = "MWAIT 0x01",
492 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
494 .target_residency = 500,
495 .enter = &intel_idle,
496 .enter_s2idle = intel_idle_s2idle, },
499 .desc = "MWAIT 0x10",
500 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
502 .target_residency = 600,
503 .enter = &intel_idle,
504 .enter_s2idle = intel_idle_s2idle, },
507 .desc = "MWAIT 0x20",
508 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
510 .target_residency = 700,
511 .enter = &intel_idle,
512 .enter_s2idle = intel_idle_s2idle, },
517 static struct cpuidle_state hsw_cstates[] __initdata = {
520 .desc = "MWAIT 0x00",
521 .flags = MWAIT2flg(0x00),
523 .target_residency = 2,
524 .enter = &intel_idle,
525 .enter_s2idle = intel_idle_s2idle, },
528 .desc = "MWAIT 0x01",
529 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
531 .target_residency = 20,
532 .enter = &intel_idle,
533 .enter_s2idle = intel_idle_s2idle, },
536 .desc = "MWAIT 0x10",
537 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
539 .target_residency = 100,
540 .enter = &intel_idle,
541 .enter_s2idle = intel_idle_s2idle, },
544 .desc = "MWAIT 0x20",
545 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
547 .target_residency = 400,
548 .enter = &intel_idle,
549 .enter_s2idle = intel_idle_s2idle, },
552 .desc = "MWAIT 0x32",
553 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
555 .target_residency = 500,
556 .enter = &intel_idle,
557 .enter_s2idle = intel_idle_s2idle, },
560 .desc = "MWAIT 0x40",
561 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
563 .target_residency = 900,
564 .enter = &intel_idle,
565 .enter_s2idle = intel_idle_s2idle, },
568 .desc = "MWAIT 0x50",
569 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
571 .target_residency = 1800,
572 .enter = &intel_idle,
573 .enter_s2idle = intel_idle_s2idle, },
576 .desc = "MWAIT 0x60",
577 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
578 .exit_latency = 2600,
579 .target_residency = 7700,
580 .enter = &intel_idle,
581 .enter_s2idle = intel_idle_s2idle, },
585 static struct cpuidle_state bdw_cstates[] __initdata = {
588 .desc = "MWAIT 0x00",
589 .flags = MWAIT2flg(0x00),
591 .target_residency = 2,
592 .enter = &intel_idle,
593 .enter_s2idle = intel_idle_s2idle, },
596 .desc = "MWAIT 0x01",
597 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
599 .target_residency = 20,
600 .enter = &intel_idle,
601 .enter_s2idle = intel_idle_s2idle, },
604 .desc = "MWAIT 0x10",
605 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
607 .target_residency = 100,
608 .enter = &intel_idle,
609 .enter_s2idle = intel_idle_s2idle, },
612 .desc = "MWAIT 0x20",
613 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
615 .target_residency = 400,
616 .enter = &intel_idle,
617 .enter_s2idle = intel_idle_s2idle, },
620 .desc = "MWAIT 0x32",
621 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
623 .target_residency = 500,
624 .enter = &intel_idle,
625 .enter_s2idle = intel_idle_s2idle, },
628 .desc = "MWAIT 0x40",
629 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
631 .target_residency = 900,
632 .enter = &intel_idle,
633 .enter_s2idle = intel_idle_s2idle, },
636 .desc = "MWAIT 0x50",
637 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
639 .target_residency = 1800,
640 .enter = &intel_idle,
641 .enter_s2idle = intel_idle_s2idle, },
644 .desc = "MWAIT 0x60",
645 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
646 .exit_latency = 2600,
647 .target_residency = 7700,
648 .enter = &intel_idle,
649 .enter_s2idle = intel_idle_s2idle, },
654 static struct cpuidle_state skl_cstates[] __initdata = {
657 .desc = "MWAIT 0x00",
658 .flags = MWAIT2flg(0x00),
660 .target_residency = 2,
661 .enter = &intel_idle,
662 .enter_s2idle = intel_idle_s2idle, },
665 .desc = "MWAIT 0x01",
666 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
668 .target_residency = 20,
669 .enter = &intel_idle,
670 .enter_s2idle = intel_idle_s2idle, },
673 .desc = "MWAIT 0x10",
674 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
676 .target_residency = 100,
677 .enter = &intel_idle,
678 .enter_s2idle = intel_idle_s2idle, },
681 .desc = "MWAIT 0x20",
682 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
684 .target_residency = 200,
685 .enter = &intel_idle,
686 .enter_s2idle = intel_idle_s2idle, },
689 .desc = "MWAIT 0x33",
690 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
692 .target_residency = 800,
693 .enter = &intel_idle,
694 .enter_s2idle = intel_idle_s2idle, },
697 .desc = "MWAIT 0x40",
698 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
700 .target_residency = 800,
701 .enter = &intel_idle,
702 .enter_s2idle = intel_idle_s2idle, },
705 .desc = "MWAIT 0x50",
706 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
708 .target_residency = 5000,
709 .enter = &intel_idle,
710 .enter_s2idle = intel_idle_s2idle, },
713 .desc = "MWAIT 0x60",
714 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
716 .target_residency = 5000,
717 .enter = &intel_idle,
718 .enter_s2idle = intel_idle_s2idle, },
723 static struct cpuidle_state skx_cstates[] __initdata = {
726 .desc = "MWAIT 0x00",
727 .flags = MWAIT2flg(0x00),
729 .target_residency = 2,
730 .enter = &intel_idle,
731 .enter_s2idle = intel_idle_s2idle, },
734 .desc = "MWAIT 0x01",
735 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
737 .target_residency = 20,
738 .enter = &intel_idle,
739 .enter_s2idle = intel_idle_s2idle, },
742 .desc = "MWAIT 0x20",
743 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
745 .target_residency = 600,
746 .enter = &intel_idle,
747 .enter_s2idle = intel_idle_s2idle, },
752 static struct cpuidle_state icx_cstates[] __initdata = {
755 .desc = "MWAIT 0x00",
756 .flags = MWAIT2flg(0x00),
758 .target_residency = 1,
759 .enter = &intel_idle,
760 .enter_s2idle = intel_idle_s2idle, },
763 .desc = "MWAIT 0x01",
764 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
766 .target_residency = 4,
767 .enter = &intel_idle,
768 .enter_s2idle = intel_idle_s2idle, },
771 .desc = "MWAIT 0x20",
772 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
774 .target_residency = 384,
775 .enter = &intel_idle,
776 .enter_s2idle = intel_idle_s2idle, },
781 static struct cpuidle_state atom_cstates[] __initdata = {
784 .desc = "MWAIT 0x00",
785 .flags = MWAIT2flg(0x00),
787 .target_residency = 20,
788 .enter = &intel_idle,
789 .enter_s2idle = intel_idle_s2idle, },
792 .desc = "MWAIT 0x10",
793 .flags = MWAIT2flg(0x10),
795 .target_residency = 80,
796 .enter = &intel_idle,
797 .enter_s2idle = intel_idle_s2idle, },
800 .desc = "MWAIT 0x30",
801 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
803 .target_residency = 400,
804 .enter = &intel_idle,
805 .enter_s2idle = intel_idle_s2idle, },
808 .desc = "MWAIT 0x52",
809 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
811 .target_residency = 560,
812 .enter = &intel_idle,
813 .enter_s2idle = intel_idle_s2idle, },
817 static struct cpuidle_state tangier_cstates[] __initdata = {
820 .desc = "MWAIT 0x00",
821 .flags = MWAIT2flg(0x00),
823 .target_residency = 4,
824 .enter = &intel_idle,
825 .enter_s2idle = intel_idle_s2idle, },
828 .desc = "MWAIT 0x30",
829 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
831 .target_residency = 400,
832 .enter = &intel_idle,
833 .enter_s2idle = intel_idle_s2idle, },
836 .desc = "MWAIT 0x52",
837 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
839 .target_residency = 560,
840 .enter = &intel_idle,
841 .enter_s2idle = intel_idle_s2idle, },
844 .desc = "MWAIT 0x60",
845 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
846 .exit_latency = 1200,
847 .target_residency = 4000,
848 .enter = &intel_idle,
849 .enter_s2idle = intel_idle_s2idle, },
852 .desc = "MWAIT 0x64",
853 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
854 .exit_latency = 10000,
855 .target_residency = 20000,
856 .enter = &intel_idle,
857 .enter_s2idle = intel_idle_s2idle, },
861 static struct cpuidle_state avn_cstates[] __initdata = {
864 .desc = "MWAIT 0x00",
865 .flags = MWAIT2flg(0x00),
867 .target_residency = 2,
868 .enter = &intel_idle,
869 .enter_s2idle = intel_idle_s2idle, },
872 .desc = "MWAIT 0x51",
873 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
875 .target_residency = 45,
876 .enter = &intel_idle,
877 .enter_s2idle = intel_idle_s2idle, },
881 static struct cpuidle_state knl_cstates[] __initdata = {
884 .desc = "MWAIT 0x00",
885 .flags = MWAIT2flg(0x00),
887 .target_residency = 2,
888 .enter = &intel_idle,
889 .enter_s2idle = intel_idle_s2idle },
892 .desc = "MWAIT 0x10",
893 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
895 .target_residency = 500,
896 .enter = &intel_idle,
897 .enter_s2idle = intel_idle_s2idle },
902 static struct cpuidle_state bxt_cstates[] __initdata = {
905 .desc = "MWAIT 0x00",
906 .flags = MWAIT2flg(0x00),
908 .target_residency = 2,
909 .enter = &intel_idle,
910 .enter_s2idle = intel_idle_s2idle, },
913 .desc = "MWAIT 0x01",
914 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
916 .target_residency = 20,
917 .enter = &intel_idle,
918 .enter_s2idle = intel_idle_s2idle, },
921 .desc = "MWAIT 0x20",
922 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
924 .target_residency = 133,
925 .enter = &intel_idle,
926 .enter_s2idle = intel_idle_s2idle, },
929 .desc = "MWAIT 0x31",
930 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
932 .target_residency = 155,
933 .enter = &intel_idle,
934 .enter_s2idle = intel_idle_s2idle, },
937 .desc = "MWAIT 0x40",
938 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
939 .exit_latency = 1000,
940 .target_residency = 1000,
941 .enter = &intel_idle,
942 .enter_s2idle = intel_idle_s2idle, },
945 .desc = "MWAIT 0x50",
946 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
947 .exit_latency = 2000,
948 .target_residency = 2000,
949 .enter = &intel_idle,
950 .enter_s2idle = intel_idle_s2idle, },
953 .desc = "MWAIT 0x60",
954 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
955 .exit_latency = 10000,
956 .target_residency = 10000,
957 .enter = &intel_idle,
958 .enter_s2idle = intel_idle_s2idle, },
963 static struct cpuidle_state dnv_cstates[] __initdata = {
966 .desc = "MWAIT 0x00",
967 .flags = MWAIT2flg(0x00),
969 .target_residency = 2,
970 .enter = &intel_idle,
971 .enter_s2idle = intel_idle_s2idle, },
974 .desc = "MWAIT 0x01",
975 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
977 .target_residency = 20,
978 .enter = &intel_idle,
979 .enter_s2idle = intel_idle_s2idle, },
982 .desc = "MWAIT 0x20",
983 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
985 .target_residency = 500,
986 .enter = &intel_idle,
987 .enter_s2idle = intel_idle_s2idle, },
992 static const struct idle_cpu idle_cpu_nehalem __initconst = {
993 .state_table = nehalem_cstates,
994 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
995 .disable_promotion_to_c1e = true,
998 static const struct idle_cpu idle_cpu_nhx __initconst = {
999 .state_table = nehalem_cstates,
1000 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1001 .disable_promotion_to_c1e = true,
1005 static const struct idle_cpu idle_cpu_atom __initconst = {
1006 .state_table = atom_cstates,
1009 static const struct idle_cpu idle_cpu_tangier __initconst = {
1010 .state_table = tangier_cstates,
1013 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1014 .state_table = atom_cstates,
1015 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1018 static const struct idle_cpu idle_cpu_snb __initconst = {
1019 .state_table = snb_cstates,
1020 .disable_promotion_to_c1e = true,
1023 static const struct idle_cpu idle_cpu_snx __initconst = {
1024 .state_table = snb_cstates,
1025 .disable_promotion_to_c1e = true,
1029 static const struct idle_cpu idle_cpu_byt __initconst = {
1030 .state_table = byt_cstates,
1031 .disable_promotion_to_c1e = true,
1032 .byt_auto_demotion_disable_flag = true,
1035 static const struct idle_cpu idle_cpu_cht __initconst = {
1036 .state_table = cht_cstates,
1037 .disable_promotion_to_c1e = true,
1038 .byt_auto_demotion_disable_flag = true,
1041 static const struct idle_cpu idle_cpu_ivb __initconst = {
1042 .state_table = ivb_cstates,
1043 .disable_promotion_to_c1e = true,
1046 static const struct idle_cpu idle_cpu_ivt __initconst = {
1047 .state_table = ivt_cstates,
1048 .disable_promotion_to_c1e = true,
1052 static const struct idle_cpu idle_cpu_hsw __initconst = {
1053 .state_table = hsw_cstates,
1054 .disable_promotion_to_c1e = true,
1057 static const struct idle_cpu idle_cpu_hsx __initconst = {
1058 .state_table = hsw_cstates,
1059 .disable_promotion_to_c1e = true,
1063 static const struct idle_cpu idle_cpu_bdw __initconst = {
1064 .state_table = bdw_cstates,
1065 .disable_promotion_to_c1e = true,
1068 static const struct idle_cpu idle_cpu_bdx __initconst = {
1069 .state_table = bdw_cstates,
1070 .disable_promotion_to_c1e = true,
1074 static const struct idle_cpu idle_cpu_skl __initconst = {
1075 .state_table = skl_cstates,
1076 .disable_promotion_to_c1e = true,
1079 static const struct idle_cpu idle_cpu_skx __initconst = {
1080 .state_table = skx_cstates,
1081 .disable_promotion_to_c1e = true,
1085 static const struct idle_cpu idle_cpu_icx __initconst = {
1086 .state_table = icx_cstates,
1087 .disable_promotion_to_c1e = true,
1091 static const struct idle_cpu idle_cpu_avn __initconst = {
1092 .state_table = avn_cstates,
1093 .disable_promotion_to_c1e = true,
1097 static const struct idle_cpu idle_cpu_knl __initconst = {
1098 .state_table = knl_cstates,
1102 static const struct idle_cpu idle_cpu_bxt __initconst = {
1103 .state_table = bxt_cstates,
1104 .disable_promotion_to_c1e = true,
1107 static const struct idle_cpu idle_cpu_dnv __initconst = {
1108 .state_table = dnv_cstates,
1109 .disable_promotion_to_c1e = true,
1113 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1114 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1115 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
1116 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
1117 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
1118 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
1119 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
1120 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
1121 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
1122 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
1123 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
1124 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
1125 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
1126 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
1127 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1128 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
1129 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
1130 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
1131 X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
1132 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
1133 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
1134 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
1135 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
1136 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
1137 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
1138 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
1139 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
1140 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
1141 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
1142 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
1143 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
1144 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
1145 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
1146 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
1147 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
1148 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1149 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1150 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1151 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_dnv),
1155 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1156 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1160 static bool __init intel_idle_max_cstate_reached(int cstate)
1162 if (cstate + 1 > max_cstate) {
1163 pr_info("max_cstate %d reached\n", max_cstate);
1169 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1171 unsigned long eax = flg2MWAIT(state->flags);
1173 if (boot_cpu_has(X86_FEATURE_ARAT))
1177 * Switch over to one-shot tick broadcast if the target C-state
1178 * is deeper than C1.
1180 return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1183 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1184 #include <acpi/processor.h>
1186 static bool no_acpi __read_mostly;
1187 module_param(no_acpi, bool, 0444);
1188 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1190 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1191 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1192 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1194 static struct acpi_processor_power acpi_state_table __initdata;
1197 * intel_idle_cst_usable - Check if the _CST information can be used.
1199 * Check if all of the C-states listed by _CST in the max_cstate range are
1200 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1202 static bool __init intel_idle_cst_usable(void)
1206 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1207 acpi_state_table.count);
1209 for (cstate = 1; cstate < limit; cstate++) {
1210 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1212 if (cx->entry_method != ACPI_CSTATE_FFH)
1219 static bool __init intel_idle_acpi_cst_extract(void)
1224 pr_debug("Not allowed to use ACPI _CST\n");
1228 for_each_possible_cpu(cpu) {
1229 struct acpi_processor *pr = per_cpu(processors, cpu);
1234 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1237 acpi_state_table.count++;
1239 if (!intel_idle_cst_usable())
1242 if (!acpi_processor_claim_cst_control())
1248 acpi_state_table.count = 0;
1249 pr_debug("ACPI _CST not found or not usable\n");
1253 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1255 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1258 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1259 * the interesting states are ACPI_CSTATE_FFH.
1261 for (cstate = 1; cstate < limit; cstate++) {
1262 struct acpi_processor_cx *cx;
1263 struct cpuidle_state *state;
1265 if (intel_idle_max_cstate_reached(cstate - 1))
1268 cx = &acpi_state_table.states[cstate];
1270 state = &drv->states[drv->state_count++];
1272 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1273 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1274 state->exit_latency = cx->latency;
1276 * For C1-type C-states use the same number for both the exit
1277 * latency and target residency, because that is the case for
1278 * C1 in the majority of the static C-states tables above.
1279 * For the other types of C-states, however, set the target
1280 * residency to 3 times the exit latency which should lead to
1281 * a reasonable balance between energy-efficiency and
1282 * performance in the majority of interesting cases.
1284 state->target_residency = cx->latency;
1285 if (cx->type > ACPI_STATE_C1)
1286 state->target_residency *= 3;
1288 state->flags = MWAIT2flg(cx->address);
1289 if (cx->type > ACPI_STATE_C2)
1290 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1292 if (disabled_states_mask & BIT(cstate))
1293 state->flags |= CPUIDLE_FLAG_OFF;
1295 if (intel_idle_state_needs_timer_stop(state))
1296 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1298 state->enter = intel_idle;
1299 state->enter_s2idle = intel_idle_s2idle;
1303 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1308 * If there are no _CST C-states, do not disable any C-states by
1311 if (!acpi_state_table.count)
1314 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1316 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1317 * the interesting states are ACPI_CSTATE_FFH.
1319 for (cstate = 1; cstate < limit; cstate++) {
1320 if (acpi_state_table.states[cstate].address == mwait_hint)
1325 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1326 #define force_use_acpi (false)
1328 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1329 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1330 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1331 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1334 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1336 * Tune IVT multi-socket targets.
1337 * Assumption: num_sockets == (max_package_num + 1).
1339 static void __init ivt_idle_state_table_update(void)
1341 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1342 int cpu, package_num, num_sockets = 1;
1344 for_each_online_cpu(cpu) {
1345 package_num = topology_physical_package_id(cpu);
1346 if (package_num + 1 > num_sockets) {
1347 num_sockets = package_num + 1;
1349 if (num_sockets > 4) {
1350 cpuidle_state_table = ivt_cstates_8s;
1356 if (num_sockets > 2)
1357 cpuidle_state_table = ivt_cstates_4s;
1359 /* else, 1 and 2 socket systems use default ivt_cstates */
1363 * irtl_2_usec - IRTL to microseconds conversion.
1364 * @irtl: IRTL MSR value.
1366 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1368 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1370 static const unsigned int irtl_ns_units[] __initconst = {
1371 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1373 unsigned long long ns;
1378 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1380 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1384 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1386 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1387 * definitive maximum latency and use the same value for target_residency.
1389 static void __init bxt_idle_state_table_update(void)
1391 unsigned long long msr;
1394 rdmsrl(MSR_PKGC6_IRTL, msr);
1395 usec = irtl_2_usec(msr);
1397 bxt_cstates[2].exit_latency = usec;
1398 bxt_cstates[2].target_residency = usec;
1401 rdmsrl(MSR_PKGC7_IRTL, msr);
1402 usec = irtl_2_usec(msr);
1404 bxt_cstates[3].exit_latency = usec;
1405 bxt_cstates[3].target_residency = usec;
1408 rdmsrl(MSR_PKGC8_IRTL, msr);
1409 usec = irtl_2_usec(msr);
1411 bxt_cstates[4].exit_latency = usec;
1412 bxt_cstates[4].target_residency = usec;
1415 rdmsrl(MSR_PKGC9_IRTL, msr);
1416 usec = irtl_2_usec(msr);
1418 bxt_cstates[5].exit_latency = usec;
1419 bxt_cstates[5].target_residency = usec;
1422 rdmsrl(MSR_PKGC10_IRTL, msr);
1423 usec = irtl_2_usec(msr);
1425 bxt_cstates[6].exit_latency = usec;
1426 bxt_cstates[6].target_residency = usec;
1432 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1434 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1436 static void __init sklh_idle_state_table_update(void)
1438 unsigned long long msr;
1439 unsigned int eax, ebx, ecx, edx;
1442 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1443 if (max_cstate <= 7)
1446 /* if PC10 not present in CPUID.MWAIT.EDX */
1447 if ((mwait_substates & (0xF << 28)) == 0)
1450 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1452 /* PC10 is not enabled in PKG C-state limit */
1453 if ((msr & 0xF) != 8)
1457 cpuid(7, &eax, &ebx, &ecx, &edx);
1459 /* if SGX is present */
1460 if (ebx & (1 << 2)) {
1462 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1464 /* if SGX is enabled */
1465 if (msr & (1 << 18))
1469 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1470 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1473 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1475 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1476 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1477 MWAIT_SUBSTATE_MASK;
1479 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1480 if (num_substates == 0)
1483 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1484 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1489 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1493 switch (boot_cpu_data.x86_model) {
1494 case INTEL_FAM6_IVYBRIDGE_X:
1495 ivt_idle_state_table_update();
1497 case INTEL_FAM6_ATOM_GOLDMONT:
1498 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1499 bxt_idle_state_table_update();
1501 case INTEL_FAM6_SKYLAKE:
1502 sklh_idle_state_table_update();
1506 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1507 unsigned int mwait_hint;
1509 if (intel_idle_max_cstate_reached(cstate))
1512 if (!cpuidle_state_table[cstate].enter &&
1513 !cpuidle_state_table[cstate].enter_s2idle)
1516 /* If marked as unusable, skip this state. */
1517 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1518 pr_debug("state %s is disabled\n",
1519 cpuidle_state_table[cstate].name);
1523 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1524 if (!intel_idle_verify_cstate(mwait_hint))
1527 /* Structure copy. */
1528 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1530 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) &&
1531 cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_IBRS) {
1532 drv->states[drv->state_count].enter = intel_idle_ibrs;
1535 if ((disabled_states_mask & BIT(drv->state_count)) ||
1536 ((icpu->use_acpi || force_use_acpi) &&
1537 intel_idle_off_by_default(mwait_hint) &&
1538 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1539 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1541 if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
1542 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
1547 if (icpu->byt_auto_demotion_disable_flag) {
1548 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1549 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1554 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1555 * @drv: cpuidle driver structure to initialize.
1557 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1559 cpuidle_poll_state_init(drv);
1561 if (disabled_states_mask & BIT(0))
1562 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1564 drv->state_count = 1;
1567 intel_idle_init_cstates_icpu(drv);
1569 intel_idle_init_cstates_acpi(drv);
1572 static void auto_demotion_disable(void)
1574 unsigned long long msr_bits;
1576 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1577 msr_bits &= ~auto_demotion_disable_flags;
1578 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1581 static void c1e_promotion_disable(void)
1583 unsigned long long msr_bits;
1585 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1587 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1591 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1592 * @cpu: CPU to initialize.
1594 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1595 * with the processor model flags.
1597 static int intel_idle_cpu_init(unsigned int cpu)
1599 struct cpuidle_device *dev;
1601 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1604 if (cpuidle_register_device(dev)) {
1605 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1609 if (auto_demotion_disable_flags)
1610 auto_demotion_disable();
1612 if (disable_promotion_to_c1e)
1613 c1e_promotion_disable();
1618 static int intel_idle_cpu_online(unsigned int cpu)
1620 struct cpuidle_device *dev;
1622 if (!boot_cpu_has(X86_FEATURE_ARAT))
1623 tick_broadcast_enable();
1626 * Some systems can hotplug a cpu at runtime after
1627 * the kernel has booted, we have to initialize the
1628 * driver in this case
1630 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1631 if (!dev->registered)
1632 return intel_idle_cpu_init(cpu);
1638 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1640 static void __init intel_idle_cpuidle_devices_uninit(void)
1644 for_each_online_cpu(i)
1645 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1648 static int __init intel_idle_init(void)
1650 const struct x86_cpu_id *id;
1651 unsigned int eax, ebx, ecx;
1654 /* Do not load intel_idle at all for now if idle= is passed */
1655 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1658 if (max_cstate == 0) {
1659 pr_debug("disabled\n");
1663 id = x86_match_cpu(intel_idle_ids);
1665 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1666 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1670 id = x86_match_cpu(intel_mwait_ids);
1675 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1678 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1680 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1681 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1685 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1687 icpu = (const struct idle_cpu *)id->driver_data;
1689 cpuidle_state_table = icpu->state_table;
1690 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1691 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1692 if (icpu->use_acpi || force_use_acpi)
1693 intel_idle_acpi_cst_extract();
1694 } else if (!intel_idle_acpi_cst_extract()) {
1698 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1699 boot_cpu_data.x86_model);
1701 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1702 if (!intel_idle_cpuidle_devices)
1705 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1707 retval = cpuidle_register_driver(&intel_idle_driver);
1709 struct cpuidle_driver *drv = cpuidle_get_driver();
1710 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1711 drv ? drv->name : "none");
1712 goto init_driver_fail;
1715 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1716 intel_idle_cpu_online, NULL);
1720 pr_debug("Local APIC timer is reliable in %s\n",
1721 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1726 intel_idle_cpuidle_devices_uninit();
1727 cpuidle_unregister_driver(&intel_idle_driver);
1729 free_percpu(intel_idle_cpuidle_devices);
1733 device_initcall(intel_idle_init);
1736 * We are not really modular, but we used to support that. Meaning we also
1737 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1738 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1739 * is the easiest way (currently) to continue doing that.
1741 module_param(max_cstate, int, 0444);
1743 * The positions of the bits that are set in this number are the indices of the
1744 * idle states to be disabled by default (as reflected by the names of the
1745 * corresponding idle state directories in sysfs, "state0", "state1" ...
1746 * "state<i>" ..., where <i> is the index of the given state).
1748 module_param_named(states_off, disabled_states_mask, uint, 0444);
1749 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");