1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
7 #include "intel_dram.h"
8 #include "intel_sideband.h"
10 struct dram_dimm_info {
11 u8 size, width, ranks;
14 struct dram_channel_info {
15 struct dram_dimm_info dimm_l, dimm_s;
20 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
22 static const char *intel_dram_type_str(enum intel_dram_type type)
24 static const char * const str[] = {
25 DRAM_TYPE_STR(UNKNOWN),
28 DRAM_TYPE_STR(LPDDR3),
29 DRAM_TYPE_STR(LPDDR4),
32 if (type >= ARRAY_SIZE(str))
33 type = INTEL_DRAM_UNKNOWN;
40 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
42 return dimm->ranks * 64 / (dimm->width ?: 1);
45 /* Returns total GB for the whole DIMM */
46 static int skl_get_dimm_size(u16 val)
48 return val & SKL_DRAM_SIZE_MASK;
51 static int skl_get_dimm_width(u16 val)
53 if (skl_get_dimm_size(val) == 0)
56 switch (val & SKL_DRAM_WIDTH_MASK) {
57 case SKL_DRAM_WIDTH_X8:
58 case SKL_DRAM_WIDTH_X16:
59 case SKL_DRAM_WIDTH_X32:
60 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
68 static int skl_get_dimm_ranks(u16 val)
70 if (skl_get_dimm_size(val) == 0)
73 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
78 /* Returns total GB for the whole DIMM */
79 static int cnl_get_dimm_size(u16 val)
81 return (val & CNL_DRAM_SIZE_MASK) / 2;
84 static int cnl_get_dimm_width(u16 val)
86 if (cnl_get_dimm_size(val) == 0)
89 switch (val & CNL_DRAM_WIDTH_MASK) {
90 case CNL_DRAM_WIDTH_X8:
91 case CNL_DRAM_WIDTH_X16:
92 case CNL_DRAM_WIDTH_X32:
93 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
101 static int cnl_get_dimm_ranks(u16 val)
103 if (cnl_get_dimm_size(val) == 0)
106 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
112 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
114 /* Convert total GB to Gb per DRAM device */
115 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
119 skl_dram_get_dimm_info(struct drm_i915_private *i915,
120 struct dram_dimm_info *dimm,
121 int channel, char dimm_name, u16 val)
123 if (INTEL_GEN(i915) >= 10) {
124 dimm->size = cnl_get_dimm_size(val);
125 dimm->width = cnl_get_dimm_width(val);
126 dimm->ranks = cnl_get_dimm_ranks(val);
128 dimm->size = skl_get_dimm_size(val);
129 dimm->width = skl_get_dimm_width(val);
130 dimm->ranks = skl_get_dimm_ranks(val);
133 drm_dbg_kms(&i915->drm,
134 "CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
135 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
136 yesno(skl_is_16gb_dimm(dimm)));
140 skl_dram_get_channel_info(struct drm_i915_private *i915,
141 struct dram_channel_info *ch,
142 int channel, u32 val)
144 skl_dram_get_dimm_info(i915, &ch->dimm_l,
145 channel, 'L', val & 0xffff);
146 skl_dram_get_dimm_info(i915, &ch->dimm_s,
147 channel, 'S', val >> 16);
149 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
150 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
154 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
156 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
161 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
162 skl_is_16gb_dimm(&ch->dimm_s);
164 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
165 channel, ch->ranks, yesno(ch->is_16gb_dimm));
171 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
172 const struct dram_channel_info *ch1)
174 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
175 (ch0->dimm_s.size == 0 ||
176 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
180 skl_dram_get_channels_info(struct drm_i915_private *i915)
182 struct dram_info *dram_info = &i915->dram_info;
183 struct dram_channel_info ch0 = {}, ch1 = {};
187 val = intel_uncore_read(&i915->uncore,
188 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
189 ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
191 dram_info->num_channels++;
193 val = intel_uncore_read(&i915->uncore,
194 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
195 ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
197 dram_info->num_channels++;
199 if (dram_info->num_channels == 0) {
200 drm_info(&i915->drm, "Number of memory channels is zero\n");
205 * If any of the channel is single rank channel, worst case output
206 * will be same as if single rank memory, so consider single rank
209 if (ch0.ranks == 1 || ch1.ranks == 1)
210 dram_info->ranks = 1;
212 dram_info->ranks = max(ch0.ranks, ch1.ranks);
214 if (dram_info->ranks == 0) {
215 drm_info(&i915->drm, "couldn't get memory rank information\n");
219 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
221 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
223 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
224 yesno(dram_info->symmetric_memory));
229 static enum intel_dram_type
230 skl_get_dram_type(struct drm_i915_private *i915)
234 val = intel_uncore_read(&i915->uncore,
235 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
237 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
238 case SKL_DRAM_DDR_TYPE_DDR3:
239 return INTEL_DRAM_DDR3;
240 case SKL_DRAM_DDR_TYPE_DDR4:
241 return INTEL_DRAM_DDR4;
242 case SKL_DRAM_DDR_TYPE_LPDDR3:
243 return INTEL_DRAM_LPDDR3;
244 case SKL_DRAM_DDR_TYPE_LPDDR4:
245 return INTEL_DRAM_LPDDR4;
248 return INTEL_DRAM_UNKNOWN;
253 skl_get_dram_info(struct drm_i915_private *i915)
255 struct dram_info *dram_info = &i915->dram_info;
256 u32 mem_freq_khz, val;
259 dram_info->type = skl_get_dram_type(i915);
260 drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
261 intel_dram_type_str(dram_info->type));
263 ret = skl_dram_get_channels_info(i915);
267 val = intel_uncore_read(&i915->uncore,
268 SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
269 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
270 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
272 dram_info->bandwidth_kbps = dram_info->num_channels *
275 if (dram_info->bandwidth_kbps == 0) {
277 "Couldn't get system memory bandwidth\n");
281 dram_info->valid = true;
285 /* Returns Gb per DRAM device */
286 static int bxt_get_dimm_size(u32 val)
288 switch (val & BXT_DRAM_SIZE_MASK) {
289 case BXT_DRAM_SIZE_4GBIT:
291 case BXT_DRAM_SIZE_6GBIT:
293 case BXT_DRAM_SIZE_8GBIT:
295 case BXT_DRAM_SIZE_12GBIT:
297 case BXT_DRAM_SIZE_16GBIT:
305 static int bxt_get_dimm_width(u32 val)
307 if (!bxt_get_dimm_size(val))
310 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
315 static int bxt_get_dimm_ranks(u32 val)
317 if (!bxt_get_dimm_size(val))
320 switch (val & BXT_DRAM_RANK_MASK) {
321 case BXT_DRAM_RANK_SINGLE:
323 case BXT_DRAM_RANK_DUAL:
331 static enum intel_dram_type bxt_get_dimm_type(u32 val)
333 if (!bxt_get_dimm_size(val))
334 return INTEL_DRAM_UNKNOWN;
336 switch (val & BXT_DRAM_TYPE_MASK) {
337 case BXT_DRAM_TYPE_DDR3:
338 return INTEL_DRAM_DDR3;
339 case BXT_DRAM_TYPE_LPDDR3:
340 return INTEL_DRAM_LPDDR3;
341 case BXT_DRAM_TYPE_DDR4:
342 return INTEL_DRAM_DDR4;
343 case BXT_DRAM_TYPE_LPDDR4:
344 return INTEL_DRAM_LPDDR4;
347 return INTEL_DRAM_UNKNOWN;
351 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
353 dimm->width = bxt_get_dimm_width(val);
354 dimm->ranks = bxt_get_dimm_ranks(val);
357 * Size in register is Gb per DRAM device. Convert to total
358 * GB to match the way we report this for non-LP platforms.
360 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
363 static int bxt_get_dram_info(struct drm_i915_private *i915)
365 struct dram_info *dram_info = &i915->dram_info;
367 u32 mem_freq_khz, val;
368 u8 num_active_channels;
371 val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
372 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
373 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
375 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
376 num_active_channels = hweight32(dram_channels);
378 /* Each active bit represents 4-byte channel */
379 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
381 if (dram_info->bandwidth_kbps == 0) {
383 "Couldn't get system memory bandwidth\n");
388 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
390 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
391 struct dram_dimm_info dimm;
392 enum intel_dram_type type;
394 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
395 if (val == 0xFFFFFFFF)
398 dram_info->num_channels++;
400 bxt_get_dimm_info(&dimm, val);
401 type = bxt_get_dimm_type(val);
403 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
404 dram_info->type != INTEL_DRAM_UNKNOWN &&
405 dram_info->type != type);
407 drm_dbg_kms(&i915->drm,
408 "CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
409 i - BXT_D_CR_DRP0_DUNIT_START,
410 dimm.size, dimm.width, dimm.ranks,
411 intel_dram_type_str(type));
414 * If any of the channel is single rank channel,
415 * worst case output will be same as if single rank
416 * memory, so consider single rank memory.
418 if (dram_info->ranks == 0)
419 dram_info->ranks = dimm.ranks;
420 else if (dimm.ranks == 1)
421 dram_info->ranks = 1;
423 if (type != INTEL_DRAM_UNKNOWN)
424 dram_info->type = type;
427 if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {
428 drm_info(&i915->drm, "couldn't get memory information\n");
432 dram_info->valid = true;
437 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
439 struct dram_info *dram_info = &dev_priv->dram_info;
443 ret = sandybridge_pcode_read(dev_priv,
444 ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
445 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
450 if (IS_GEN(dev_priv, 12)) {
453 dram_info->type = INTEL_DRAM_DDR4;
456 dram_info->type = INTEL_DRAM_LPDDR4;
459 dram_info->type = INTEL_DRAM_DDR3;
462 dram_info->type = INTEL_DRAM_LPDDR3;
465 MISSING_CASE(val & 0xf);
471 dram_info->type = INTEL_DRAM_DDR4;
474 dram_info->type = INTEL_DRAM_DDR3;
477 dram_info->type = INTEL_DRAM_LPDDR3;
480 dram_info->type = INTEL_DRAM_LPDDR4;
483 MISSING_CASE(val & 0xf);
488 dram_info->num_channels = (val & 0xf0) >> 4;
489 dram_info->num_qgv_points = (val & 0xf00) >> 8;
494 static int gen11_get_dram_info(struct drm_i915_private *i915)
496 int ret = skl_get_dram_info(i915);
501 return icl_pcode_read_mem_global_info(i915);
504 static int gen12_get_dram_info(struct drm_i915_private *i915)
506 /* Always needed for GEN12+ */
507 i915->dram_info.is_16gb_dimm = true;
509 return icl_pcode_read_mem_global_info(i915);
512 void intel_dram_detect(struct drm_i915_private *i915)
514 struct dram_info *dram_info = &i915->dram_info;
518 * Assume 16Gb DIMMs are present until proven otherwise.
519 * This is only used for the level 0 watermark latency
520 * w/a which does not apply to bxt/glk.
522 dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
524 if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
527 if (INTEL_GEN(i915) >= 12)
528 ret = gen12_get_dram_info(i915);
529 else if (INTEL_GEN(i915) >= 11)
530 ret = gen11_get_dram_info(i915);
531 else if (IS_GEN9_LP(i915))
532 ret = bxt_get_dram_info(i915);
534 ret = skl_get_dram_info(i915);
538 drm_dbg_kms(&i915->drm, "DRAM bandwidth: %u kBps, channels: %u\n",
539 dram_info->bandwidth_kbps, dram_info->num_channels);
541 drm_dbg_kms(&i915->drm, "DRAM ranks: %u, 16Gb DIMMs: %s\n",
542 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
545 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
547 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
548 static const u8 sets[4] = { 1, 1, 2, 2 };
550 return EDRAM_NUM_BANKS(cap) *
551 ways[EDRAM_WAYS_IDX(cap)] *
552 sets[EDRAM_SETS_IDX(cap)];
555 void intel_dram_edram_detect(struct drm_i915_private *i915)
559 if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || INTEL_GEN(i915) >= 9))
562 edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
564 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
566 if (!(edram_cap & EDRAM_ENABLED))
570 * The needed capability bits for size calculation are not there with
571 * pre gen9 so return 128MB always.
573 if (INTEL_GEN(i915) < 9)
574 i915->edram_size_mb = 128;
576 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
578 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);