2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "athos_api.h"
40 #include "adf_os_io.h"
42 #if defined(PROJECT_MAGPIE)
44 extern uint32_t *init_htc_handle;
45 uint8_t htc_complete_setup = 0;
46 void reset_EP4_FIFO(void);
50 void Magpie_init(void);
53 #if defined(PROJECT_MAGPIE)
54 extern BOOLEAN bEepromExist;
55 extern BOOLEAN bJumptoFlash;
58 static uint32_t loop_low, loop_high;
60 // reference idle count at the beginning
61 uint32_t idle_cnt = 0;
63 #if defined(PROJECT_K2)
64 // save the ROM printf function point
65 int (* save_cmnos_printf)(const char * fmt, ...);
68 #define ATH_DATE_STRING __DATE__" "__TIME__
70 static void idle_task();
72 #if defined(PROJECT_MAGPIE)
73 void fatal_exception_func()
75 // patch for execption
76 (void)_xtos_set_exception_handler(EXCCAUSE_UNALIGNED, AR6002_fatal_exception_handler_patch);
77 (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, AR6002_fatal_exception_handler_patch);
78 (void)_xtos_set_exception_handler(EXCCAUSE_ILLEGAL, AR6002_fatal_exception_handler_patch);
79 (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_ERROR, AR6002_fatal_exception_handler_patch);
80 (void)_xtos_set_exception_handler(EXCCAUSE_PRIVILEGED, AR6002_fatal_exception_handler_patch);
81 (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_DATA_ERROR, AR6002_fatal_exception_handler_patch);
82 (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, AR6002_fatal_exception_handler_patch);
83 (void)_xtos_set_exception_handler(EXCCAUSE_DIVIDE_BY_ZERO, AR6002_fatal_exception_handler_patch);
87 #if defined(PROJECT_MAGPIE)
89 change_magpie_clk(void)
91 iowrite32(0x00056004, BIT4 | BIT0);
93 /* Wait for the update bit (BIT0) to get cleared */
94 while (ioread32(0x00056004) & BIT0)
97 /* Put the PLL into reset */
98 io32_set(0x00050010, BIT1);
101 * XXX: statically set the CPU clock to 200Mhz
103 /* Setting PLL to 400MHz */
104 iowrite32(0x00056000, 0x325);
106 /* Pull CPU PLL out of Reset */
107 io32_clr(0x00050010, BIT1);
109 A_DELAY_USECS(60); // wait for stable
111 /* CPU & AHB settings */
113 * AHB clk = ( CPU clk / 2 )
115 iowrite32(0x00056004, 0x00001 | BIT16 | BIT8); /* set plldiv to 2 */
117 while (ioread32(0x00056004) & BIT0)
121 A_UART_HWINIT((100*1000*1000), 115200);
125 void exception_reset(struct register_dump_s *dump)
127 A_PRINTF("exception_reset \n");
129 /* phase I dump info */
130 A_PRINTF("exception reset-phase 1\n");
135 A_PRINTF("exception reset-phase 2\n");
136 iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, WDT_MAGIC_PATTERN);
138 io32_set(MAGPIE_REG_RST_RESET_ADDR, BIT10 | BIT8 | BIT7 | BIT6);
140 io32_set(MAGPIE_REG_AHB_ARB_ADDR, BIT1);
142 iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
143 io32_set(0x50010, BIT4);
145 io32_clr(0x50010, BIT4);
147 iowrite32_usb(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
149 // set clock to bypass mode - 40Mhz from XTAL
150 iowrite32(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, BIT0 | BIT4);
151 A_DELAY_USECS(100); // wait for stable
152 iowrite32(MAGPIE_REG_CPU_PLL_ADDR, BIT16);
154 A_UART_HWINIT((40*1000*1000), 115200);
156 A_PRINTF("do TX/RX swap\n");
158 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
159 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
160 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
161 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
163 A_PRINTF("Cold reboot initiated.");
164 #if defined(PROJECT_MAGPIE)
165 iowrite32(WATCH_DOG_MAGIC_PATTERN_ADDR, 0);
166 #elif defined(PROJECT_K2)
167 iowrite32(MAGPIE_REG_RST_STATUS_ADDR, 0);
168 #endif /* #if defined(PROJECT_MAGPIE) */
172 void reset_EP4_FIFO(void)
177 io8_set_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4);
178 for(i = 0; i < 100; i++) {}
179 io8_clr_usb(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, BIT4);
182 LOCAL void zfGenExceptionEvent(uint32_t exccause, uint32_t pc, uint32_t badvaddr)
184 uint32_t pattern = 0x33221199;
186 A_PRINTF("<Exception>Tgt Drv send an event 44332211 to Host Drv\n");
187 mUSB_STATUS_IN_INT_DISABLE();
189 iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
191 iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern);
192 iowrite32_usb(ZM_EP3_DATA_OFFSET, exccause);
193 iowrite32_usb(ZM_EP3_DATA_OFFSET, pc);
194 iowrite32_usb(ZM_EP3_DATA_OFFSET, badvaddr);
196 mUSB_EP3_XFER_DONE();
199 LOCAL void zfGenWrongEpidEvent(uint32_t epid)
201 uint32_t pattern = 0x33221299;
203 A_PRINTF("<WrongEPID>Tgt Drv send an event 44332212 to Host Drv\n");
204 mUSB_STATUS_IN_INT_DISABLE();
206 iowrite32_usb(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
208 iowrite32_usb(ZM_EP3_DATA_OFFSET, pattern);
209 iowrite32_usb(ZM_EP3_DATA_OFFSET, epid);
211 mUSB_EP3_XFER_DONE();
215 AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame)
217 struct register_dump_s dump;
218 uint32_t exc_cause, exc_vaddr;
219 asm volatile("rsr %0,%1" : "=r" (exc_cause) : "n" (EXCCAUSE));
220 asm volatile("rsr %0,%1" : "=r" (exc_vaddr) : "n" (EXCVADDR));
222 dump.exc_frame = *exc_frame; /* structure copy */
223 dump.badvaddr = exc_vaddr;
224 dump.exc_frame.xt_exccause = exc_cause;
225 dump.pc = exc_frame->xt_pc;
228 zfGenExceptionEvent(dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr);
230 #if SYSTEM_MODULE_PRINT
231 A_PRINTF("\nFatal exception (%d): \tpc=0x%x \n\r\tbadvaddr=0x%x \n\r\tdump area=0x%x\n",
232 dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump);
233 PRINT_FAILURE_STATE();
235 A_PUTS("Fatal exception\n\r");
247 HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf,
248 adf_nbuf_t pBuffers, void *arg)
252 HTC_UNKNOWN_MSG *pMsg;
254 /* we assume buffers are aligned such that we can access the message
255 * parameters directly*/
256 adf_nbuf_peek_header(pBuffers, &anbdata, &anblen);
257 pMsg = (HTC_UNKNOWN_MSG *)anbdata;
259 if (pMsg->MessageID == HTC_MSG_SETUP_COMPLETE_ID) {
260 htc_complete_setup = 1;
263 HTCControlSvcProcessMsg(EndpointID, hdr_buf, pBuffers, arg);
266 /* Patch callback for check the endpoint ID is correct or not */
268 HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context)
274 HTC_FRAME_HDR *pHTCHdr;
276 if (hdr_buf == ADF_NBUF_NULL) {
277 /* HTC hdr is not in the hdr_buf */
283 adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen);
284 pHTCHdr = (HTC_FRAME_HDR *)anbdata;
286 eid = pHTCHdr->EndpointID;
288 if ((eid != 0) && (htc_complete_setup == 0)) {
289 A_PRINTF("\nHTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen);
290 A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n",
291 *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
292 *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7),
293 *(anbdata+8), *(anbdata+9), *(anbdata+10), *(anbdata+11));
294 A_PRINTF("init_htc_handle = 0x%8x\n", init_htc_handle);
296 if (pHTCHdr->EndpointID == 1) {
297 A_PRINTF("Return WMI Command buffer\n");
298 HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf);
299 } else if ((pHTCHdr->EndpointID == 5) || (pHTCHdr->EndpointID == 6)) {
300 A_PRINTF("Return Data buffer\n");
301 HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf);
305 if ((pHTCHdr->EndpointID < 0) || (pHTCHdr->EndpointID >= ENDPOINT_MAX)) {
306 A_PRINTF("HTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen);
307 A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n",
308 *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
309 *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7));
312 A_PRINTF("EP1-Tx-Data with Wrong Htc Header Endpoint ID, WAR free this buffer\n");
313 HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf);
314 A_PRINTF("EP1-Tx-Data > Free this buffer successfully\n");
316 A_PRINTF("EP4-WMI-Cmd with Wrong Htc Header Endpoint ID, WAR free this buffer\n");
317 zfGenWrongEpidEvent((a_uint32_t)pHTCHdr->EndpointID);
318 HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf);
319 A_PRINTF("EP4-WMI-Cmd > Free this buffer successfully\n");
322 HTCMsgRecvHandler( hdr_buf, buffer, context);
330 uint32_t *temp = (uint32_t *)ALLOCRAM_START;
332 /* clear bss segment */
333 for(temp = (uint32_t *)&START_BSS; temp < (uint32_t *)&END_BSS; temp++)
336 /* clear heap segment */
337 for(i = 0; i < ((ALLOCRAM_SIZE - 4)/4); i++)
341 static void idle_task()
343 if (loop_low == 0xffffffff) {
352 void __noreturn wlan_task(void)
354 loop_low=loop_high=0;
357 /* update wdt timer */
360 /* UPDATE cticks - to be moved to idle_tsk, put here will be easier to read */
363 HIF_isr_handler(NULL);
365 #if MAGPIE_ENABLE_WLAN == 1
372 /* Very low priority tasks */
373 if ((loop_low & 0x1fff) == 0x7)
380 #endif /* #if defined(_RAM_) */