2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
34 #include <subdev/devinit.h>
35 #include <subdev/gpio.h>
36 #include <subdev/i2c.h>
37 #include <subdev/vga.h>
39 #define bioslog(lvl, fmt, args...) do { \
40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \
41 init->offset, init_exec(init) ? \
42 '0' + (init->nested - 1) : ' ', ##args); \
44 #define cont(fmt, args...) do { \
45 if (init->subdev->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
52 /******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
57 init_exec(struct nvbios_init *init)
59 return (init->execute == 1) || ((init->execute & 5) == 5);
63 init_exec_set(struct nvbios_init *init, bool exec)
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
70 init_exec_inv(struct nvbios_init *init)
72 init->execute ^= 0x02;
76 init_exec_force(struct nvbios_init *init, bool exec)
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
82 /******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
87 init_or(struct nvbios_init *init)
89 if (init_exec(init)) {
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
98 init_link(struct nvbios_init *init)
100 if (init_exec(init)) {
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
109 init_crtc(struct nvbios_init *init)
111 if (init_exec(init)) {
114 error("script needs crtc\n");
120 init_conn(struct nvbios_init *init)
122 struct nvkm_bios *bios = init->bios;
123 struct nvbios_connE connE;
127 if (init_exec(init)) {
129 conn = init->outp->connector;
130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
135 error("script needs connector type\n");
142 init_nvreg(struct nvbios_init *init, u32 reg)
144 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
157 if (init->bios->subdev.device->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
176 return nvkm_devinit_mmio(devinit, reg);
180 init_rd32(struct nvbios_init *init, u32 reg)
182 struct nvkm_device *device = init->bios->subdev.device;
183 reg = init_nvreg(init, reg);
184 if (reg != ~0 && init_exec(init))
185 return nvkm_rd32(device, reg);
190 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
192 struct nvkm_device *device = init->bios->subdev.device;
193 reg = init_nvreg(init, reg);
194 if (reg != ~0 && init_exec(init))
195 nvkm_wr32(device, reg, val);
199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
201 struct nvkm_device *device = init->bios->subdev.device;
202 reg = init_nvreg(init, reg);
203 if (reg != ~0 && init_exec(init)) {
204 u32 tmp = nvkm_rd32(device, reg);
205 nvkm_wr32(device, reg, (tmp & ~mask) | val);
212 init_rdport(struct nvbios_init *init, u16 port)
215 return nvkm_rdport(init->subdev->device, init->crtc, port);
220 init_wrport(struct nvbios_init *init, u16 port, u8 value)
223 nvkm_wrport(init->subdev->device, init->crtc, port, value);
227 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
229 struct nvkm_subdev *subdev = init->subdev;
230 if (init_exec(init)) {
231 int head = init->crtc < 0 ? 0 : init->crtc;
232 return nvkm_rdvgai(subdev->device, head, port, index);
238 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
240 struct nvkm_device *device = init->subdev->device;
242 /* force head 0 for updates to cr44, it only exists on first head */
243 if (device->card_type < NV_50) {
244 if (port == 0x03d4 && index == 0x44)
248 if (init_exec(init)) {
249 int head = init->crtc < 0 ? 0 : init->crtc;
250 nvkm_wrvgai(device, head, port, index, value);
253 /* select head 1 if cr44 write selected it */
254 if (device->card_type < NV_50) {
255 if (port == 0x03d4 && index == 0x44 && value == 3)
260 static struct i2c_adapter *
261 init_i2c(struct nvbios_init *init, int index)
263 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
264 struct nvkm_i2c_bus *bus;
267 index = NVKM_I2C_BUS_PRI;
268 if (init->outp && init->outp->i2c_upper_default)
269 index = NVKM_I2C_BUS_SEC;
272 index = NVKM_I2C_BUS_PRI;
275 index = NVKM_I2C_BUS_SEC;
278 bus = nvkm_i2c_bus_find(i2c, index);
279 return bus ? &bus->i2c : NULL;
283 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
285 struct i2c_adapter *adap = init_i2c(init, index);
286 if (adap && init_exec(init))
287 return nvkm_rdi2cr(adap, addr, reg);
292 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
294 struct i2c_adapter *adap = init_i2c(init, index);
295 if (adap && init_exec(init))
296 return nvkm_wri2cr(adap, addr, reg, val);
300 static struct nvkm_i2c_aux *
301 init_aux(struct nvbios_init *init)
303 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
306 error("script needs output for aux\n");
309 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index);
313 init_rdauxr(struct nvbios_init *init, u32 addr)
315 struct nvkm_i2c_aux *aux = init_aux(init);
318 if (aux && init_exec(init)) {
319 int ret = nvkm_rdaux(aux, addr, &data, 1);
322 trace("auxch read failed with %d\n", ret);
329 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
331 struct nvkm_i2c_aux *aux = init_aux(init);
332 if (aux && init_exec(init)) {
333 int ret = nvkm_wraux(aux, addr, &data, 1);
335 trace("auxch write failed with %d\n", ret);
342 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
344 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
345 if (init_exec(init)) {
346 int ret = nvkm_devinit_pll_set(devinit, id, freq);
348 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
352 /******************************************************************************
353 * parsing of bios structures that are required to execute init tables
354 *****************************************************************************/
357 init_table(struct nvkm_bios *bios, u16 *len)
359 struct bit_entry bit_I;
361 if (!bit_entry(bios, 'I', &bit_I)) {
366 if (bmp_version(bios) >= 0x0510) {
368 return bios->bmp_offset + 75;
375 init_table_(struct nvbios_init *init, u16 offset, const char *name)
377 struct nvkm_bios *bios = init->bios;
378 u16 len, data = init_table(bios, &len);
380 if (len >= offset + 2) {
381 data = nvbios_rd16(bios, data + offset);
385 warn("%s pointer invalid\n", name);
389 warn("init data too short for %s pointer", name);
393 warn("init data not found\n");
397 #define init_script_table(b) init_table_((b), 0x00, "script table")
398 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
399 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
400 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
401 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
402 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
403 #define init_function_table(b) init_table_((b), 0x0c, "function table")
404 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
407 init_script(struct nvkm_bios *bios, int index)
409 struct nvbios_init init = { .bios = bios };
410 u16 bmp_ver = bmp_version(bios), data;
412 if (bmp_ver && bmp_ver < 0x0510) {
413 if (index > 1 || bmp_ver < 0x0100)
416 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
417 return nvbios_rd16(bios, data + (index * 2));
420 data = init_script_table(&init);
422 return nvbios_rd16(bios, data + (index * 2));
428 init_unknown_script(struct nvkm_bios *bios)
430 u16 len, data = init_table(bios, &len);
431 if (data && len >= 16)
432 return nvbios_rd16(bios, data + 14);
437 init_ram_restrict_group_count(struct nvbios_init *init)
439 return nvbios_ramcfg_count(init->bios);
443 init_ram_restrict(struct nvbios_init *init)
445 /* This appears to be the behaviour of the VBIOS parser, and *is*
446 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
447 * avoid fucking up the memory controller (somehow) by reading it
448 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
450 * Preserving the non-caching behaviour on earlier chipsets just
451 * in case *not* re-reading the strap causes similar breakage.
453 if (!init->ramcfg || init->bios->version.major < 0x70)
454 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
455 return (init->ramcfg & 0x7fffffff);
459 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
461 struct nvkm_bios *bios = init->bios;
462 u16 table = init_xlat_table(init);
464 u16 data = nvbios_rd16(bios, table + (index * 2));
466 return nvbios_rd08(bios, data + offset);
467 warn("xlat table pointer %d invalid\n", index);
472 /******************************************************************************
473 * utility functions used by various init opcode handlers
474 *****************************************************************************/
477 init_condition_met(struct nvbios_init *init, u8 cond)
479 struct nvkm_bios *bios = init->bios;
480 u16 table = init_condition_table(init);
482 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0);
483 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4);
484 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8);
485 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
486 cond, reg, msk, val);
487 return (init_rd32(init, reg) & msk) == val;
493 init_io_condition_met(struct nvbios_init *init, u8 cond)
495 struct nvkm_bios *bios = init->bios;
496 u16 table = init_io_condition_table(init);
498 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0);
499 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2);
500 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3);
501 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4);
502 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
503 cond, port, index, mask, value);
504 return (init_rdvgai(init, port, index) & mask) == value;
510 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
512 struct nvkm_bios *bios = init->bios;
513 u16 table = init_io_flag_condition_table(init);
515 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0);
516 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2);
517 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3);
518 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4);
519 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5);
520 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7);
521 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8);
522 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
523 return (nvbios_rd08(bios, data + ioval) & dmask) == value;
529 init_shift(u32 data, u8 shift)
532 return data >> shift;
533 return data << (0x100 - shift);
537 init_tmds_reg(struct nvbios_init *init, u8 tmds)
539 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
540 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
541 * CR58 for CR57 = 0 to index a table of offsets to the basic
543 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
544 * CR58 for CR57 = 0 to index a table of offsets to the basic
545 * 0x6808b0 address, and then flip the offset by 8.
547 const int pramdac_offset[13] = {
548 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
549 const u32 pramdac_table[4] = {
550 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
554 u32 dacoffset = pramdac_offset[init->outp->or];
557 return 0x6808b0 + dacoffset;
561 error("tmds opcodes need dcb\n");
563 if (tmds < ARRAY_SIZE(pramdac_table))
564 return pramdac_table[tmds];
566 error("tmds selector 0x%02x unknown\n", tmds);
572 /******************************************************************************
573 * init opcode handlers
574 *****************************************************************************/
577 * init_reserved - stub for various unknown/unused single-byte opcodes
581 init_reserved(struct nvbios_init *init)
583 u8 opcode = nvbios_rd08(init->bios, init->offset);
595 trace("RESERVED 0x%02x\t", opcode);
596 for (i = 1; i < length; i++)
597 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i));
599 init->offset += length;
603 * INIT_DONE - opcode 0x71
607 init_done(struct nvbios_init *init)
610 init->offset = 0x0000;
614 * INIT_IO_RESTRICT_PROG - opcode 0x32
618 init_io_restrict_prog(struct nvbios_init *init)
620 struct nvkm_bios *bios = init->bios;
621 u16 port = nvbios_rd16(bios, init->offset + 1);
622 u8 index = nvbios_rd08(bios, init->offset + 3);
623 u8 mask = nvbios_rd08(bios, init->offset + 4);
624 u8 shift = nvbios_rd08(bios, init->offset + 5);
625 u8 count = nvbios_rd08(bios, init->offset + 6);
626 u32 reg = nvbios_rd32(bios, init->offset + 7);
629 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
630 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
631 reg, port, index, mask, shift);
634 conf = (init_rdvgai(init, port, index) & mask) >> shift;
635 for (i = 0; i < count; i++) {
636 u32 data = nvbios_rd32(bios, init->offset);
639 trace("\t0x%08x *\n", data);
640 init_wr32(init, reg, data);
642 trace("\t0x%08x\n", data);
651 * INIT_REPEAT - opcode 0x33
655 init_repeat(struct nvbios_init *init)
657 struct nvkm_bios *bios = init->bios;
658 u8 count = nvbios_rd08(bios, init->offset + 1);
659 u16 repeat = init->repeat;
661 trace("REPEAT\t0x%02x\n", count);
664 init->repeat = init->offset;
665 init->repend = init->offset;
667 init->offset = init->repeat;
670 trace("REPEAT\t0x%02x\n", count);
672 init->offset = init->repend;
673 init->repeat = repeat;
677 * INIT_IO_RESTRICT_PLL - opcode 0x34
681 init_io_restrict_pll(struct nvbios_init *init)
683 struct nvkm_bios *bios = init->bios;
684 u16 port = nvbios_rd16(bios, init->offset + 1);
685 u8 index = nvbios_rd08(bios, init->offset + 3);
686 u8 mask = nvbios_rd08(bios, init->offset + 4);
687 u8 shift = nvbios_rd08(bios, init->offset + 5);
688 s8 iofc = nvbios_rd08(bios, init->offset + 6);
689 u8 count = nvbios_rd08(bios, init->offset + 7);
690 u32 reg = nvbios_rd32(bios, init->offset + 8);
693 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
694 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
695 reg, port, index, mask, shift, iofc);
698 conf = (init_rdvgai(init, port, index) & mask) >> shift;
699 for (i = 0; i < count; i++) {
700 u32 freq = nvbios_rd16(bios, init->offset) * 10;
703 trace("\t%dkHz *\n", freq);
704 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
706 init_prog_pll(init, reg, freq);
708 trace("\t%dkHz\n", freq);
717 * INIT_END_REPEAT - opcode 0x36
721 init_end_repeat(struct nvbios_init *init)
723 trace("END_REPEAT\n");
727 init->repend = init->offset;
733 * INIT_COPY - opcode 0x37
737 init_copy(struct nvbios_init *init)
739 struct nvkm_bios *bios = init->bios;
740 u32 reg = nvbios_rd32(bios, init->offset + 1);
741 u8 shift = nvbios_rd08(bios, init->offset + 5);
742 u8 smask = nvbios_rd08(bios, init->offset + 6);
743 u16 port = nvbios_rd16(bios, init->offset + 7);
744 u8 index = nvbios_rd08(bios, init->offset + 9);
745 u8 mask = nvbios_rd08(bios, init->offset + 10);
748 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
749 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
750 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
751 (shift & 0x80) ? (0x100 - shift) : shift, smask);
754 data = init_rdvgai(init, port, index) & mask;
755 data |= init_shift(init_rd32(init, reg), shift) & smask;
756 init_wrvgai(init, port, index, data);
760 * INIT_NOT - opcode 0x38
764 init_not(struct nvbios_init *init)
772 * INIT_IO_FLAG_CONDITION - opcode 0x39
776 init_io_flag_condition(struct nvbios_init *init)
778 struct nvkm_bios *bios = init->bios;
779 u8 cond = nvbios_rd08(bios, init->offset + 1);
781 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
784 if (!init_io_flag_condition_met(init, cond))
785 init_exec_set(init, false);
789 * INIT_GENERIC_CONDITION - opcode 0x3a
793 init_generic_condition(struct nvbios_init *init)
795 struct nvkm_bios *bios = init->bios;
796 struct nvbios_dpout info;
797 u8 cond = nvbios_rd08(bios, init->offset + 1);
798 u8 size = nvbios_rd08(bios, init->offset + 2);
799 u8 ver, hdr, cnt, len;
802 trace("GENERIC_CONDITION\t0x%02x 0x%02x\n", cond, size);
807 if (init_conn(init) != DCB_CONNECTOR_eDP)
808 init_exec_set(init, false);
813 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
814 (init->outp->or << 0) |
815 (init->outp->sorconf.link << 6),
816 &ver, &hdr, &cnt, &len, &info)))
818 if (!(info.flags & cond))
819 init_exec_set(init, false);
824 warn("script needs dp output table data\n");
827 if (!(init_rdauxr(init, 0x0d) & 1))
828 init_exec_set(init, false);
831 warn("INIT_GENERIC_CONDITON: unknown 0x%02x\n", cond);
832 init->offset += size;
838 * INIT_IO_MASK_OR - opcode 0x3b
842 init_io_mask_or(struct nvbios_init *init)
844 struct nvkm_bios *bios = init->bios;
845 u8 index = nvbios_rd08(bios, init->offset + 1);
846 u8 or = init_or(init);
849 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
852 data = init_rdvgai(init, 0x03d4, index);
853 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
857 * INIT_IO_OR - opcode 0x3c
861 init_io_or(struct nvbios_init *init)
863 struct nvkm_bios *bios = init->bios;
864 u8 index = nvbios_rd08(bios, init->offset + 1);
865 u8 or = init_or(init);
868 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
871 data = init_rdvgai(init, 0x03d4, index);
872 init_wrvgai(init, 0x03d4, index, data | (1 << or));
876 * INIT_ANDN_REG - opcode 0x47
880 init_andn_reg(struct nvbios_init *init)
882 struct nvkm_bios *bios = init->bios;
883 u32 reg = nvbios_rd32(bios, init->offset + 1);
884 u32 mask = nvbios_rd32(bios, init->offset + 5);
886 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
889 init_mask(init, reg, mask, 0);
893 * INIT_OR_REG - opcode 0x48
897 init_or_reg(struct nvbios_init *init)
899 struct nvkm_bios *bios = init->bios;
900 u32 reg = nvbios_rd32(bios, init->offset + 1);
901 u32 mask = nvbios_rd32(bios, init->offset + 5);
903 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
906 init_mask(init, reg, 0, mask);
910 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
914 init_idx_addr_latched(struct nvbios_init *init)
916 struct nvkm_bios *bios = init->bios;
917 u32 creg = nvbios_rd32(bios, init->offset + 1);
918 u32 dreg = nvbios_rd32(bios, init->offset + 5);
919 u32 mask = nvbios_rd32(bios, init->offset + 9);
920 u32 data = nvbios_rd32(bios, init->offset + 13);
921 u8 count = nvbios_rd08(bios, init->offset + 17);
923 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
924 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
928 u8 iaddr = nvbios_rd08(bios, init->offset + 0);
929 u8 idata = nvbios_rd08(bios, init->offset + 1);
931 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
934 init_wr32(init, dreg, idata);
935 init_mask(init, creg, ~mask, data | iaddr);
940 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
944 init_io_restrict_pll2(struct nvbios_init *init)
946 struct nvkm_bios *bios = init->bios;
947 u16 port = nvbios_rd16(bios, init->offset + 1);
948 u8 index = nvbios_rd08(bios, init->offset + 3);
949 u8 mask = nvbios_rd08(bios, init->offset + 4);
950 u8 shift = nvbios_rd08(bios, init->offset + 5);
951 u8 count = nvbios_rd08(bios, init->offset + 6);
952 u32 reg = nvbios_rd32(bios, init->offset + 7);
955 trace("IO_RESTRICT_PLL2\t"
956 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
957 reg, port, index, mask, shift);
960 conf = (init_rdvgai(init, port, index) & mask) >> shift;
961 for (i = 0; i < count; i++) {
962 u32 freq = nvbios_rd32(bios, init->offset);
964 trace("\t%dkHz *\n", freq);
965 init_prog_pll(init, reg, freq);
967 trace("\t%dkHz\n", freq);
975 * INIT_PLL2 - opcode 0x4b
979 init_pll2(struct nvbios_init *init)
981 struct nvkm_bios *bios = init->bios;
982 u32 reg = nvbios_rd32(bios, init->offset + 1);
983 u32 freq = nvbios_rd32(bios, init->offset + 5);
985 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
988 init_prog_pll(init, reg, freq);
992 * INIT_I2C_BYTE - opcode 0x4c
996 init_i2c_byte(struct nvbios_init *init)
998 struct nvkm_bios *bios = init->bios;
999 u8 index = nvbios_rd08(bios, init->offset + 1);
1000 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1001 u8 count = nvbios_rd08(bios, init->offset + 3);
1003 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1007 u8 reg = nvbios_rd08(bios, init->offset + 0);
1008 u8 mask = nvbios_rd08(bios, init->offset + 1);
1009 u8 data = nvbios_rd08(bios, init->offset + 2);
1012 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1015 val = init_rdi2cr(init, index, addr, reg);
1018 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1023 * INIT_ZM_I2C_BYTE - opcode 0x4d
1027 init_zm_i2c_byte(struct nvbios_init *init)
1029 struct nvkm_bios *bios = init->bios;
1030 u8 index = nvbios_rd08(bios, init->offset + 1);
1031 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1032 u8 count = nvbios_rd08(bios, init->offset + 3);
1034 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1038 u8 reg = nvbios_rd08(bios, init->offset + 0);
1039 u8 data = nvbios_rd08(bios, init->offset + 1);
1041 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1044 init_wri2cr(init, index, addr, reg, data);
1049 * INIT_ZM_I2C - opcode 0x4e
1053 init_zm_i2c(struct nvbios_init *init)
1055 struct nvkm_bios *bios = init->bios;
1056 u8 index = nvbios_rd08(bios, init->offset + 1);
1057 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1058 u8 count = nvbios_rd08(bios, init->offset + 3);
1061 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1064 for (i = 0; i < count; i++) {
1065 data[i] = nvbios_rd08(bios, init->offset);
1066 trace("\t0x%02x\n", data[i]);
1070 if (init_exec(init)) {
1071 struct i2c_adapter *adap = init_i2c(init, index);
1072 struct i2c_msg msg = {
1073 .addr = addr, .flags = 0, .len = count, .buf = data,
1077 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1)
1078 warn("i2c wr failed, %d\n", ret);
1083 * INIT_TMDS - opcode 0x4f
1087 init_tmds(struct nvbios_init *init)
1089 struct nvkm_bios *bios = init->bios;
1090 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1091 u8 addr = nvbios_rd08(bios, init->offset + 2);
1092 u8 mask = nvbios_rd08(bios, init->offset + 3);
1093 u8 data = nvbios_rd08(bios, init->offset + 4);
1094 u32 reg = init_tmds_reg(init, tmds);
1096 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1097 tmds, addr, mask, data);
1103 init_wr32(init, reg + 0, addr | 0x00010000);
1104 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1105 init_wr32(init, reg + 0, addr);
1109 * INIT_ZM_TMDS_GROUP - opcode 0x50
1113 init_zm_tmds_group(struct nvbios_init *init)
1115 struct nvkm_bios *bios = init->bios;
1116 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1117 u8 count = nvbios_rd08(bios, init->offset + 2);
1118 u32 reg = init_tmds_reg(init, tmds);
1120 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1124 u8 addr = nvbios_rd08(bios, init->offset + 0);
1125 u8 data = nvbios_rd08(bios, init->offset + 1);
1127 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1130 init_wr32(init, reg + 4, data);
1131 init_wr32(init, reg + 0, addr);
1136 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1140 init_cr_idx_adr_latch(struct nvbios_init *init)
1142 struct nvkm_bios *bios = init->bios;
1143 u8 addr0 = nvbios_rd08(bios, init->offset + 1);
1144 u8 addr1 = nvbios_rd08(bios, init->offset + 2);
1145 u8 base = nvbios_rd08(bios, init->offset + 3);
1146 u8 count = nvbios_rd08(bios, init->offset + 4);
1149 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1152 save0 = init_rdvgai(init, 0x03d4, addr0);
1154 u8 data = nvbios_rd08(bios, init->offset);
1156 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1159 init_wrvgai(init, 0x03d4, addr0, base++);
1160 init_wrvgai(init, 0x03d4, addr1, data);
1162 init_wrvgai(init, 0x03d4, addr0, save0);
1166 * INIT_CR - opcode 0x52
1170 init_cr(struct nvbios_init *init)
1172 struct nvkm_bios *bios = init->bios;
1173 u8 addr = nvbios_rd08(bios, init->offset + 1);
1174 u8 mask = nvbios_rd08(bios, init->offset + 2);
1175 u8 data = nvbios_rd08(bios, init->offset + 3);
1178 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1181 val = init_rdvgai(init, 0x03d4, addr) & mask;
1182 init_wrvgai(init, 0x03d4, addr, val | data);
1186 * INIT_ZM_CR - opcode 0x53
1190 init_zm_cr(struct nvbios_init *init)
1192 struct nvkm_bios *bios = init->bios;
1193 u8 addr = nvbios_rd08(bios, init->offset + 1);
1194 u8 data = nvbios_rd08(bios, init->offset + 2);
1196 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1199 init_wrvgai(init, 0x03d4, addr, data);
1203 * INIT_ZM_CR_GROUP - opcode 0x54
1207 init_zm_cr_group(struct nvbios_init *init)
1209 struct nvkm_bios *bios = init->bios;
1210 u8 count = nvbios_rd08(bios, init->offset + 1);
1212 trace("ZM_CR_GROUP\n");
1216 u8 addr = nvbios_rd08(bios, init->offset + 0);
1217 u8 data = nvbios_rd08(bios, init->offset + 1);
1219 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1222 init_wrvgai(init, 0x03d4, addr, data);
1227 * INIT_CONDITION_TIME - opcode 0x56
1231 init_condition_time(struct nvbios_init *init)
1233 struct nvkm_bios *bios = init->bios;
1234 u8 cond = nvbios_rd08(bios, init->offset + 1);
1235 u8 retry = nvbios_rd08(bios, init->offset + 2);
1236 u8 wait = min((u16)retry * 50, 100);
1238 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1241 if (!init_exec(init))
1245 if (init_condition_met(init, cond))
1250 init_exec_set(init, false);
1254 * INIT_LTIME - opcode 0x57
1258 init_ltime(struct nvbios_init *init)
1260 struct nvkm_bios *bios = init->bios;
1261 u16 msec = nvbios_rd16(bios, init->offset + 1);
1263 trace("LTIME\t0x%04x\n", msec);
1266 if (init_exec(init))
1271 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1275 init_zm_reg_sequence(struct nvbios_init *init)
1277 struct nvkm_bios *bios = init->bios;
1278 u32 base = nvbios_rd32(bios, init->offset + 1);
1279 u8 count = nvbios_rd08(bios, init->offset + 5);
1281 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1285 u32 data = nvbios_rd32(bios, init->offset);
1287 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1290 init_wr32(init, base, data);
1296 * INIT_PLL_INDIRECT - opcode 0x59
1300 init_pll_indirect(struct nvbios_init *init)
1302 struct nvkm_bios *bios = init->bios;
1303 u32 reg = nvbios_rd32(bios, init->offset + 1);
1304 u16 addr = nvbios_rd16(bios, init->offset + 5);
1305 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000;
1307 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1311 init_prog_pll(init, reg, freq);
1315 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1319 init_zm_reg_indirect(struct nvbios_init *init)
1321 struct nvkm_bios *bios = init->bios;
1322 u32 reg = nvbios_rd32(bios, init->offset + 1);
1323 u16 addr = nvbios_rd16(bios, init->offset + 5);
1324 u32 data = nvbios_rd32(bios, addr);
1326 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1330 init_wr32(init, addr, data);
1334 * INIT_SUB_DIRECT - opcode 0x5b
1338 init_sub_direct(struct nvbios_init *init)
1340 struct nvkm_bios *bios = init->bios;
1341 u16 addr = nvbios_rd16(bios, init->offset + 1);
1344 trace("SUB_DIRECT\t0x%04x\n", addr);
1346 if (init_exec(init)) {
1347 save = init->offset;
1348 init->offset = addr;
1349 if (nvbios_exec(init)) {
1350 error("error parsing sub-table\n");
1353 init->offset = save;
1360 * INIT_JUMP - opcode 0x5c
1364 init_jump(struct nvbios_init *init)
1366 struct nvkm_bios *bios = init->bios;
1367 u16 offset = nvbios_rd16(bios, init->offset + 1);
1369 trace("JUMP\t0x%04x\n", offset);
1371 if (init_exec(init))
1372 init->offset = offset;
1378 * INIT_I2C_IF - opcode 0x5e
1382 init_i2c_if(struct nvbios_init *init)
1384 struct nvkm_bios *bios = init->bios;
1385 u8 index = nvbios_rd08(bios, init->offset + 1);
1386 u8 addr = nvbios_rd08(bios, init->offset + 2);
1387 u8 reg = nvbios_rd08(bios, init->offset + 3);
1388 u8 mask = nvbios_rd08(bios, init->offset + 4);
1389 u8 data = nvbios_rd08(bios, init->offset + 5);
1392 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1393 index, addr, reg, mask, data);
1395 init_exec_force(init, true);
1397 value = init_rdi2cr(init, index, addr, reg);
1398 if ((value & mask) != data)
1399 init_exec_set(init, false);
1401 init_exec_force(init, false);
1405 * INIT_COPY_NV_REG - opcode 0x5f
1409 init_copy_nv_reg(struct nvbios_init *init)
1411 struct nvkm_bios *bios = init->bios;
1412 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1413 u8 shift = nvbios_rd08(bios, init->offset + 5);
1414 u32 smask = nvbios_rd32(bios, init->offset + 6);
1415 u32 sxor = nvbios_rd32(bios, init->offset + 10);
1416 u32 dreg = nvbios_rd32(bios, init->offset + 14);
1417 u32 dmask = nvbios_rd32(bios, init->offset + 18);
1420 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1421 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1422 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1423 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1426 data = init_shift(init_rd32(init, sreg), shift);
1427 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1431 * INIT_ZM_INDEX_IO - opcode 0x62
1435 init_zm_index_io(struct nvbios_init *init)
1437 struct nvkm_bios *bios = init->bios;
1438 u16 port = nvbios_rd16(bios, init->offset + 1);
1439 u8 index = nvbios_rd08(bios, init->offset + 3);
1440 u8 data = nvbios_rd08(bios, init->offset + 4);
1442 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1445 init_wrvgai(init, port, index, data);
1449 * INIT_COMPUTE_MEM - opcode 0x63
1453 init_compute_mem(struct nvbios_init *init)
1455 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
1457 trace("COMPUTE_MEM\n");
1460 init_exec_force(init, true);
1461 if (init_exec(init))
1462 nvkm_devinit_meminit(devinit);
1463 init_exec_force(init, false);
1467 * INIT_RESET - opcode 0x65
1471 init_reset(struct nvbios_init *init)
1473 struct nvkm_bios *bios = init->bios;
1474 u32 reg = nvbios_rd32(bios, init->offset + 1);
1475 u32 data1 = nvbios_rd32(bios, init->offset + 5);
1476 u32 data2 = nvbios_rd32(bios, init->offset + 9);
1479 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1481 init_exec_force(init, true);
1483 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1484 init_wr32(init, reg, data1);
1486 init_wr32(init, reg, data2);
1487 init_wr32(init, 0x00184c, savepci19);
1488 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1490 init_exec_force(init, false);
1494 * INIT_CONFIGURE_MEM - opcode 0x66
1498 init_configure_mem_clk(struct nvbios_init *init)
1500 u16 mdata = bmp_mem_init_table(init->bios);
1502 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1507 init_configure_mem(struct nvbios_init *init)
1509 struct nvkm_bios *bios = init->bios;
1513 trace("CONFIGURE_MEM\n");
1516 if (bios->version.major > 2) {
1520 init_exec_force(init, true);
1522 mdata = init_configure_mem_clk(init);
1523 sdata = bmp_sdr_seq_table(bios);
1524 if (nvbios_rd08(bios, mdata) & 0x01)
1525 sdata = bmp_ddr_seq_table(bios);
1526 mdata += 6; /* skip to data */
1528 data = init_rdvgai(init, 0x03c4, 0x01);
1529 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1531 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) {
1533 case 0x10021c: /* CKE_NORMAL */
1534 case 0x1002d0: /* CMD_REFRESH */
1535 case 0x1002d4: /* CMD_PRECHARGE */
1539 data = nvbios_rd32(bios, mdata);
1541 if (data == 0xffffffff)
1546 init_wr32(init, addr, data);
1549 init_exec_force(init, false);
1553 * INIT_CONFIGURE_CLK - opcode 0x67
1557 init_configure_clk(struct nvbios_init *init)
1559 struct nvkm_bios *bios = init->bios;
1562 trace("CONFIGURE_CLK\n");
1565 if (bios->version.major > 2) {
1569 init_exec_force(init, true);
1571 mdata = init_configure_mem_clk(init);
1574 clock = nvbios_rd16(bios, mdata + 4) * 10;
1575 init_prog_pll(init, 0x680500, clock);
1578 clock = nvbios_rd16(bios, mdata + 2) * 10;
1579 if (nvbios_rd08(bios, mdata) & 0x01)
1581 init_prog_pll(init, 0x680504, clock);
1583 init_exec_force(init, false);
1587 * INIT_CONFIGURE_PREINIT - opcode 0x68
1591 init_configure_preinit(struct nvbios_init *init)
1593 struct nvkm_bios *bios = init->bios;
1596 trace("CONFIGURE_PREINIT\n");
1599 if (bios->version.major > 2) {
1603 init_exec_force(init, true);
1605 strap = init_rd32(init, 0x101000);
1606 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1607 init_wrvgai(init, 0x03d4, 0x3c, strap);
1609 init_exec_force(init, false);
1613 * INIT_IO - opcode 0x69
1617 init_io(struct nvbios_init *init)
1619 struct nvkm_bios *bios = init->bios;
1620 u16 port = nvbios_rd16(bios, init->offset + 1);
1621 u8 mask = nvbios_rd16(bios, init->offset + 3);
1622 u8 data = nvbios_rd16(bios, init->offset + 4);
1625 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1628 /* ummm.. yes.. should really figure out wtf this is and why it's
1629 * needed some day.. it's almost certainly wrong, but, it also
1630 * somehow makes things work...
1632 if (bios->subdev.device->card_type >= NV_50 &&
1633 port == 0x03c3 && data == 0x01) {
1634 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1635 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1636 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1637 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1639 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1640 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1641 init_wr32(init, 0x614100, 0x00800018);
1642 init_wr32(init, 0x614900, 0x00800018);
1644 init_wr32(init, 0x614100, 0x10000018);
1645 init_wr32(init, 0x614900, 0x10000018);
1648 value = init_rdport(init, port) & mask;
1649 init_wrport(init, port, data | value);
1653 * INIT_SUB - opcode 0x6b
1657 init_sub(struct nvbios_init *init)
1659 struct nvkm_bios *bios = init->bios;
1660 u8 index = nvbios_rd08(bios, init->offset + 1);
1663 trace("SUB\t0x%02x\n", index);
1665 addr = init_script(bios, index);
1666 if (addr && init_exec(init)) {
1667 save = init->offset;
1668 init->offset = addr;
1669 if (nvbios_exec(init)) {
1670 error("error parsing sub-table\n");
1673 init->offset = save;
1680 * INIT_RAM_CONDITION - opcode 0x6d
1684 init_ram_condition(struct nvbios_init *init)
1686 struct nvkm_bios *bios = init->bios;
1687 u8 mask = nvbios_rd08(bios, init->offset + 1);
1688 u8 value = nvbios_rd08(bios, init->offset + 2);
1690 trace("RAM_CONDITION\t"
1691 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1694 if ((init_rd32(init, 0x100000) & mask) != value)
1695 init_exec_set(init, false);
1699 * INIT_NV_REG - opcode 0x6e
1703 init_nv_reg(struct nvbios_init *init)
1705 struct nvkm_bios *bios = init->bios;
1706 u32 reg = nvbios_rd32(bios, init->offset + 1);
1707 u32 mask = nvbios_rd32(bios, init->offset + 5);
1708 u32 data = nvbios_rd32(bios, init->offset + 9);
1710 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1713 init_mask(init, reg, ~mask, data);
1717 * INIT_MACRO - opcode 0x6f
1721 init_macro(struct nvbios_init *init)
1723 struct nvkm_bios *bios = init->bios;
1724 u8 macro = nvbios_rd08(bios, init->offset + 1);
1727 trace("MACRO\t0x%02x\n", macro);
1729 table = init_macro_table(init);
1731 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0);
1732 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4);
1733 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1734 init_wr32(init, addr, data);
1741 * INIT_RESUME - opcode 0x72
1745 init_resume(struct nvbios_init *init)
1749 init_exec_set(init, true);
1753 * INIT_STRAP_CONDITION - opcode 0x73
1757 init_strap_condition(struct nvbios_init *init)
1759 struct nvkm_bios *bios = init->bios;
1760 u32 mask = nvbios_rd32(bios, init->offset + 1);
1761 u32 value = nvbios_rd32(bios, init->offset + 5);
1763 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value);
1766 if ((init_rd32(init, 0x101000) & mask) != value)
1767 init_exec_set(init, false);
1771 * INIT_TIME - opcode 0x74
1775 init_time(struct nvbios_init *init)
1777 struct nvkm_bios *bios = init->bios;
1778 u16 usec = nvbios_rd16(bios, init->offset + 1);
1780 trace("TIME\t0x%04x\n", usec);
1783 if (init_exec(init)) {
1787 mdelay((usec + 900) / 1000);
1792 * INIT_CONDITION - opcode 0x75
1796 init_condition(struct nvbios_init *init)
1798 struct nvkm_bios *bios = init->bios;
1799 u8 cond = nvbios_rd08(bios, init->offset + 1);
1801 trace("CONDITION\t0x%02x\n", cond);
1804 if (!init_condition_met(init, cond))
1805 init_exec_set(init, false);
1809 * INIT_IO_CONDITION - opcode 0x76
1813 init_io_condition(struct nvbios_init *init)
1815 struct nvkm_bios *bios = init->bios;
1816 u8 cond = nvbios_rd08(bios, init->offset + 1);
1818 trace("IO_CONDITION\t0x%02x\n", cond);
1821 if (!init_io_condition_met(init, cond))
1822 init_exec_set(init, false);
1826 * INIT_ZM_REG16 - opcode 0x77
1830 init_zm_reg16(struct nvbios_init *init)
1832 struct nvkm_bios *bios = init->bios;
1833 u32 addr = nvbios_rd32(bios, init->offset + 1);
1834 u16 data = nvbios_rd16(bios, init->offset + 5);
1836 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data);
1839 init_wr32(init, addr, data);
1843 * INIT_INDEX_IO - opcode 0x78
1847 init_index_io(struct nvbios_init *init)
1849 struct nvkm_bios *bios = init->bios;
1850 u16 port = nvbios_rd16(bios, init->offset + 1);
1851 u8 index = nvbios_rd16(bios, init->offset + 3);
1852 u8 mask = nvbios_rd08(bios, init->offset + 4);
1853 u8 data = nvbios_rd08(bios, init->offset + 5);
1856 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1857 port, index, mask, data);
1860 value = init_rdvgai(init, port, index) & mask;
1861 init_wrvgai(init, port, index, data | value);
1865 * INIT_PLL - opcode 0x79
1869 init_pll(struct nvbios_init *init)
1871 struct nvkm_bios *bios = init->bios;
1872 u32 reg = nvbios_rd32(bios, init->offset + 1);
1873 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10;
1875 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1878 init_prog_pll(init, reg, freq);
1882 * INIT_ZM_REG - opcode 0x7a
1886 init_zm_reg(struct nvbios_init *init)
1888 struct nvkm_bios *bios = init->bios;
1889 u32 addr = nvbios_rd32(bios, init->offset + 1);
1890 u32 data = nvbios_rd32(bios, init->offset + 5);
1892 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1895 if (addr == 0x000200)
1898 init_wr32(init, addr, data);
1902 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1906 init_ram_restrict_pll(struct nvbios_init *init)
1908 struct nvkm_bios *bios = init->bios;
1909 u8 type = nvbios_rd08(bios, init->offset + 1);
1910 u8 count = init_ram_restrict_group_count(init);
1911 u8 strap = init_ram_restrict(init);
1914 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1917 for (cconf = 0; cconf < count; cconf++) {
1918 u32 freq = nvbios_rd32(bios, init->offset);
1920 if (cconf == strap) {
1921 trace("%dkHz *\n", freq);
1922 init_prog_pll(init, type, freq);
1924 trace("%dkHz\n", freq);
1932 * INIT_GPIO - opcode 0x8e
1936 init_gpio(struct nvbios_init *init)
1938 struct nvkm_gpio *gpio = init->bios->subdev.device->gpio;
1943 if (init_exec(init))
1944 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED);
1948 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1952 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1954 struct nvkm_bios *bios = init->bios;
1955 u32 addr = nvbios_rd32(bios, init->offset + 1);
1956 u8 incr = nvbios_rd08(bios, init->offset + 5);
1957 u8 num = nvbios_rd08(bios, init->offset + 6);
1958 u8 count = init_ram_restrict_group_count(init);
1959 u8 index = init_ram_restrict(init);
1962 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1963 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1966 for (i = 0; i < num; i++) {
1967 trace("\tR[0x%06x] = {\n", addr);
1968 for (j = 0; j < count; j++) {
1969 u32 data = nvbios_rd32(bios, init->offset);
1972 trace("\t\t0x%08x *\n", data);
1973 init_wr32(init, addr, data);
1975 trace("\t\t0x%08x\n", data);
1986 * INIT_COPY_ZM_REG - opcode 0x90
1990 init_copy_zm_reg(struct nvbios_init *init)
1992 struct nvkm_bios *bios = init->bios;
1993 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1994 u32 dreg = nvbios_rd32(bios, init->offset + 5);
1996 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1999 init_wr32(init, dreg, init_rd32(init, sreg));
2003 * INIT_ZM_REG_GROUP - opcode 0x91
2007 init_zm_reg_group(struct nvbios_init *init)
2009 struct nvkm_bios *bios = init->bios;
2010 u32 addr = nvbios_rd32(bios, init->offset + 1);
2011 u8 count = nvbios_rd08(bios, init->offset + 5);
2013 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
2017 u32 data = nvbios_rd32(bios, init->offset);
2018 trace("\t0x%08x\n", data);
2019 init_wr32(init, addr, data);
2025 * INIT_XLAT - opcode 0x96
2029 init_xlat(struct nvbios_init *init)
2031 struct nvkm_bios *bios = init->bios;
2032 u32 saddr = nvbios_rd32(bios, init->offset + 1);
2033 u8 sshift = nvbios_rd08(bios, init->offset + 5);
2034 u8 smask = nvbios_rd08(bios, init->offset + 6);
2035 u8 index = nvbios_rd08(bios, init->offset + 7);
2036 u32 daddr = nvbios_rd32(bios, init->offset + 8);
2037 u32 dmask = nvbios_rd32(bios, init->offset + 12);
2038 u8 shift = nvbios_rd08(bios, init->offset + 16);
2041 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
2042 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2043 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2044 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2047 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2048 data = init_xlat_(init, index, data) << shift;
2049 init_mask(init, daddr, ~dmask, data);
2053 * INIT_ZM_MASK_ADD - opcode 0x97
2057 init_zm_mask_add(struct nvbios_init *init)
2059 struct nvkm_bios *bios = init->bios;
2060 u32 addr = nvbios_rd32(bios, init->offset + 1);
2061 u32 mask = nvbios_rd32(bios, init->offset + 5);
2062 u32 add = nvbios_rd32(bios, init->offset + 9);
2065 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2068 data = init_rd32(init, addr);
2069 data = (data & mask) | ((data + add) & ~mask);
2070 init_wr32(init, addr, data);
2074 * INIT_AUXCH - opcode 0x98
2078 init_auxch(struct nvbios_init *init)
2080 struct nvkm_bios *bios = init->bios;
2081 u32 addr = nvbios_rd32(bios, init->offset + 1);
2082 u8 count = nvbios_rd08(bios, init->offset + 5);
2084 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2088 u8 mask = nvbios_rd08(bios, init->offset + 0);
2089 u8 data = nvbios_rd08(bios, init->offset + 1);
2090 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2091 mask = init_rdauxr(init, addr) & mask;
2092 init_wrauxr(init, addr, mask | data);
2098 * INIT_AUXCH - opcode 0x99
2102 init_zm_auxch(struct nvbios_init *init)
2104 struct nvkm_bios *bios = init->bios;
2105 u32 addr = nvbios_rd32(bios, init->offset + 1);
2106 u8 count = nvbios_rd08(bios, init->offset + 5);
2108 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2112 u8 data = nvbios_rd08(bios, init->offset + 0);
2113 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2114 init_wrauxr(init, addr, data);
2120 * INIT_I2C_LONG_IF - opcode 0x9a
2124 init_i2c_long_if(struct nvbios_init *init)
2126 struct nvkm_bios *bios = init->bios;
2127 u8 index = nvbios_rd08(bios, init->offset + 1);
2128 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
2129 u8 reglo = nvbios_rd08(bios, init->offset + 3);
2130 u8 reghi = nvbios_rd08(bios, init->offset + 4);
2131 u8 mask = nvbios_rd08(bios, init->offset + 5);
2132 u8 data = nvbios_rd08(bios, init->offset + 6);
2133 struct i2c_adapter *adap;
2135 trace("I2C_LONG_IF\t"
2136 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2137 index, addr, reglo, reghi, mask, data);
2140 adap = init_i2c(init, index);
2142 u8 i[2] = { reghi, reglo };
2144 struct i2c_msg msg[] = {
2145 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2146 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2150 ret = i2c_transfer(adap, msg, 2);
2151 if (ret == 2 && ((o[0] & mask) == data))
2155 init_exec_set(init, false);
2159 * INIT_GPIO_NE - opcode 0xa9
2163 init_gpio_ne(struct nvbios_init *init)
2165 struct nvkm_bios *bios = init->bios;
2166 struct nvkm_gpio *gpio = bios->subdev.device->gpio;
2167 struct dcb_gpio_func func;
2168 u8 count = nvbios_rd08(bios, init->offset + 1);
2169 u8 idx = 0, ver, len;
2175 for (i = init->offset; i < init->offset + count; i++)
2176 cont("0x%02x ", nvbios_rd08(bios, i));
2179 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2180 if (func.func != DCB_GPIO_UNUSED) {
2181 for (i = init->offset; i < init->offset + count; i++) {
2182 if (func.func == nvbios_rd08(bios, i))
2186 trace("\tFUNC[0x%02x]", func.func);
2187 if (i == (init->offset + count)) {
2189 if (init_exec(init))
2190 nvkm_gpio_reset(gpio, func.func);
2196 init->offset += count;
2199 static struct nvbios_init_opcode {
2200 void (*exec)(struct nvbios_init *);
2202 [0x32] = { init_io_restrict_prog },
2203 [0x33] = { init_repeat },
2204 [0x34] = { init_io_restrict_pll },
2205 [0x36] = { init_end_repeat },
2206 [0x37] = { init_copy },
2207 [0x38] = { init_not },
2208 [0x39] = { init_io_flag_condition },
2209 [0x3a] = { init_generic_condition },
2210 [0x3b] = { init_io_mask_or },
2211 [0x3c] = { init_io_or },
2212 [0x47] = { init_andn_reg },
2213 [0x48] = { init_or_reg },
2214 [0x49] = { init_idx_addr_latched },
2215 [0x4a] = { init_io_restrict_pll2 },
2216 [0x4b] = { init_pll2 },
2217 [0x4c] = { init_i2c_byte },
2218 [0x4d] = { init_zm_i2c_byte },
2219 [0x4e] = { init_zm_i2c },
2220 [0x4f] = { init_tmds },
2221 [0x50] = { init_zm_tmds_group },
2222 [0x51] = { init_cr_idx_adr_latch },
2223 [0x52] = { init_cr },
2224 [0x53] = { init_zm_cr },
2225 [0x54] = { init_zm_cr_group },
2226 [0x56] = { init_condition_time },
2227 [0x57] = { init_ltime },
2228 [0x58] = { init_zm_reg_sequence },
2229 [0x59] = { init_pll_indirect },
2230 [0x5a] = { init_zm_reg_indirect },
2231 [0x5b] = { init_sub_direct },
2232 [0x5c] = { init_jump },
2233 [0x5e] = { init_i2c_if },
2234 [0x5f] = { init_copy_nv_reg },
2235 [0x62] = { init_zm_index_io },
2236 [0x63] = { init_compute_mem },
2237 [0x65] = { init_reset },
2238 [0x66] = { init_configure_mem },
2239 [0x67] = { init_configure_clk },
2240 [0x68] = { init_configure_preinit },
2241 [0x69] = { init_io },
2242 [0x6b] = { init_sub },
2243 [0x6d] = { init_ram_condition },
2244 [0x6e] = { init_nv_reg },
2245 [0x6f] = { init_macro },
2246 [0x71] = { init_done },
2247 [0x72] = { init_resume },
2248 [0x73] = { init_strap_condition },
2249 [0x74] = { init_time },
2250 [0x75] = { init_condition },
2251 [0x76] = { init_io_condition },
2252 [0x77] = { init_zm_reg16 },
2253 [0x78] = { init_index_io },
2254 [0x79] = { init_pll },
2255 [0x7a] = { init_zm_reg },
2256 [0x87] = { init_ram_restrict_pll },
2257 [0x8c] = { init_reserved },
2258 [0x8d] = { init_reserved },
2259 [0x8e] = { init_gpio },
2260 [0x8f] = { init_ram_restrict_zm_reg_group },
2261 [0x90] = { init_copy_zm_reg },
2262 [0x91] = { init_zm_reg_group },
2263 [0x92] = { init_reserved },
2264 [0x96] = { init_xlat },
2265 [0x97] = { init_zm_mask_add },
2266 [0x98] = { init_auxch },
2267 [0x99] = { init_zm_auxch },
2268 [0x9a] = { init_i2c_long_if },
2269 [0xa9] = { init_gpio_ne },
2270 [0xaa] = { init_reserved },
2273 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2276 nvbios_exec(struct nvbios_init *init)
2279 while (init->offset) {
2280 u8 opcode = nvbios_rd08(init->bios, init->offset);
2281 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2282 error("unknown opcode 0x%02x\n", opcode);
2286 init_opcode[opcode].exec(init);
2293 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2295 struct nvkm_bios *bios = subdev->device->bios;
2301 nvkm_debug(subdev, "running init tables\n");
2302 while (!ret && (data = (init_script(bios, ++i)))) {
2303 struct nvbios_init init = {
2309 .execute = execute ? 1 : 0,
2312 ret = nvbios_exec(&init);
2315 /* the vbios parser will run this right after the normal init
2316 * tables, whereas the binary driver appears to run it later.
2318 if (!ret && (data = init_unknown_script(bios))) {
2319 struct nvbios_init init = {
2325 .execute = execute ? 1 : 0,
2328 ret = nvbios_exec(&init);