include/ufs/ufshci.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Universal Flash Storage Host controller driver
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  *
   6  * Authors:
   7  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   8  *      Vinayak Holikatti <h.vinayak@samsung.com>
   9  */
  10
  11 #ifndef _UFSHCI_H
  12 #define _UFSHCI_H
  13
  14 #include <scsi/scsi_host.h>
  15
  16 enum {
  17         TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  18         TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  19         ALIGNED_UPIU_SIZE               = 512,
  20 };
  21
  22 /* UFSHCI Registers */
  23 enum {
  24         REG_CONTROLLER_CAPABILITIES             = 0x00,
  25         REG_UFS_VERSION                         = 0x08,
  26         REG_CONTROLLER_DEV_ID                   = 0x10,
  27         REG_CONTROLLER_PROD_ID                  = 0x14,
  28         REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
  29         REG_INTERRUPT_STATUS                    = 0x20,
  30         REG_INTERRUPT_ENABLE                    = 0x24,
  31         REG_CONTROLLER_STATUS                   = 0x30,
  32         REG_CONTROLLER_ENABLE                   = 0x34,
  33         REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  34         REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  35         REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  36         REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  37         REG_UIC_ERROR_CODE_DME                  = 0x48,
  38         REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  39         REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  40         REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  41         REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  42         REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  43         REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  44         REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  45         REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  46         REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  47         REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  48         REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  49         REG_UIC_COMMAND                         = 0x90,
  50         REG_UIC_COMMAND_ARG_1                   = 0x94,
  51         REG_UIC_COMMAND_ARG_2                   = 0x98,
  52         REG_UIC_COMMAND_ARG_3                   = 0x9C,
  53
  54         UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  55
  56         REG_UFS_CCAP                            = 0x100,
  57         REG_UFS_CRYPTOCAP                       = 0x104,
  58
  59         UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  60 };
  61
  62 /* Controller capability masks */
  63 enum {
  64         MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  65         MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  66         MASK_AUTO_HIBERN8_SUPPORT               = 0x00800000,
  67         MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  68         MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  69         MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  70         MASK_CRYPTO_SUPPORT                     = 0x10000000,
  71 };
  72
  73 #define UFS_MASK(mask, offset)          ((mask) << (offset))
  74
  75 /* UFS Version 08h */
  76 #define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
  77 #define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
  78
  79 /*
  80  * Controller UFSHCI version
  81  * - 2.x and newer use the following scheme:
  82  *   major << 8 + minor << 4
  83  * - 1.x has been converted to match this in
  84  *   ufshcd_get_ufs_version()
  85  */
  86 static inline u32 ufshci_version(u32 major, u32 minor)
  87 {
  88         return (major << 8) + (minor << 4);
  89 }
  90
  91 /*
  92  * HCDDID - Host Controller Identification Descriptor
  93  *        - Device ID and Device Class 10h
  94  */
  95 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
  96 #define DEVICE_ID       UFS_MASK(0xFF, 24)
  97
  98 /*
  99  * HCPMID - Host Controller Identification Descriptor
 100  *        - Product/Manufacturer ID  14h
 101  */
 102 #define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 103 #define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 104
 105 /* AHIT - Auto-Hibernate Idle Timer */
 106 #define UFSHCI_AHIBERN8_TIMER_MASK              GENMASK(9, 0)
 107 #define UFSHCI_AHIBERN8_SCALE_MASK              GENMASK(12, 10)
 108 #define UFSHCI_AHIBERN8_SCALE_FACTOR            10
 109 #define UFSHCI_AHIBERN8_MAX                     (1023 * 100000)
 110
 111 /*
 112  * IS - Interrupt Status - 20h
 113  */
 114 #define UTP_TRANSFER_REQ_COMPL                  0x1
 115 #define UIC_DME_END_PT_RESET                    0x2
 116 #define UIC_ERROR                               0x4
 117 #define UIC_TEST_MODE                           0x8
 118 #define UIC_POWER_MODE                          0x10
 119 #define UIC_HIBERNATE_EXIT                      0x20
 120 #define UIC_HIBERNATE_ENTER                     0x40
 121 #define UIC_LINK_LOST                           0x80
 122 #define UIC_LINK_STARTUP                        0x100
 123 #define UTP_TASK_REQ_COMPL                      0x200
 124 #define UIC_COMMAND_COMPL                       0x400
 125 #define DEVICE_FATAL_ERROR                      0x800
 126 #define CONTROLLER_FATAL_ERROR                  0x10000
 127 #define SYSTEM_BUS_FATAL_ERROR                  0x20000
 128 #define CRYPTO_ENGINE_FATAL_ERROR               0x40000
 129
 130 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
 131                                 UIC_HIBERNATE_EXIT)
 132
 133 #define UFSHCD_UIC_PWR_MASK     (UFSHCD_UIC_HIBERN8_MASK |\
 134                                 UIC_POWER_MODE)
 135
 136 #define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 137
 138 #define UFSHCD_ERROR_MASK       (UIC_ERROR | INT_FATAL_ERRORS)
 139
 140 #define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 141                                 CONTROLLER_FATAL_ERROR |\
 142                                 SYSTEM_BUS_FATAL_ERROR |\
 143                                 CRYPTO_ENGINE_FATAL_ERROR |\
 144                                 UIC_LINK_LOST)
 145
 146 /* HCS - Host Controller Status 30h */
 147 #define DEVICE_PRESENT                          0x1
 148 #define UTP_TRANSFER_REQ_LIST_READY             0x2
 149 #define UTP_TASK_REQ_LIST_READY                 0x4
 150 #define UIC_COMMAND_READY                       0x8
 151 #define HOST_ERROR_INDICATOR                    0x10
 152 #define DEVICE_ERROR_INDICATOR                  0x20
 153 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 154
 155 #define UFSHCD_STATUS_READY     (UTP_TRANSFER_REQ_LIST_READY |\
 156                                 UTP_TASK_REQ_LIST_READY |\
 157                                 UIC_COMMAND_READY)
 158
 159 enum {
 160         PWR_OK          = 0x0,
 161         PWR_LOCAL       = 0x01,
 162         PWR_REMOTE      = 0x02,
 163         PWR_BUSY        = 0x03,
 164         PWR_ERROR_CAP   = 0x04,
 165         PWR_FATAL_ERROR = 0x05,
 166 };
 167
 168 /* HCE - Host Controller Enable 34h */
 169 #define CONTROLLER_ENABLE       0x1
 170 #define CONTROLLER_DISABLE      0x0
 171 #define CRYPTO_GENERAL_ENABLE   0x2
 172
 173 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 174 #define UIC_PHY_ADAPTER_LAYER_ERROR                     0x80000000
 175 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 176 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 177 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR             0x10
 178
 179 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 180 #define UIC_DATA_LINK_LAYER_ERROR               0x80000000
 181 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0xFFFF
 182 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP     0x2
 183 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP    0x4
 184 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP     0x8
 185 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF     0x20
 186 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       0x2000
 187 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 188 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 189
 190 /* UECN - Host UIC Error Code Network Layer 40h */
 191 #define UIC_NETWORK_LAYER_ERROR                 0x80000000
 192 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 193 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE     0x1
 194 #define UIC_NETWORK_BAD_DEVICEID_ENC            0x2
 195 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING   0x4
 196
 197 /* UECT - Host UIC Error Code Transport Layer 44h */
 198 #define UIC_TRANSPORT_LAYER_ERROR               0x80000000
 199 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 200 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE   0x1
 201 #define UIC_TRANSPORT_UNKNOWN_CPORTID           0x2
 202 #define UIC_TRANSPORT_NO_CONNECTION_RX          0x4
 203 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING       0x8
 204 #define UIC_TRANSPORT_BAD_TC                    0x10
 205 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW        0x20
 206 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING     0x40
 207
 208 /* UECDME - Host UIC Error Code DME 48h */
 209 #define UIC_DME_ERROR                   0x80000000
 210 #define UIC_DME_ERROR_CODE_MASK         0x1
 211
 212 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
 213 #define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 214 #define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 215 #define INT_AGGR_COUNTER_AND_TIMER_RESET        0x10000
 216 #define INT_AGGR_STATUS_BIT                     0x100000
 217 #define INT_AGGR_PARAM_WRITE                    0x1000000
 218 #define INT_AGGR_ENABLE                         0x80000000
 219
 220 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 221 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      0x1
 222
 223 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 224 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT          0x1
 225
 226 /* UICCMD - UIC Command */
 227 #define COMMAND_OPCODE_MASK             0xFF
 228 #define GEN_SELECTOR_INDEX_MASK         0xFFFF
 229
 230 #define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 231 #define RESET_LEVEL                     0xFF
 232
 233 #define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 234 #define CONFIG_RESULT_CODE_MASK         0xFF
 235 #define GENERIC_ERROR_CODE_MASK         0xFF
 236
 237 /* GenSelectorIndex calculation macros for M-PHY attributes */
 238 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 239 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 240
 241 #define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 242                                          ((sel) & 0xFFFF))
 243 #define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 244 #define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 245 #define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 246
 247 /* Link Status*/
 248 enum link_status {
 249         UFSHCD_LINK_IS_DOWN     = 1,
 250         UFSHCD_LINK_IS_UP       = 2,
 251 };
 252
 253 /* UIC Commands */
 254 enum uic_cmd_dme {
 255         UIC_CMD_DME_GET                 = 0x01,
 256         UIC_CMD_DME_SET                 = 0x02,
 257         UIC_CMD_DME_PEER_GET            = 0x03,
 258         UIC_CMD_DME_PEER_SET            = 0x04,
 259         UIC_CMD_DME_POWERON             = 0x10,
 260         UIC_CMD_DME_POWEROFF            = 0x11,
 261         UIC_CMD_DME_ENABLE              = 0x12,
 262         UIC_CMD_DME_RESET               = 0x14,
 263         UIC_CMD_DME_END_PT_RST          = 0x15,
 264         UIC_CMD_DME_LINK_STARTUP        = 0x16,
 265         UIC_CMD_DME_HIBER_ENTER         = 0x17,
 266         UIC_CMD_DME_HIBER_EXIT          = 0x18,
 267         UIC_CMD_DME_TEST_MODE           = 0x1A,
 268 };
 269
 270 /* UIC Config result code / Generic error code */
 271 enum {
 272         UIC_CMD_RESULT_SUCCESS                  = 0x00,
 273         UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 274         UIC_CMD_RESULT_FAILURE                  = 0x01,
 275         UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 276         UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 277         UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 278         UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 279         UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 280         UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 281         UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 282         UIC_CMD_RESULT_BUSY                     = 0x09,
 283         UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 284 };
 285
 286 #define MASK_UIC_COMMAND_RESULT                 0xFF
 287
 288 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 289 #define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 290
 291 /* Interrupt disable masks */
 292 enum {
 293         /* Interrupt disable mask for UFSHCI v1.0 */
 294         INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 295         INTERRUPT_MASK_RW_VER_10        = 0x30000,
 296
 297         /* Interrupt disable mask for UFSHCI v1.1 */
 298         INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 299
 300         /* Interrupt disable mask for UFSHCI v2.1 */
 301         INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 302 };
 303
 304 /* CCAP - Crypto Capability 100h */
 305 union ufs_crypto_capabilities {
 306         __le32 reg_val;
 307         struct {
 308                 u8 num_crypto_cap;
 309                 u8 config_count;
 310                 u8 reserved;
 311                 u8 config_array_ptr;
 312         };
 313 };
 314
 315 enum ufs_crypto_key_size {
 316         UFS_CRYPTO_KEY_SIZE_INVALID     = 0x0,
 317         UFS_CRYPTO_KEY_SIZE_128         = 0x1,
 318         UFS_CRYPTO_KEY_SIZE_192         = 0x2,
 319         UFS_CRYPTO_KEY_SIZE_256         = 0x3,
 320         UFS_CRYPTO_KEY_SIZE_512         = 0x4,
 321 };
 322
 323 enum ufs_crypto_alg {
 324         UFS_CRYPTO_ALG_AES_XTS                  = 0x0,
 325         UFS_CRYPTO_ALG_BITLOCKER_AES_CBC        = 0x1,
 326         UFS_CRYPTO_ALG_AES_ECB                  = 0x2,
 327         UFS_CRYPTO_ALG_ESSIV_AES_CBC            = 0x3,
 328 };
 329
 330 /* x-CRYPTOCAP - Crypto Capability X */
 331 union ufs_crypto_cap_entry {
 332         __le32 reg_val;
 333         struct {
 334                 u8 algorithm_id;
 335                 u8 sdus_mask; /* Supported data unit size mask */
 336                 u8 key_size;
 337                 u8 reserved;
 338         };
 339 };
 340
 341 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
 342 #define UFS_CRYPTO_KEY_MAX_SIZE 64
 343 /* x-CRYPTOCFG - Crypto Configuration X */
 344 union ufs_crypto_cfg_entry {
 345         __le32 reg_val[32];
 346         struct {
 347                 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
 348                 u8 data_unit_size;
 349                 u8 crypto_cap_idx;
 350                 u8 reserved_1;
 351                 u8 config_enable;
 352                 u8 reserved_multi_host;
 353                 u8 reserved_2;
 354                 u8 vsb[2];
 355                 u8 reserved_3[56];
 356         };
 357 };
 358
 359 /*
 360  * Request Descriptor Definitions
 361  */
 362
 363 /* Transfer request command type */
 364 enum {
 365         UTP_CMD_TYPE_SCSI               = 0x0,
 366         UTP_CMD_TYPE_UFS                = 0x1,
 367         UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 368 };
 369
 370 /* To accommodate UFS2.0 required Command type */
 371 enum {
 372         UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 373 };
 374
 375 enum {
 376         UTP_SCSI_COMMAND                = 0x00000000,
 377         UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 378         UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 379         UTP_REQ_DESC_INT_CMD            = 0x01000000,
 380         UTP_REQ_DESC_CRYPTO_ENABLE_CMD  = 0x00800000,
 381 };
 382
 383 /* UTP Transfer Request Data Direction (DD) */
 384 enum {
 385         UTP_NO_DATA_TRANSFER    = 0x00000000,
 386         UTP_HOST_TO_DEVICE      = 0x02000000,
 387         UTP_DEVICE_TO_HOST      = 0x04000000,
 388 };
 389
 390 /* Overall command status values */
 391 enum utp_ocs {
 392         OCS_SUCCESS                     = 0x0,
 393         OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 394         OCS_INVALID_PRDT_ATTR           = 0x2,
 395         OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 396         OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 397         OCS_PEER_COMM_FAILURE           = 0x5,
 398         OCS_ABORTED                     = 0x6,
 399         OCS_FATAL_ERROR                 = 0x7,
 400         OCS_DEVICE_FATAL_ERROR          = 0x8,
 401         OCS_INVALID_CRYPTO_CONFIG       = 0x9,
 402         OCS_GENERAL_CRYPTO_ERROR        = 0xA,
 403         OCS_INVALID_COMMAND_STATUS      = 0x0F,
 404 };
 405
 406 enum {
 407         MASK_OCS                        = 0x0F,
 408 };
 409
 410 /* The maximum length of the data byte count field in the PRDT is 256KB */
 411 #define PRDT_DATA_BYTE_COUNT_MAX        (256 * 1024)
 412 /* The granularity of the data byte count field in the PRDT is 32-bit */
 413 #define PRDT_DATA_BYTE_COUNT_PAD        4
 414
 415 /**
 416  * struct ufshcd_sg_entry - UFSHCI PRD Entry
 417  * @addr: Physical address; DW-0 and DW-1.
 418  * @reserved: Reserved for future use DW-2
 419  * @size: size of physical segment DW-3
 420  */
 421 struct ufshcd_sg_entry {
 422         __le64    addr;
 423         __le32    reserved;
 424         __le32    size;
 425 };
 426
 427 /**
 428  * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
 429  * @command_upiu: Command UPIU Frame address
 430  * @response_upiu: Response UPIU Frame address
 431  * @prd_table: Physical Region Descriptor
 432  */
 433 struct utp_transfer_cmd_desc {
 434         u8 command_upiu[ALIGNED_UPIU_SIZE];
 435         u8 response_upiu[ALIGNED_UPIU_SIZE];
 436         struct ufshcd_sg_entry    prd_table[SG_ALL];
 437 };
 438
 439 /**
 440  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 441  * @dword0: Descriptor Header DW0
 442  * @dword1: Descriptor Header DW1
 443  * @dword2: Descriptor Header DW2
 444  * @dword3: Descriptor Header DW3
 445  */
 446 struct request_desc_header {
 447         __le32 dword_0;
 448         __le32 dword_1;
 449         __le32 dword_2;
 450         __le32 dword_3;
 451 };
 452
 453 /**
 454  * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
 455  * @header: UTRD header DW-0 to DW-3
 456  * @command_desc_base_addr_lo: UCD base address low DW-4
 457  * @command_desc_base_addr_hi: UCD base address high DW-5
 458  * @response_upiu_length: response UPIU length DW-6
 459  * @response_upiu_offset: response UPIU offset DW-6
 460  * @prd_table_length: Physical region descriptor length DW-7
 461  * @prd_table_offset: Physical region descriptor offset DW-7
 462  */
 463 struct utp_transfer_req_desc {
 464
 465         /* DW 0-3 */
 466         struct request_desc_header header;
 467
 468         /* DW 4-5*/
 469         __le32  command_desc_base_addr_lo;
 470         __le32  command_desc_base_addr_hi;
 471
 472         /* DW 6 */
 473         __le16  response_upiu_length;
 474         __le16  response_upiu_offset;
 475
 476         /* DW 7 */
 477         __le16  prd_table_length;
 478         __le16  prd_table_offset;
 479 };
 480
 481 /*
 482  * UTMRD structure.
 483  */
 484 struct utp_task_req_desc {
 485         /* DW 0-3 */
 486         struct request_desc_header header;
 487
 488         /* DW 4-11 - Task request UPIU structure */
 489         struct {
 490                 struct utp_upiu_header  req_header;
 491                 __be32                  input_param1;
 492                 __be32                  input_param2;
 493                 __be32                  input_param3;
 494                 __be32                  __reserved1[2];
 495         } upiu_req;
 496
 497         /* DW 12-19 - Task Management Response UPIU structure */
 498         struct {
 499                 struct utp_upiu_header  rsp_header;
 500                 __be32                  output_param1;
 501                 __be32                  output_param2;
 502                 __be32                  __reserved2[3];
 503         } upiu_rsp;
 504 };
 505
 506 #endif /* End of Header */