1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
7 #include <linux/types.h>
12 /* Driver command error status */
14 IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
24 IDXD_SCMD_PERCPU_ERR = 0x80090000,
25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
26 IDXD_SCMD_CDEV_ERR = 0x800b0000,
27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
35 #define IDXD_SCMD_SOFTERR_MASK 0x80000000
36 #define IDXD_SCMD_SOFTERR_SHIFT 16
38 /* Descriptor flags */
39 #define IDXD_OP_FLAG_FENCE 0x0001
40 #define IDXD_OP_FLAG_BOF 0x0002
41 #define IDXD_OP_FLAG_CRAV 0x0004
42 #define IDXD_OP_FLAG_RCR 0x0008
43 #define IDXD_OP_FLAG_RCI 0x0010
44 #define IDXD_OP_FLAG_CRSTS 0x0020
45 #define IDXD_OP_FLAG_CR 0x0080
46 #define IDXD_OP_FLAG_CC 0x0100
47 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200
48 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400
49 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800
50 #define IDXD_OP_FLAG_CR_TCS 0x1000
51 #define IDXD_OP_FLAG_STORD 0x2000
52 #define IDXD_OP_FLAG_DRDBK 0x4000
53 #define IDXD_OP_FLAG_DSTS 0x8000
56 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
57 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000
58 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000
59 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000
60 #define IDXD_OP_FLAG_SRC2_STS 0x100000
61 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000
75 DSA_OPCODE_CRCGEN = 0x10,
81 DSA_OPCODE_CFLUSH = 0x20,
88 IAX_OPCODE_DECOMPRESS = 0x42,
91 IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
92 IAX_OPCODE_ZERO_DECOMP_16,
93 IAX_OPCODE_ZERO_COMP_32 = 0x4c,
94 IAX_OPCODE_ZERO_COMP_16,
95 IAX_OPCODE_SCAN = 0x50,
96 IAX_OPCODE_SET_MEMBER,
100 IAX_OPCODE_FIND_UNIQUE,
104 /* Completion record status */
105 enum dsa_completion_status {
108 DSA_COMP_SUCCESS_PRED,
109 DSA_COMP_PAGE_FAULT_NOBOF,
110 DSA_COMP_PAGE_FAULT_IR,
112 DSA_COMP_BATCH_PAGE_FAULT,
113 DSA_COMP_DR_OFFSET_NOINC,
114 DSA_COMP_DR_OFFSET_ERANGE,
116 DSA_COMP_BAD_OPCODE = 0x10,
117 DSA_COMP_INVALID_FLAGS,
118 DSA_COMP_NOZERO_RESERVE,
119 DSA_COMP_XFER_ERANGE,
120 DSA_COMP_DESC_CNT_ERANGE,
122 DSA_COMP_OVERLAP_BUFFERS,
124 DSA_COMP_DESCLIST_ALIGN,
125 DSA_COMP_INT_HANDLE_INVAL,
130 DSA_COMP_TRAFFIC_CLASS_CONF,
131 DSA_COMP_PFAULT_RDBA,
134 DSA_COMP_TRANSLATION_FAIL,
137 enum iax_completion_status {
140 IAX_COMP_PAGE_FAULT_IR = 0x04,
141 IAX_COMP_ANALYTICS_ERROR = 0x0a,
142 IAX_COMP_OUTBUF_OVERFLOW,
143 IAX_COMP_BAD_OPCODE = 0x10,
144 IAX_COMP_INVALID_FLAGS,
145 IAX_COMP_NOZERO_RESERVE,
146 IAX_COMP_INVALID_SIZE,
147 IAX_COMP_OVERLAP_BUFFERS = 0x16,
148 IAX_COMP_INT_HANDLE_INVAL = 0x19,
153 IAX_COMP_TRAFFIC_CLASS_CONF,
154 IAX_COMP_PFAULT_RDBA,
157 IAX_COMP_TRANSLATION_FAIL,
158 IAX_COMP_PRS_TIMEOUT,
160 IAX_COMP_INVALID_COMP_FLAG = 0x30,
161 IAX_COMP_INVALID_FILTER_FLAG,
162 IAX_COMP_INVALID_INPUT_SIZE,
163 IAX_COMP_INVALID_NUM_ELEMS,
164 IAX_COMP_INVALID_SRC1_WIDTH,
165 IAX_COMP_INVALID_INVERT_OUT,
168 #define DSA_COMP_STATUS_MASK 0x7f
169 #define DSA_COMP_STATUS_WRITE 0x80
177 uint64_t completion_addr;
180 uint64_t rdback_addr;
182 uint64_t desc_list_addr;
186 uint64_t rdback_addr2;
188 uint64_t comp_pattern;
197 uint8_t expected_res;
198 /* create delta record */
201 uint32_t max_delta_size;
203 uint8_t expected_res_mask;
205 uint32_t delta_rec_size;
213 /* DIF check or strip */
215 uint8_t src_dif_flags;
217 uint8_t dif_chk_flags;
218 uint8_t dif_chk_res2[5];
219 uint32_t chk_ref_tag_seed;
220 uint16_t chk_app_tag_mask;
221 uint16_t chk_app_tag_seed;
226 uint8_t dest_dif_flag;
227 uint8_t dif_ins_flags;
228 uint8_t dif_ins_res2[13];
229 uint32_t ins_ref_tag_seed;
230 uint16_t ins_app_tag_mask;
231 uint16_t ins_app_tag_seed;
235 uint8_t src_upd_flags;
236 uint8_t upd_dest_flags;
237 uint8_t dif_upd_flags;
238 uint8_t dif_upd_res[5];
239 uint32_t src_ref_tag_seed;
240 uint16_t src_app_tag_mask;
241 uint16_t src_app_tag_seed;
242 uint32_t dest_ref_tag_seed;
243 uint16_t dest_app_tag_mask;
244 uint16_t dest_app_tag_seed;
247 uint8_t op_specific[24];
249 } __attribute__((packed));
257 uint64_t completion_addr;
263 uint16_t compr_flags;
264 uint16_t decompr_flags;
267 uint32_t max_dst_size;
269 uint32_t filter_flags;
271 } __attribute__((packed));
273 struct dsa_raw_desc {
275 } __attribute__((packed));
278 * The status field will be modified by hardware, therefore it should be
279 * volatile and prevent the compiler from optimize the read.
281 struct dsa_completion_record {
282 volatile uint8_t status;
288 uint32_t bytes_completed;
293 uint32_t invalid_flags:24;
297 uint32_t delta_rec_size;
300 /* DIF check & strip */
302 uint32_t dif_chk_ref_tag;
303 uint16_t dif_chk_app_tag_mask;
304 uint16_t dif_chk_app_tag;
309 uint64_t dif_ins_res;
310 uint32_t dif_ins_ref_tag;
311 uint16_t dif_ins_app_tag_mask;
312 uint16_t dif_ins_app_tag;
317 uint32_t dif_upd_src_ref_tag;
318 uint16_t dif_upd_src_app_tag_mask;
319 uint16_t dif_upd_src_app_tag;
320 uint32_t dif_upd_dest_ref_tag;
321 uint16_t dif_upd_dest_app_tag_mask;
322 uint16_t dif_upd_dest_app_tag;
325 uint8_t op_specific[16];
327 } __attribute__((packed));
329 struct dsa_raw_completion_record {
331 } __attribute__((packed));
333 struct iax_completion_record {
334 volatile uint8_t status;
337 uint32_t bytes_completed;
339 uint32_t invalid_flags;
341 uint32_t output_size;
350 } __attribute__((packed));
352 struct iax_raw_completion_record {
354 } __attribute__((packed));