2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000
32 #if defined(__cplusplus)
36 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
37 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
38 #define NOUVEAU_GETPARAM_BUS_TYPE 5
39 #define NOUVEAU_GETPARAM_FB_SIZE 8
40 #define NOUVEAU_GETPARAM_AGP_SIZE 9
41 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
43 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
44 #define NOUVEAU_GETPARAM_PTIMER_TIME 14
45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
49 * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
51 * Query the maximum amount of IBs that can be pushed through a single
52 * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
55 #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
58 * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size
60 * Query the VRAM BAR size.
62 #define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
65 * NOUVEAU_GETPARAM_VRAM_USED
67 * Get remaining VRAM size.
69 #define NOUVEAU_GETPARAM_VRAM_USED 19
72 * NOUVEAU_GETPARAM_HAS_VMA_TILEMODE
74 * Query whether tile mode and PTE kind are accepted with VM allocs or not.
76 #define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
78 struct drm_nouveau_getparam {
83 struct drm_nouveau_channel_alloc {
84 __u32 fb_ctxdma_handle;
85 __u32 tt_ctxdma_handle;
88 __u32 pushbuf_domains;
91 __u32 notifier_handle;
93 /* DRM-enforced subchannel assignments */
101 struct drm_nouveau_channel_free {
105 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
106 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
107 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
108 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
109 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
110 /* The BO will never be shared via import or export. */
111 #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
113 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
114 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
115 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
116 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
117 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
118 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
120 struct drm_nouveau_gem_info {
130 struct drm_nouveau_gem_new {
131 struct drm_nouveau_gem_info info;
136 #define NOUVEAU_GEM_MAX_BUFFERS 1024
137 struct drm_nouveau_gem_pushbuf_bo_presumed {
143 struct drm_nouveau_gem_pushbuf_bo {
149 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
152 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
153 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
154 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
155 #define NOUVEAU_GEM_MAX_RELOCS 1024
156 struct drm_nouveau_gem_pushbuf_reloc {
157 __u32 reloc_bo_index;
158 __u32 reloc_bo_offset;
166 #define NOUVEAU_GEM_MAX_PUSH 512
167 struct drm_nouveau_gem_pushbuf_push {
172 #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
175 struct drm_nouveau_gem_pushbuf {
185 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
186 __u64 vram_available;
187 __u64 gart_available;
190 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
191 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
192 struct drm_nouveau_gem_cpu_prep {
197 struct drm_nouveau_gem_cpu_fini {
202 * struct drm_nouveau_sync - sync object
204 * This structure serves as synchronization mechanism for (potentially)
205 * asynchronous operations such as EXEC or VM_BIND.
207 struct drm_nouveau_sync {
209 * @flags: the flags for a sync object
211 * The first 8 bits are used to determine the type of the sync object.
214 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
215 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
216 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
218 * @handle: the handle of the sync object
224 * The timeline point of the sync object in case the syncobj is of
225 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
227 __u64 timeline_value;
231 * struct drm_nouveau_vm_init - GPU VA space init structure
233 * Used to initialize the GPU's VA space for a user client, telling the kernel
234 * which portion of the VA space is managed by the UMD and kernel respectively.
236 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
237 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
240 struct drm_nouveau_vm_init {
242 * @kernel_managed_addr: start address of the kernel managed VA space
245 __u64 kernel_managed_addr;
247 * @kernel_managed_size: size of the kernel managed VA space region in
250 __u64 kernel_managed_size;
254 * struct drm_nouveau_vm_bind_op - VM_BIND operation
256 * This structure represents a single VM_BIND operation. UMDs should pass
257 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
259 struct drm_nouveau_vm_bind_op {
261 * @op: the operation type
265 * @DRM_NOUVEAU_VM_BIND_OP_MAP:
267 * Map a GEM object to the GPU's VA space. Optionally, the
268 * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
269 * create sparse mappings for the given range.
271 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
273 * @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
275 * Unmap an existing mapping in the GPU's VA space. If the region the mapping
276 * is located in is a sparse region, new sparse mappings are created where the
277 * unmapped (memory backed) mapping was mapped previously. To remove a sparse
278 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
280 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
282 * @flags: the flags for a &drm_nouveau_vm_bind_op
286 * @DRM_NOUVEAU_VM_BIND_SPARSE:
288 * Indicates that an allocated VA space region should be sparse.
290 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
292 * @handle: the handle of the DRM GEM object to map
296 * @pad: 32 bit padding, should be 0
302 * the address the VA space region or (memory backed) mapping should be mapped to
306 * @bo_offset: the offset within the BO backing the mapping
310 * @range: the size of the requested mapping in bytes
316 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
318 struct drm_nouveau_vm_bind {
320 * @op_count: the number of &drm_nouveau_vm_bind_op
324 * @flags: the flags for a &drm_nouveau_vm_bind ioctl
328 * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
330 * Indicates that the given VM_BIND operation should be executed asynchronously
333 * If this flag is not supplied the kernel executes the associated operations
334 * synchronously and doesn't accept any &drm_nouveau_sync objects.
336 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
338 * @wait_count: the number of wait &drm_nouveau_syncs
342 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
346 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
350 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
354 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
360 * struct drm_nouveau_exec_push - EXEC push operation
362 * This structure represents a single EXEC push operation. UMDs should pass an
363 * array of this structure via struct drm_nouveau_exec's &push_ptr field.
365 struct drm_nouveau_exec_push {
367 * @va: the virtual address of the push buffer mapping
371 * @va_len: the length of the push buffer mapping
375 * @flags: the flags for this push buffer mapping
378 #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
382 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
384 struct drm_nouveau_exec {
386 * @channel: the channel to execute the push buffer in
390 * @push_count: the number of &drm_nouveau_exec_push ops
394 * @wait_count: the number of wait &drm_nouveau_syncs
398 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
402 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
406 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
410 * @push_ptr: pointer to &drm_nouveau_exec_push ops
415 #define DRM_NOUVEAU_GETPARAM 0x00
416 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
417 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
418 #define DRM_NOUVEAU_CHANNEL_FREE 0x03
419 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
420 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
421 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
422 #define DRM_NOUVEAU_NVIF 0x07
423 #define DRM_NOUVEAU_SVM_INIT 0x08
424 #define DRM_NOUVEAU_SVM_BIND 0x09
425 #define DRM_NOUVEAU_VM_INIT 0x10
426 #define DRM_NOUVEAU_VM_BIND 0x11
427 #define DRM_NOUVEAU_EXEC 0x12
428 #define DRM_NOUVEAU_GEM_NEW 0x40
429 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
430 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
431 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
432 #define DRM_NOUVEAU_GEM_INFO 0x44
434 struct drm_nouveau_svm_init {
435 __u64 unmanaged_addr;
436 __u64 unmanaged_size;
439 struct drm_nouveau_svm_bind {
450 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
451 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8
452 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
453 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
454 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
455 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
456 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
457 #define NOUVEAU_SVM_BIND_TARGET_BITS 32
458 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
461 * Below is use to validate ioctl argument, userspace can also use it to make
462 * sure that no bit are set beyond known fields for a given kernel version.
464 #define NOUVEAU_SVM_BIND_VALID_BITS 48
465 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
469 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
470 * result: number of page successfuly migrate to the target memory.
472 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
475 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
477 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
480 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
481 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
482 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
484 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
485 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
487 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
488 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
489 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
490 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
491 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
493 #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
494 #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
495 #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
496 #if defined(__cplusplus)
500 #endif /* __NOUVEAU_DRM_H__ */