2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000
32 #if defined(__cplusplus)
36 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
37 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
38 #define NOUVEAU_GETPARAM_BUS_TYPE 5
39 #define NOUVEAU_GETPARAM_FB_SIZE 8
40 #define NOUVEAU_GETPARAM_AGP_SIZE 9
41 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
43 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
44 #define NOUVEAU_GETPARAM_PTIMER_TIME 14
45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
49 * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
51 * Query the maximum amount of IBs that can be pushed through a single
52 * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
55 #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
57 struct drm_nouveau_getparam {
62 struct drm_nouveau_channel_alloc {
63 __u32 fb_ctxdma_handle;
64 __u32 tt_ctxdma_handle;
67 __u32 pushbuf_domains;
70 __u32 notifier_handle;
72 /* DRM-enforced subchannel assignments */
80 struct drm_nouveau_channel_free {
84 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
85 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
86 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
87 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
88 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
89 /* The BO will never be shared via import or export. */
90 #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
92 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
93 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
94 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
95 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
96 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
97 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
99 struct drm_nouveau_gem_info {
109 struct drm_nouveau_gem_new {
110 struct drm_nouveau_gem_info info;
115 #define NOUVEAU_GEM_MAX_BUFFERS 1024
116 struct drm_nouveau_gem_pushbuf_bo_presumed {
122 struct drm_nouveau_gem_pushbuf_bo {
128 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
131 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
132 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
133 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
134 #define NOUVEAU_GEM_MAX_RELOCS 1024
135 struct drm_nouveau_gem_pushbuf_reloc {
136 __u32 reloc_bo_index;
137 __u32 reloc_bo_offset;
145 #define NOUVEAU_GEM_MAX_PUSH 512
146 struct drm_nouveau_gem_pushbuf_push {
151 #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
154 struct drm_nouveau_gem_pushbuf {
164 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
165 __u64 vram_available;
166 __u64 gart_available;
169 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
170 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
171 struct drm_nouveau_gem_cpu_prep {
176 struct drm_nouveau_gem_cpu_fini {
181 * struct drm_nouveau_sync - sync object
183 * This structure serves as synchronization mechanism for (potentially)
184 * asynchronous operations such as EXEC or VM_BIND.
186 struct drm_nouveau_sync {
188 * @flags: the flags for a sync object
190 * The first 8 bits are used to determine the type of the sync object.
193 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
194 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
195 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
197 * @handle: the handle of the sync object
203 * The timeline point of the sync object in case the syncobj is of
204 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
206 __u64 timeline_value;
210 * struct drm_nouveau_vm_init - GPU VA space init structure
212 * Used to initialize the GPU's VA space for a user client, telling the kernel
213 * which portion of the VA space is managed by the UMD and kernel respectively.
215 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
216 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
219 struct drm_nouveau_vm_init {
221 * @kernel_managed_addr: start address of the kernel managed VA space
224 __u64 kernel_managed_addr;
226 * @kernel_managed_size: size of the kernel managed VA space region in
229 __u64 kernel_managed_size;
233 * struct drm_nouveau_vm_bind_op - VM_BIND operation
235 * This structure represents a single VM_BIND operation. UMDs should pass
236 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
238 struct drm_nouveau_vm_bind_op {
240 * @op: the operation type
244 * @DRM_NOUVEAU_VM_BIND_OP_MAP:
246 * Map a GEM object to the GPU's VA space. Optionally, the
247 * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
248 * create sparse mappings for the given range.
250 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
252 * @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
254 * Unmap an existing mapping in the GPU's VA space. If the region the mapping
255 * is located in is a sparse region, new sparse mappings are created where the
256 * unmapped (memory backed) mapping was mapped previously. To remove a sparse
257 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
259 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
261 * @flags: the flags for a &drm_nouveau_vm_bind_op
265 * @DRM_NOUVEAU_VM_BIND_SPARSE:
267 * Indicates that an allocated VA space region should be sparse.
269 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
271 * @handle: the handle of the DRM GEM object to map
275 * @pad: 32 bit padding, should be 0
281 * the address the VA space region or (memory backed) mapping should be mapped to
285 * @bo_offset: the offset within the BO backing the mapping
289 * @range: the size of the requested mapping in bytes
295 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
297 struct drm_nouveau_vm_bind {
299 * @op_count: the number of &drm_nouveau_vm_bind_op
303 * @flags: the flags for a &drm_nouveau_vm_bind ioctl
307 * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
309 * Indicates that the given VM_BIND operation should be executed asynchronously
312 * If this flag is not supplied the kernel executes the associated operations
313 * synchronously and doesn't accept any &drm_nouveau_sync objects.
315 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
317 * @wait_count: the number of wait &drm_nouveau_syncs
321 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
325 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
329 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
333 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
339 * struct drm_nouveau_exec_push - EXEC push operation
341 * This structure represents a single EXEC push operation. UMDs should pass an
342 * array of this structure via struct drm_nouveau_exec's &push_ptr field.
344 struct drm_nouveau_exec_push {
346 * @va: the virtual address of the push buffer mapping
350 * @va_len: the length of the push buffer mapping
354 * @flags: the flags for this push buffer mapping
357 #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
361 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
363 struct drm_nouveau_exec {
365 * @channel: the channel to execute the push buffer in
369 * @push_count: the number of &drm_nouveau_exec_push ops
373 * @wait_count: the number of wait &drm_nouveau_syncs
377 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
381 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
385 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
389 * @push_ptr: pointer to &drm_nouveau_exec_push ops
394 #define DRM_NOUVEAU_GETPARAM 0x00
395 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
396 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
397 #define DRM_NOUVEAU_CHANNEL_FREE 0x03
398 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
399 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
400 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
401 #define DRM_NOUVEAU_NVIF 0x07
402 #define DRM_NOUVEAU_SVM_INIT 0x08
403 #define DRM_NOUVEAU_SVM_BIND 0x09
404 #define DRM_NOUVEAU_VM_INIT 0x10
405 #define DRM_NOUVEAU_VM_BIND 0x11
406 #define DRM_NOUVEAU_EXEC 0x12
407 #define DRM_NOUVEAU_GEM_NEW 0x40
408 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
409 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
410 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
411 #define DRM_NOUVEAU_GEM_INFO 0x44
413 struct drm_nouveau_svm_init {
414 __u64 unmanaged_addr;
415 __u64 unmanaged_size;
418 struct drm_nouveau_svm_bind {
429 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
430 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8
431 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
432 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
433 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
434 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
435 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
436 #define NOUVEAU_SVM_BIND_TARGET_BITS 32
437 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
440 * Below is use to validate ioctl argument, userspace can also use it to make
441 * sure that no bit are set beyond known fields for a given kernel version.
443 #define NOUVEAU_SVM_BIND_VALID_BITS 48
444 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
448 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
449 * result: number of page successfuly migrate to the target memory.
451 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
454 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
456 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
459 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
460 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
461 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
463 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
464 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
466 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
467 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
468 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
469 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
470 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
472 #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
473 #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
474 #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
475 #if defined(__cplusplus)
479 #endif /* __NOUVEAU_DRM_H__ */