2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #if defined(__cplusplus)
34 /* Please note that modifications to all structs defined here are
35 * subject to backwards-compatibility constraints:
36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
37 * user/kernel compatibility
38 * 2) Keep fields aligned to their size
39 * 3) Because of how drm_ioctl() works, we can add new fields at
40 * the end of an ioctl if some care is taken: drm_ioctl() will
41 * zero out the new fields at the tail of the ioctl, so a zero
42 * value should have a backwards compatible meaning. And for
43 * output params, userspace won't see the newly added output
44 * fields.. so that has to be somehow ok.
47 #define MSM_PIPE_NONE 0x00
48 #define MSM_PIPE_2D0 0x01
49 #define MSM_PIPE_2D1 0x02
50 #define MSM_PIPE_3D0 0x10
52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
53 * the upper 16 bits (which could be extended further, if needed, maybe
54 * we extend/overload the pipe-id some day to deal with multiple rings,
55 * but even then I don't think we need the full lower 16 bits).
57 #define MSM_PIPE_ID_MASK 0xffff
58 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
59 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
61 /* timeouts are specified in clock-monotonic absolute times (to simplify
62 * restarting interrupted ioctls). The following struct is logically the
63 * same as 'struct timespec' but 32/64b ABI safe.
65 struct drm_msm_timespec {
66 __s64 tv_sec; /* seconds */
67 __s64 tv_nsec; /* nanoseconds */
70 #define MSM_PARAM_GPU_ID 0x01
71 #define MSM_PARAM_GMEM_SIZE 0x02
72 #define MSM_PARAM_CHIP_ID 0x03
73 #define MSM_PARAM_MAX_FREQ 0x04
74 #define MSM_PARAM_TIMESTAMP 0x05
75 #define MSM_PARAM_GMEM_BASE 0x06
76 #define MSM_PARAM_NR_RINGS 0x07
77 #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
78 #define MSM_PARAM_FAULTS 0x09
79 #define MSM_PARAM_SUSPENDS 0x0a
81 struct drm_msm_param {
82 __u32 pipe; /* in, MSM_PIPE_x */
83 __u32 param; /* in, MSM_PARAM_x */
84 __u64 value; /* out (get_param) or in (set_param) */
91 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
92 #define MSM_BO_GPU_READONLY 0x00000002
93 #define MSM_BO_CACHE_MASK 0x000f0000
95 #define MSM_BO_CACHED 0x00010000
96 #define MSM_BO_WC 0x00020000
97 #define MSM_BO_UNCACHED 0x00040000
99 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
100 MSM_BO_GPU_READONLY | \
105 struct drm_msm_gem_new {
107 __u32 flags; /* in, mask of MSM_BO_x */
108 __u32 handle; /* out */
111 /* Get or set GEM buffer info. The requested value can be passed
112 * directly in 'value', or for data larger than 64b 'value' is a
113 * pointer to userspace buffer, with 'len' specifying the number of
114 * bytes copied into that buffer. For info returned by pointer,
115 * calling the GEM_INFO ioctl with null 'value' will return the
116 * required buffer size in 'len'
118 #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
119 #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
120 #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
121 #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
123 struct drm_msm_gem_info {
124 __u32 handle; /* in */
125 __u32 info; /* in - one of MSM_INFO_* */
126 __u64 value; /* in or out */
127 __u32 len; /* in or out */
131 #define MSM_PREP_READ 0x01
132 #define MSM_PREP_WRITE 0x02
133 #define MSM_PREP_NOSYNC 0x04
135 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
137 struct drm_msm_gem_cpu_prep {
138 __u32 handle; /* in */
139 __u32 op; /* in, mask of MSM_PREP_x */
140 struct drm_msm_timespec timeout; /* in */
143 struct drm_msm_gem_cpu_fini {
144 __u32 handle; /* in */
148 * Cmdstream Submission:
151 /* The value written into the cmdstream is logically:
153 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
155 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
156 * with this by emit'ing two reloc entries with appropriate shift
157 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
159 * NOTE that reloc's must be sorted by order of increasing submit_offset,
162 struct drm_msm_gem_submit_reloc {
163 __u32 submit_offset; /* in, offset from submit_bo */
164 __u32 or; /* in, value OR'd with result */
165 __s32 shift; /* in, amount of left shift (can be negative) */
166 __u32 reloc_idx; /* in, index of reloc_bo buffer */
167 __u64 reloc_offset; /* in, offset from start of reloc_bo */
171 * BUF - this cmd buffer is executed normally.
172 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
173 * processed normally, but the kernel does not setup an IB to
174 * this buffer in the first-level ringbuffer
175 * CTX_RESTORE_BUF - only executed if there has been a GPU context
176 * switch since the last SUBMIT ioctl
178 #define MSM_SUBMIT_CMD_BUF 0x0001
179 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
180 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
181 struct drm_msm_gem_submit_cmd {
182 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
183 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
184 __u32 submit_offset; /* in, offset into submit_bo */
185 __u32 size; /* in, cmdstream size */
187 __u32 nr_relocs; /* in, number of submit_reloc's */
188 __u64 relocs; /* in, ptr to array of submit_reloc's */
191 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
192 * cmdstream buffer(s) themselves or reloc entries) has one (and only
193 * one) entry in the submit->bos[] table.
195 * As a optimization, the current buffer (gpu virtual address) can be
196 * passed back through the 'presumed' field. If on a subsequent reloc,
197 * userspace passes back a 'presumed' address that is still valid,
198 * then patching the cmdstream for this entry is skipped. This can
199 * avoid kernel needing to map/access the cmdstream bo in the common
202 #define MSM_SUBMIT_BO_READ 0x0001
203 #define MSM_SUBMIT_BO_WRITE 0x0002
204 #define MSM_SUBMIT_BO_DUMP 0x0004
206 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
207 MSM_SUBMIT_BO_WRITE | \
210 struct drm_msm_gem_submit_bo {
211 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
212 __u32 handle; /* in, GEM handle */
213 __u64 presumed; /* in/out, presumed buffer address */
216 /* Valid submit ioctl flags: */
217 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
218 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
219 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
220 #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
221 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
222 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
223 #define MSM_SUBMIT_FLAGS ( \
224 MSM_SUBMIT_NO_IMPLICIT | \
225 MSM_SUBMIT_FENCE_FD_IN | \
226 MSM_SUBMIT_FENCE_FD_OUT | \
228 MSM_SUBMIT_SYNCOBJ_IN | \
229 MSM_SUBMIT_SYNCOBJ_OUT | \
232 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
233 #define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
234 MSM_SUBMIT_SYNCOBJ_RESET | \
237 struct drm_msm_gem_submit_syncobj {
238 __u32 handle; /* in, syncobj handle. */
239 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
240 __u64 point; /* in, timepoint for timeline syncobjs. */
243 /* Each cmdstream submit consists of a table of buffers involved, and
244 * one or more cmdstream buffers. This allows for conditional execution
245 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
247 struct drm_msm_gem_submit {
248 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
249 __u32 fence; /* out */
250 __u32 nr_bos; /* in, number of submit_bo's */
251 __u32 nr_cmds; /* in, number of submit_cmd's */
252 __u64 bos; /* in, ptr to array of submit_bo's */
253 __u64 cmds; /* in, ptr to array of submit_cmd's */
254 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
255 __u32 queueid; /* in, submitqueue id */
256 __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
257 __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
258 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
259 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
260 __u32 syncobj_stride; /* in, stride of syncobj arrays. */
261 __u32 pad; /*in, reserved for future use, always 0. */
265 /* The normal way to synchronize with the GPU is just to CPU_PREP on
266 * a buffer if you need to access it from the CPU (other cmdstream
267 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
268 * handle the required synchronization under the hood). This ioctl
269 * mainly just exists as a way to implement the gallium pipe_fence
270 * APIs without requiring a dummy bo to synchronize on.
272 struct drm_msm_wait_fence {
273 __u32 fence; /* in */
275 struct drm_msm_timespec timeout; /* in */
276 __u32 queueid; /* in, submitqueue id */
279 /* madvise provides a way to tell the kernel in case a buffers contents
280 * can be discarded under memory pressure, which is useful for userspace
281 * bo cache where we want to optimistically hold on to buffer allocate
282 * and potential mmap, but allow the pages to be discarded under memory
285 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
286 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
287 * In the WILLNEED case, 'retained' indicates to userspace whether the
288 * backing pages still exist.
290 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
291 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */
292 #define __MSM_MADV_PURGED 2 /* internal state */
294 struct drm_msm_gem_madvise {
295 __u32 handle; /* in, GEM handle */
296 __u32 madv; /* in, MSM_MADV_x */
297 __u32 retained; /* out, whether backing store still exists */
301 * Draw queues allow the user to set specific submission parameter. Command
302 * submissions specify a specific submitqueue to use. ID 0 is reserved for
303 * backwards compatibility as a "default" submitqueue
306 #define MSM_SUBMITQUEUE_FLAGS (0)
308 struct drm_msm_submitqueue {
309 __u32 flags; /* in, MSM_SUBMITQUEUE_x */
310 __u32 prio; /* in, Priority level */
311 __u32 id; /* out, identifier */
314 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0
316 struct drm_msm_submitqueue_query {
324 #define DRM_MSM_GET_PARAM 0x00
326 #define DRM_MSM_SET_PARAM 0x01
328 #define DRM_MSM_GEM_NEW 0x02
329 #define DRM_MSM_GEM_INFO 0x03
330 #define DRM_MSM_GEM_CPU_PREP 0x04
331 #define DRM_MSM_GEM_CPU_FINI 0x05
332 #define DRM_MSM_GEM_SUBMIT 0x06
333 #define DRM_MSM_WAIT_FENCE 0x07
334 #define DRM_MSM_GEM_MADVISE 0x08
336 #define DRM_MSM_GEM_SVM_NEW 0x09
338 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A
339 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
340 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
342 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
343 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
344 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
345 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
346 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
347 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
348 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
349 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
350 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
351 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
352 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
354 #if defined(__cplusplus)
358 #endif /* __MSM_DRM_H__ */