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29 #if defined(__cplusplus)
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
74 * There are two kinds of modifier users:
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
85 * Vendors should document their modifier usage in as much detail as
86 * possible, to ensure maximum compatibility across devices, drivers and
89 * The authoritative list of format modifier codes is found in
90 * `include/uapi/drm/drm_fourcc.h`
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
94 ((__u32)(c) << 16) | ((__u32)(d) << 24))
96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
98 /* Reserve 0 for the invalid format specifier */
99 #define DRM_FORMAT_INVALID 0
102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
108 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
111 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
112 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
115 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
116 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
119 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
120 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
123 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
124 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
125 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
126 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
128 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
129 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
130 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
131 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
133 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
134 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
135 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
136 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
138 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
139 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
140 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
141 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
143 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
144 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
147 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
148 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
151 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
152 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
153 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
154 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
156 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
157 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
158 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
159 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
161 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
162 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
163 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
164 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
166 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
167 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
168 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
169 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
172 * Floating point 64bpp RGB
173 * IEEE 754-2008 binary16 half-precision float
174 * [15:0] sign:exponent:mantissa 1:5:10
176 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
177 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
179 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
180 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
183 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
184 * of unused padding per component:
186 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
189 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
190 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
191 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
192 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
194 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
195 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
196 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
197 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
200 * packed Y2xx indicate for each component, xx valid data occupy msb
201 * 16-xx padding occupy lsb
203 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
204 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
205 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
208 * packed Y4xx indicate for each component, xx valid data occupy msb
209 * 16-xx padding occupy lsb except Y410
211 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
212 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
213 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
215 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
216 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
217 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
220 * packed YCbCr420 2x2 tiled formats
221 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
223 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
224 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
225 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
226 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
228 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
229 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
230 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
231 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
235 * In these formats, the component ordering is specified (Y, followed by U
236 * then V), but the exact Linear layout is undefined.
237 * These formats can only be used with a non-Linear modifier.
239 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
240 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
244 * index 0 = RGB plane, same format as the corresponding non _A8 format has
245 * index 1 = A plane, [7:0] A
247 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
248 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
249 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
250 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
251 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
252 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
253 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
254 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
258 * index 0 = Y plane, [7:0] Y
259 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
261 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
263 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
264 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
265 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
266 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
267 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
268 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
271 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
272 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
274 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
277 * 2 plane YCbCr MSB aligned
278 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
279 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
281 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
284 * 2 plane YCbCr MSB aligned
285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
288 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
291 * 2 plane YCbCr MSB aligned
292 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
295 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
298 * 2 plane YCbCr MSB aligned
299 * index 0 = Y plane, [15:0] Y little endian
300 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
302 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
304 /* 3 plane non-subsampled (444) YCbCr
305 * 16 bits per component, but only 10 bits are used and 6 bits are padded
306 * index 0: Y plane, [15:0] Y:x [10:6] little endian
307 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
308 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
310 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
312 /* 3 plane non-subsampled (444) YCrCb
313 * 16 bits per component, but only 10 bits are used and 6 bits are padded
314 * index 0: Y plane, [15:0] Y:x [10:6] little endian
315 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
316 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
318 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
322 * index 0: Y plane, [7:0] Y
323 * index 1: Cb plane, [7:0] Cb
324 * index 2: Cr plane, [7:0] Cr
326 * index 1: Cr plane, [7:0] Cr
327 * index 2: Cb plane, [7:0] Cb
329 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
330 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
331 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
332 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
333 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
334 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
335 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
336 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
337 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
338 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
344 * Format modifiers describe, typically, a re-ordering or modification
345 * of the data in a plane of an FB. This can be used to express tiled/
346 * swizzled formats, or compression, or a combination of the two.
348 * The upper 8 bits of the format modifier are a vendor-id as assigned
349 * below. The lower 56 bits are assigned as vendor sees fit.
353 #define DRM_FORMAT_MOD_VENDOR_NONE 0
354 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
355 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
356 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
357 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
358 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
359 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
360 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
361 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
362 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
363 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
365 /* add more to the end as needed */
367 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
369 #define fourcc_mod_code(vendor, val) \
370 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
373 * Format Modifier tokens:
375 * When adding a new token please document the layout with a code comment,
376 * similar to the fourcc codes above. drm_fourcc.h is considered the
377 * authoritative source for all of these.
379 * Generic modifier names:
381 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
382 * for layouts which are common across multiple vendors. To preserve
383 * compatibility, in cases where a vendor-specific definition already exists and
384 * a generic name for it is desired, the common name is a purely symbolic alias
385 * and must use the same numerical value as the original definition.
387 * Note that generic names should only be used for modifiers which describe
388 * generic layouts (such as pixel re-ordering), which may have
389 * independently-developed support across multiple vendors.
391 * In future cases where a generic layout is identified before merging with a
392 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
393 * 'NONE' could be considered. This should only be for obvious, exceptional
394 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
395 * apply to a single vendor.
397 * Generic names should not be used for cases where multiple hardware vendors
398 * have implementations of the same standardised compression scheme (such as
399 * AFBC). In those cases, all implementations should use the same format
400 * modifier(s), reflecting the vendor of the standard.
403 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
408 * This modifier can be used as a sentinel to terminate the format modifiers
409 * list, or to initialize a variable with an invalid modifier. It might also be
410 * used to report an error back to userspace for certain APIs.
412 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
417 * Just plain linear layout. Note that this is different from no specifying any
418 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
419 * which tells the driver to also take driver-internal information into account
420 * and so might actually result in a tiled framebuffer.
422 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
425 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
427 * The "none" format modifier doesn't actually mean that the modifier is
428 * implicit, instead it means that the layout is linear. Whether modifiers are
429 * used is out-of-band information carried in an API-specific way (e.g. in a
430 * flag for drm_mode_fb_cmd2).
432 #define DRM_FORMAT_MOD_NONE 0
434 /* Intel framebuffer modifiers */
437 * Intel X-tiling layout
439 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
440 * in row-major layout. Within the tile bytes are laid out row-major, with
441 * a platform-dependent stride. On top of that the memory can apply
442 * platform-depending swizzling of some higher address bits into bit6.
444 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
445 * On earlier platforms the is highly platforms specific and not useful for
446 * cross-driver sharing. It exists since on a given platform it does uniquely
447 * identify the layout in a simple way for i915-specific userspace, which
448 * facilitated conversion of userspace to modifiers. Additionally the exact
449 * format on some really old platforms is not known.
451 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
454 * Intel Y-tiling layout
456 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
457 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
458 * chunks column-major, with a platform-dependent height. On top of that the
459 * memory can apply platform-depending swizzling of some higher address bits
462 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
463 * On earlier platforms the is highly platforms specific and not useful for
464 * cross-driver sharing. It exists since on a given platform it does uniquely
465 * identify the layout in a simple way for i915-specific userspace, which
466 * facilitated conversion of userspace to modifiers. Additionally the exact
467 * format on some really old platforms is not known.
469 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
472 * Intel Yf-tiling layout
474 * This is a tiled layout using 4Kb tiles in row-major layout.
475 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
476 * are arranged in four groups (two wide, two high) with column-major layout.
477 * Each group therefore consits out of four 256 byte units, which are also laid
478 * out as 2x2 column-major.
479 * 256 byte units are made out of four 64 byte blocks of pixels, producing
480 * either a square block or a 2:1 unit.
481 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
482 * in pixel depends on the pixel depth.
484 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
487 * Intel color control surface (CCS) for render compression
489 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
490 * The main surface will be plane index 0 and must be Y/Yf-tiled,
491 * the CCS will be plane index 1.
493 * Each CCS tile matches a 1024x512 pixel area of the main surface.
494 * To match certain aspects of the 3D hardware the CCS is
495 * considered to be made up of normal 128Bx32 Y tiles, Thus
496 * the CCS pitch must be specified in multiples of 128 bytes.
498 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
499 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
500 * But that fact is not relevant unless the memory is accessed
503 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
504 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
507 * Intel color control surfaces (CCS) for Gen-12 render compression.
509 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
510 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
511 * main surface. In other words, 4 bits in CCS map to a main surface cache
512 * line pair. The main surface pitch is required to be a multiple of four
515 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
518 * Intel color control surfaces (CCS) for Gen-12 media compression
520 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
521 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
522 * main surface. In other words, 4 bits in CCS map to a main surface cache
523 * line pair. The main surface pitch is required to be a multiple of four
524 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
525 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
526 * planes 2 and 3 for the respective CCS.
528 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
531 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
534 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
535 * and at index 1. The clear color is stored at index 2, and the pitch should
536 * be ignored. The clear color structure is 256 bits. The first 128 bits
537 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
538 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
539 * the converted clear color of size 64 bits. The first 32 bits store the Lower
540 * Converted Clear Color value and the next 32 bits store the Higher Converted
541 * Clear Color value when applicable. The Converted Clear Color values are
542 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
543 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
544 * corresponds to an area of 4x1 tiles in the main surface. The main surface
545 * pitch is required to be a multiple of 4 tile widths.
547 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
550 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
552 * Macroblocks are laid in a Z-shape, and each pixel data is following the
553 * standard NV12 style.
554 * As for NV12, an image is the result of two frame buffers: one for Y,
555 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
556 * Alignment requirements are (for each buffer):
557 * - multiple of 128 pixels for the width
558 * - multiple of 32 pixels for the height
560 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
562 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
565 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
567 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
568 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
569 * they correspond to their 16x16 luma block.
571 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
574 * Qualcomm Compressed Format
576 * Refers to a compressed variant of the base format that is compressed.
577 * Implementation may be platform and base-format specific.
579 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
580 * Pixel data pitch/stride is aligned with macrotile width.
581 * Pixel data height is aligned with macrotile height.
582 * Entire pixel data buffer is aligned with 4k(bytes).
584 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
586 /* Vivante framebuffer modifiers */
589 * Vivante 4x4 tiling layout
591 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
594 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
597 * Vivante 64x64 super-tiling layout
599 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
600 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
603 * For more information: see
604 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
606 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
609 * Vivante 4x4 tiling layout for dual-pipe
611 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
612 * different base address. Offsets from the base addresses are therefore halved
613 * compared to the non-split tiled layout.
615 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
618 * Vivante 64x64 super-tiling layout for dual-pipe
620 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
621 * starts at a different base address. Offsets from the base addresses are
622 * therefore halved compared to the non-split super-tiled layout.
624 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
626 /* NVIDIA frame buffer modifiers */
629 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
631 * Pixels are arranged in simple tiles of 16 x 16 bytes.
633 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
636 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
637 * and Tegra GPUs starting with Tegra K1.
639 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
640 * based on the architecture generation. GOBs themselves are then arranged in
641 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
642 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
643 * a block depth or height of "4").
645 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
649 * Bits Param Description
650 * ---- ----- -----------------------------------------------------------------
652 * 3:0 h log2(height) of each block, in GOBs. Placed here for
653 * compatibility with the existing
654 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
656 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
657 * compatibility with the existing
658 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
660 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
661 * size). Must be zero.
663 * Note there is no log2(width) parameter. Some portions of the
664 * hardware support a block width of two gobs, but it is impractical
665 * to use due to lack of support elsewhere, and has no known
668 * 11:9 - Reserved (To support 2D-array textures with variable array stride
669 * in blocks, specified via log2(tile width in blocks)). Must be
672 * 19:12 k Page Kind. This value directly maps to a field in the page
673 * tables of all GPUs >= NV50. It affects the exact layout of bits
674 * in memory and can be derived from the tuple
676 * (format, GPU model, compression type, samples per pixel)
678 * Where compression type is defined below. If GPU model were
679 * implied by the format modifier, format, or memory buffer, page
680 * kind would not need to be included in the modifier itself, but
681 * since the modifier should define the layout of the associated
682 * memory buffer independent from any device or other context, it
683 * must be included here.
685 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
686 * starting with Fermi GPUs. Additionally, the mapping between page
687 * kind and bit layout has changed at various points.
689 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
690 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
691 * 2 = Gob Height 8, Turing+ Page Kind mapping
692 * 3 = Reserved for future use.
694 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
695 * bit remapping step that occurs at an even lower level than the
696 * page kind and block linear swizzles. This causes the layout of
697 * surfaces mapped in those SOC's GPUs to be incompatible with the
698 * equivalent mapping on other GPUs in the same system.
700 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
701 * 1 = Desktop GPU and Tegra Xavier+ Layout
703 * 25:23 c Lossless Framebuffer Compression type.
706 * 1 = ROP/3D, layout 1, exact compression format implied by Page
708 * 2 = ROP/3D, layout 2, exact compression format implied by Page
712 * 5 = Reserved for future use
713 * 6 = Reserved for future use
714 * 7 = Reserved for future use
716 * 55:25 - Reserved for future use. Must be zero.
718 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
719 fourcc_mod_code(NVIDIA, (0x10 | \
721 (((k) & 0xff) << 12) | \
722 (((g) & 0x3) << 20) | \
723 (((s) & 0x1) << 22) | \
724 (((c) & 0x7) << 23)))
726 /* To grandfather in prior block linear format modifiers to the above layout,
727 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
728 * with block-linear layouts, is remapped within drivers to the value 0xfe,
729 * which corresponds to the "generic" kind used for simple single-sample
730 * uncompressed color formats on Fermi - Volta GPUs.
733 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
735 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
738 return modifier | (0xfe << 12);
742 * 16Bx2 Block Linear layout, used by Tegra K1 and later
744 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
745 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
747 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
749 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
757 * 5 == THIRTYTWO_GOBS
759 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
762 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
765 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
766 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
767 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
768 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
769 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
770 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
771 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
772 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
773 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
774 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
775 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
776 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
779 * Some Broadcom modifiers take parameters, for example the number of
780 * vertical lines in the image. Reserve the lower 32 bits for modifier
781 * type, and the next 24 bits for parameters. Top 8 bits are the
784 #define __fourcc_mod_broadcom_param_shift 8
785 #define __fourcc_mod_broadcom_param_bits 48
786 #define fourcc_mod_broadcom_code(val, params) \
787 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
788 #define fourcc_mod_broadcom_param(m) \
789 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
790 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
791 #define fourcc_mod_broadcom_mod(m) \
792 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
793 __fourcc_mod_broadcom_param_shift))
796 * Broadcom VC4 "T" format
798 * This is the primary layout that the V3D GPU can texture from (it
799 * can't do linear). The T format has:
801 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
802 * pixels at 32 bit depth.
804 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
807 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
808 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
809 * they're (TR, BR, BL, TL), where bottom left is start of memory.
811 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
812 * tiles) or right-to-left (odd rows of 4k tiles).
814 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
817 * Broadcom SAND format
819 * This is the native format that the H.264 codec block uses. For VC4
820 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
822 * The image can be considered to be split into columns, and the
823 * columns are placed consecutively into memory. The width of those
824 * columns can be either 32, 64, 128, or 256 pixels, but in practice
825 * only 128 pixel columns are used.
827 * The pitch between the start of each column is set to optimally
828 * switch between SDRAM banks. This is passed as the number of lines
829 * of column width in the modifier (we can't use the stride value due
830 * to various core checks that look at it , so you should set the
831 * stride to width*cpp).
833 * Note that the column height for this format modifier is the same
834 * for all of the planes, assuming that each column contains both Y
835 * and UV. Some SAND-using hardware stores UV in a separate tiled
836 * image from Y to reduce the column height, which is not supported
837 * with these modifiers.
840 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
841 fourcc_mod_broadcom_code(2, v)
842 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
843 fourcc_mod_broadcom_code(3, v)
844 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
845 fourcc_mod_broadcom_code(4, v)
846 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
847 fourcc_mod_broadcom_code(5, v)
849 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
850 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
851 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
852 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
853 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
854 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
855 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
856 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
858 /* Broadcom UIF format
860 * This is the common format for the current Broadcom multimedia
861 * blocks, including V3D 3.x and newer, newer video codecs, and
864 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
865 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
866 * stored in columns, with padding between the columns to ensure that
867 * moving from one column to the next doesn't hit the same SDRAM page
870 * To calculate the padding, it is assumed that each hardware block
871 * and the software driving it knows the platform's SDRAM page size,
872 * number of banks, and XOR address, and that it's identical between
873 * all blocks using the format. This tiling modifier will use XOR as
874 * necessary to reduce the padding. If a hardware block can't do XOR,
875 * the assumption is that a no-XOR tiling modifier will be created.
877 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
880 * Arm Framebuffer Compression (AFBC) modifiers
882 * AFBC is a proprietary lossless image compression protocol and format.
883 * It provides fine-grained random access and minimizes the amount of data
884 * transferred between IP blocks.
886 * AFBC has several features which may be supported and/or used, which are
887 * represented using bits in the modifier. Not all combinations are valid,
888 * and different devices or use-cases may support different combinations.
890 * Further information on the use of AFBC modifiers can be found in
891 * Documentation/gpu/afbc.rst
895 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
896 * modifiers) denote the category for modifiers. Currently we have only two
897 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
898 * different categories.
900 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
901 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
903 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
904 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
906 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
907 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
910 * AFBC superblock size
912 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
913 * size (in pixels) must be aligned to a multiple of the superblock size.
914 * Four lowest significant bits(LSBs) are reserved for block size.
916 * Where one superblock size is specified, it applies to all planes of the
917 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
918 * the first applies to the Luma plane and the second applies to the Chroma
919 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
920 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
922 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
923 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
924 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
925 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
926 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
929 * AFBC lossless colorspace transform
931 * Indicates that the buffer makes use of the AFBC lossless colorspace
934 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
939 * Indicates that the payload of each superblock is split. The second
940 * half of the payload is positioned at a predefined offset from the start
941 * of the superblock payload.
943 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
948 * This flag indicates that the payload of each superblock must be stored at a
949 * predefined position relative to the other superblocks in the same AFBC
950 * buffer. This order is the same order used by the header buffer. In this mode
951 * each superblock is given the same amount of space as an uncompressed
952 * superblock of the particular format would require, rounding up to the next
953 * multiple of 128 bytes in size.
955 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
958 * AFBC copy-block restrict
960 * Buffers with this flag must obey the copy-block restriction. The restriction
961 * is such that there are no copy-blocks referring across the border of 8x8
962 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
964 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
969 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
970 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
971 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
972 * larger bpp formats. The order between the tiles is scan line.
973 * When the tiled layout is used, the buffer size (in pixels) must be aligned
976 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
979 * AFBC solid color blocks
981 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
982 * can be reduced if a whole superblock is a single color.
984 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
989 * Indicates that the buffer is allocated in a layout safe for front-buffer
992 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
995 * AFBC buffer content hints
997 * Indicates that the buffer includes per-superblock content hints.
999 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1001 /* AFBC uncompressed storage mode
1003 * Indicates that the buffer is using AFBC uncompressed storage mode.
1004 * In this mode all superblock payloads in the buffer use the uncompressed
1005 * storage mode, which is usually only used for data which cannot be compressed.
1006 * The buffer layout is the same as for AFBC buffers without USM set, this only
1007 * affects the storage mode of the individual superblocks. Note that even a
1008 * buffer without USM set may use uncompressed storage mode for some or all
1009 * superblocks, USM just guarantees it for all.
1011 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1014 * Arm 16x16 Block U-Interleaved modifier
1016 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1017 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1018 * in the block are reordered.
1020 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1021 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1024 * Allwinner tiled modifier
1026 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1027 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1030 * With this tiling, the luminance samples are disposed in tiles representing
1031 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1032 * The pixel order in each tile is linear and the tiles are disposed linearly,
1033 * both in row-major order.
1035 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1038 * Amlogic Video Framebuffer Compression modifiers
1040 * Amlogic uses a proprietary lossless image compression protocol and format
1041 * for their hardware video codec accelerators, either video decoders or
1042 * video input encoders.
1044 * It considerably reduces memory bandwidth while writing and reading
1047 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1048 * per component YCbCr 420, single plane :
1049 * - DRM_FORMAT_YUV420_8BIT
1050 * - DRM_FORMAT_YUV420_10BIT
1052 * The first 8 bits of the mode defines the layout, then the following 8 bits
1053 * defines the options changing the layout.
1055 * Not all combinations are valid, and different SoCs may support different
1056 * combinations of layout and options.
1058 #define __fourcc_mod_amlogic_layout_mask 0xff
1059 #define __fourcc_mod_amlogic_options_shift 8
1060 #define __fourcc_mod_amlogic_options_mask 0xff
1062 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1063 fourcc_mod_code(AMLOGIC, \
1064 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1065 (((__options) & __fourcc_mod_amlogic_options_mask) \
1066 << __fourcc_mod_amlogic_options_shift))
1068 /* Amlogic FBC Layouts */
1071 * Amlogic FBC Basic Layout
1073 * The basic layout is composed of:
1074 * - a body content organized in 64x32 superblocks with 4096 bytes per
1075 * superblock in default mode.
1076 * - a 32 bytes per 128x64 header block
1078 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1080 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1083 * Amlogic FBC Scatter Memory layout
1085 * Indicates the header contains IOMMU references to the compressed
1086 * frames content to optimize memory access and layout.
1088 * In this mode, only the header memory address is needed, thus the
1089 * content memory organization is tied to the current producer
1090 * execution and cannot be saved/dumped neither transferrable between
1091 * Amlogic SoCs supporting this modifier.
1093 * Due to the nature of the layout, these buffers are not expected to
1094 * be accessible by the user-space clients, but only accessible by the
1095 * hardware producers and consumers.
1097 * The user-space clients should expect a failure while trying to mmap
1098 * the DMA-BUF handle returned by the producer.
1100 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1102 /* Amlogic FBC Layout Options Bit Mask */
1105 * Amlogic FBC Memory Saving mode
1107 * Indicates the storage is packed when pixel size is multiple of word
1108 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1111 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1112 * the basic layout and 3200 bytes per 64x32 superblock combined with
1113 * the scatter layout.
1115 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1125 * with DCC & without DCC_RETILE:
1126 * - main surface in plane 0
1127 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1129 * with DCC & DCC_RETILE:
1130 * - main surface in plane 0
1131 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1132 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1134 * For multi-plane formats the above surfaces get merged into one plane for
1135 * each format plane, based on the required alignment only.
1137 * Bits Parameter Notes
1138 * ----- ------------------------ ---------------------------------------------
1140 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1141 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1145 * 16 DCC_INDEPENDENT_64B
1146 * 17 DCC_INDEPENDENT_128B
1147 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1148 * 20 DCC_CONSTANT_ENCODE
1149 * 23:21 PIPE_XOR_BITS Only for some chips
1150 * 26:24 BANK_XOR_BITS Only for some chips
1151 * 29:27 PACKERS Only for some chips
1152 * 32:30 RB Only for some chips
1153 * 35:33 PIPE Only for some chips
1154 * 55:36 - Reserved for future use, must be zero
1156 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1158 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1160 /* Reserve 0 for GFX8 and older */
1161 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1162 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1163 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1166 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1169 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1172 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1173 * GFX9 as canonical version.
1175 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1176 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1177 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1178 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1180 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1181 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1182 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1184 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1185 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1186 #define AMD_FMT_MOD_TILE_SHIFT 8
1187 #define AMD_FMT_MOD_TILE_MASK 0x1F
1189 /* Whether DCC compression is enabled. */
1190 #define AMD_FMT_MOD_DCC_SHIFT 13
1191 #define AMD_FMT_MOD_DCC_MASK 0x1
1194 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1195 * one which is not-aligned.
1197 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1198 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1200 /* Only set if DCC_RETILE = false */
1201 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1202 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1204 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1205 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1206 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1207 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1208 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1209 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1212 * DCC supports embedding some clear colors directly in the DCC surface.
1213 * However, on older GPUs the rendering HW ignores the embedded clear color
1214 * and prefers the driver provided color. This necessitates doing a fastclear
1215 * eliminate operation before a process transfers control.
1217 * If this bit is set that means the fastclear eliminate is not needed for these
1218 * embeddable colors.
1220 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1221 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1224 * The below fields are for accounting for per GPU differences. These are only
1225 * relevant for GFX9 and later and if the tile field is *_X/_T.
1227 * PIPE_XOR_BITS = always needed
1228 * BANK_XOR_BITS = only for TILE_VER_GFX9
1229 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1230 * RB = only for TILE_VER_GFX9 & DCC
1231 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1233 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1234 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1235 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1236 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1237 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1238 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1239 #define AMD_FMT_MOD_RB_SHIFT 30
1240 #define AMD_FMT_MOD_RB_MASK 0x7
1241 #define AMD_FMT_MOD_PIPE_SHIFT 33
1242 #define AMD_FMT_MOD_PIPE_MASK 0x7
1244 #define AMD_FMT_MOD_SET(field, value) \
1245 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1246 #define AMD_FMT_MOD_GET(field, value) \
1247 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1248 #define AMD_FMT_MOD_CLEAR(field) \
1249 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1251 #if defined(__cplusplus)
1255 #endif /* DRM_FOURCC_H */