1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
37 #if defined(__cplusplus)
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
79 * Memory in this pool could be swapped out to disk if there is pressure.
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linezrized
86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
87 * carved out by the BIOS.
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
90 * across shader threads.
92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
93 * execution of all the waves on a device.
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
98 #define AMDGPU_GEM_DOMAIN_CPU 0x1
99 #define AMDGPU_GEM_DOMAIN_GTT 0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
101 #define AMDGPU_GEM_DOMAIN_GDS 0x8
102 #define AMDGPU_GEM_DOMAIN_GWS 0x10
103 #define AMDGPU_GEM_DOMAIN_OA 0x20
104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119 /* Flag that create shadow bo(GTT) while allocating vram bo */
120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121 /* Flag that allocating the BO should use linear VRAM */
122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123 /* Flag that BO is always valid in this VM */
124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125 /* Flag that BO sharing will be explicitly synchronized */
126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128 * for the second page onward should be set to NC.
130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
132 struct drm_amdgpu_gem_create_in {
133 /** the requested memory size */
135 /** physical start_addr alignment in bytes for some HW requirements */
137 /** the requested memory domains */
139 /** allocation flags */
143 struct drm_amdgpu_gem_create_out {
144 /** returned GEM object handle */
149 union drm_amdgpu_gem_create {
150 struct drm_amdgpu_gem_create_in in;
151 struct drm_amdgpu_gem_create_out out;
154 /** Opcode to create new residency list. */
155 #define AMDGPU_BO_LIST_OP_CREATE 0
156 /** Opcode to destroy previously created residency list */
157 #define AMDGPU_BO_LIST_OP_DESTROY 1
158 /** Opcode to update resource information in the list */
159 #define AMDGPU_BO_LIST_OP_UPDATE 2
161 struct drm_amdgpu_bo_list_in {
162 /** Type of operation */
164 /** Handle of list or 0 if we want to create one */
166 /** Number of BOs in list */
168 /** Size of each element describing BO */
170 /** Pointer to array describing BOs */
174 struct drm_amdgpu_bo_list_entry {
177 /** New (if specified) BO priority to be used during migration */
181 struct drm_amdgpu_bo_list_out {
182 /** Handle of resource list */
187 union drm_amdgpu_bo_list {
188 struct drm_amdgpu_bo_list_in in;
189 struct drm_amdgpu_bo_list_out out;
192 /* context related */
193 #define AMDGPU_CTX_OP_ALLOC_CTX 1
194 #define AMDGPU_CTX_OP_FREE_CTX 2
195 #define AMDGPU_CTX_OP_QUERY_STATE 3
196 #define AMDGPU_CTX_OP_QUERY_STATE2 4
198 /* GPU reset status */
199 #define AMDGPU_CTX_NO_RESET 0
200 /* this the context caused it */
201 #define AMDGPU_CTX_GUILTY_RESET 1
202 /* some other context caused it */
203 #define AMDGPU_CTX_INNOCENT_RESET 2
205 #define AMDGPU_CTX_UNKNOWN_RESET 3
207 /* indicate gpu reset occured after ctx created */
208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
209 /* indicate vram lost occured after ctx created */
210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211 /* indicate some job from this context once cause gpu hang */
212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
214 /* Context priority level */
215 #define AMDGPU_CTX_PRIORITY_UNSET -2048
216 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
217 #define AMDGPU_CTX_PRIORITY_LOW -512
218 #define AMDGPU_CTX_PRIORITY_NORMAL 0
219 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
220 #define AMDGPU_CTX_PRIORITY_HIGH 512
221 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
223 struct drm_amdgpu_ctx_in {
224 /** AMDGPU_CTX_OP_* */
226 /** For future use, no flags defined so far */
232 union drm_amdgpu_ctx_out {
239 /** For future use, no flags defined so far */
241 /** Number of resets caused by this context so far. */
243 /** Reset status since the last call of the ioctl. */
248 union drm_amdgpu_ctx {
249 struct drm_amdgpu_ctx_in in;
250 union drm_amdgpu_ctx_out out;
254 #define AMDGPU_VM_OP_RESERVE_VMID 1
255 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
257 struct drm_amdgpu_vm_in {
258 /** AMDGPU_VM_OP_* */
263 struct drm_amdgpu_vm_out {
264 /** For future use, no flags defined so far */
268 union drm_amdgpu_vm {
269 struct drm_amdgpu_vm_in in;
270 struct drm_amdgpu_vm_out out;
274 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
275 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
277 struct drm_amdgpu_sched_in {
278 /* AMDGPU_SCHED_OP_* */
285 union drm_amdgpu_sched {
286 struct drm_amdgpu_sched_in in;
290 * This is not a reliable API and you should expect it to fail for any
291 * number of reasons and have fallback path that do not use userptr to
292 * perform any operation.
294 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
295 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
296 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
297 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
299 struct drm_amdgpu_gem_userptr {
302 /* AMDGPU_GEM_USERPTR_* */
304 /* Resulting GEM handle */
309 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
310 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
311 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
312 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
313 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
314 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
315 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
316 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
317 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
318 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
319 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
320 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
321 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
322 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
323 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
324 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
325 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
327 /* GFX9 and later: */
328 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
329 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
331 /* Set/Get helpers for tiling flags. */
332 #define AMDGPU_TILING_SET(field, value) \
333 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
334 #define AMDGPU_TILING_GET(value, field) \
335 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
337 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
338 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
340 /** The same structure is shared for input/output */
341 struct drm_amdgpu_gem_metadata {
342 /** GEM Object handle */
344 /** Do we want get or set metadata */
347 /** For future use, no flags defined so far */
349 /** family specific tiling info */
351 __u32 data_size_bytes;
356 struct drm_amdgpu_gem_mmap_in {
357 /** the GEM object handle */
362 struct drm_amdgpu_gem_mmap_out {
363 /** mmap offset from the vma offset manager */
367 union drm_amdgpu_gem_mmap {
368 struct drm_amdgpu_gem_mmap_in in;
369 struct drm_amdgpu_gem_mmap_out out;
372 struct drm_amdgpu_gem_wait_idle_in {
373 /** GEM object handle */
375 /** For future use, no flags defined so far */
377 /** Absolute timeout to wait */
381 struct drm_amdgpu_gem_wait_idle_out {
382 /** BO status: 0 - BO is idle, 1 - BO is busy */
384 /** Returned current memory domain */
388 union drm_amdgpu_gem_wait_idle {
389 struct drm_amdgpu_gem_wait_idle_in in;
390 struct drm_amdgpu_gem_wait_idle_out out;
393 struct drm_amdgpu_wait_cs_in {
394 /* Command submission handle
395 * handle equals 0 means none to wait for
396 * handle equals ~0ull means wait for the latest sequence number
399 /** Absolute timeout to wait */
407 struct drm_amdgpu_wait_cs_out {
408 /** CS status: 0 - CS completed, 1 - CS still busy */
412 union drm_amdgpu_wait_cs {
413 struct drm_amdgpu_wait_cs_in in;
414 struct drm_amdgpu_wait_cs_out out;
417 struct drm_amdgpu_fence {
425 struct drm_amdgpu_wait_fences_in {
426 /** This points to uint64_t * which points to fences */
433 struct drm_amdgpu_wait_fences_out {
435 __u32 first_signaled;
438 union drm_amdgpu_wait_fences {
439 struct drm_amdgpu_wait_fences_in in;
440 struct drm_amdgpu_wait_fences_out out;
443 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
444 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
446 /* Sets or returns a value associated with a buffer. */
447 struct drm_amdgpu_gem_op {
448 /** GEM object handle */
450 /** AMDGPU_GEM_OP_* */
452 /** Input or return value */
456 #define AMDGPU_VA_OP_MAP 1
457 #define AMDGPU_VA_OP_UNMAP 2
458 #define AMDGPU_VA_OP_CLEAR 3
459 #define AMDGPU_VA_OP_REPLACE 4
461 /* Delay the page table update till the next CS */
462 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
465 /* readable mapping */
466 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
467 /* writable mapping */
468 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
469 /* executable mapping, new for VI */
470 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
471 /* partially resident texture */
472 #define AMDGPU_VM_PAGE_PRT (1 << 4)
473 /* MTYPE flags use bit 5 to 8 */
474 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
475 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
476 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
477 /* Use NC MTYPE instead of default MTYPE */
478 #define AMDGPU_VM_MTYPE_NC (1 << 5)
479 /* Use WC MTYPE instead of default MTYPE */
480 #define AMDGPU_VM_MTYPE_WC (2 << 5)
481 /* Use CC MTYPE instead of default MTYPE */
482 #define AMDGPU_VM_MTYPE_CC (3 << 5)
483 /* Use UC MTYPE instead of default MTYPE */
484 #define AMDGPU_VM_MTYPE_UC (4 << 5)
486 struct drm_amdgpu_gem_va {
487 /** GEM object handle */
490 /** AMDGPU_VA_OP_* */
492 /** AMDGPU_VM_PAGE_* */
494 /** va address to assign . Must be correctly aligned.*/
496 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
498 /** Specify mapping size. Must be correctly aligned. */
502 #define AMDGPU_HW_IP_GFX 0
503 #define AMDGPU_HW_IP_COMPUTE 1
504 #define AMDGPU_HW_IP_DMA 2
505 #define AMDGPU_HW_IP_UVD 3
506 #define AMDGPU_HW_IP_VCE 4
507 #define AMDGPU_HW_IP_UVD_ENC 5
508 #define AMDGPU_HW_IP_VCN_DEC 6
509 #define AMDGPU_HW_IP_VCN_ENC 7
510 #define AMDGPU_HW_IP_VCN_JPEG 8
511 #define AMDGPU_HW_IP_NUM 9
513 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
515 #define AMDGPU_CHUNK_ID_IB 0x01
516 #define AMDGPU_CHUNK_ID_FENCE 0x02
517 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
518 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
519 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
520 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
522 struct drm_amdgpu_cs_chunk {
528 struct drm_amdgpu_cs_in {
529 /** Rendering context id */
531 /** Handle of resource list associated with CS */
532 __u32 bo_list_handle;
535 /** this points to __u64 * which point to cs chunks */
539 struct drm_amdgpu_cs_out {
543 union drm_amdgpu_cs {
544 struct drm_amdgpu_cs_in in;
545 struct drm_amdgpu_cs_out out;
548 /* Specify flags to be used for IB */
550 /* This IB should be submitted to CE */
551 #define AMDGPU_IB_FLAG_CE (1<<0)
553 /* Preamble flag, which means the IB could be dropped if no context switch */
554 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
556 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
557 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
559 /* The IB fence should do the L2 writeback but not invalidate any shader
560 * caches (L2/vL1/sL1/I$). */
561 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
563 struct drm_amdgpu_cs_chunk_ib {
565 /** AMDGPU_IB_FLAG_* */
567 /** Virtual address to begin IB execution */
569 /** Size of submission */
571 /** HW IP to submit to */
573 /** HW IP index of the same type to submit to */
575 /** Ring index to submit to */
579 struct drm_amdgpu_cs_chunk_dep {
587 struct drm_amdgpu_cs_chunk_fence {
592 struct drm_amdgpu_cs_chunk_sem {
596 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
597 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
598 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
600 union drm_amdgpu_fence_to_handle {
602 struct drm_amdgpu_fence fence;
611 struct drm_amdgpu_cs_chunk_data {
613 struct drm_amdgpu_cs_chunk_ib ib_data;
614 struct drm_amdgpu_cs_chunk_fence fence_data;
619 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
622 #define AMDGPU_IDS_FLAGS_FUSION 0x1
623 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
625 /* indicate if acceleration can be working */
626 #define AMDGPU_INFO_ACCEL_WORKING 0x00
627 /* get the crtc_id from the mode object id? */
628 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
629 /* query hw IP info */
630 #define AMDGPU_INFO_HW_IP_INFO 0x02
631 /* query hw IP instance count for the specified type */
632 #define AMDGPU_INFO_HW_IP_COUNT 0x03
633 /* timestamp for GL_ARB_timer_query */
634 #define AMDGPU_INFO_TIMESTAMP 0x05
635 /* Query the firmware version */
636 #define AMDGPU_INFO_FW_VERSION 0x0e
637 /* Subquery id: Query VCE firmware version */
638 #define AMDGPU_INFO_FW_VCE 0x1
639 /* Subquery id: Query UVD firmware version */
640 #define AMDGPU_INFO_FW_UVD 0x2
641 /* Subquery id: Query GMC firmware version */
642 #define AMDGPU_INFO_FW_GMC 0x03
643 /* Subquery id: Query GFX ME firmware version */
644 #define AMDGPU_INFO_FW_GFX_ME 0x04
645 /* Subquery id: Query GFX PFP firmware version */
646 #define AMDGPU_INFO_FW_GFX_PFP 0x05
647 /* Subquery id: Query GFX CE firmware version */
648 #define AMDGPU_INFO_FW_GFX_CE 0x06
649 /* Subquery id: Query GFX RLC firmware version */
650 #define AMDGPU_INFO_FW_GFX_RLC 0x07
651 /* Subquery id: Query GFX MEC firmware version */
652 #define AMDGPU_INFO_FW_GFX_MEC 0x08
653 /* Subquery id: Query SMC firmware version */
654 #define AMDGPU_INFO_FW_SMC 0x0a
655 /* Subquery id: Query SDMA firmware version */
656 #define AMDGPU_INFO_FW_SDMA 0x0b
657 /* Subquery id: Query PSP SOS firmware version */
658 #define AMDGPU_INFO_FW_SOS 0x0c
659 /* Subquery id: Query PSP ASD firmware version */
660 #define AMDGPU_INFO_FW_ASD 0x0d
661 /* Subquery id: Query VCN firmware version */
662 #define AMDGPU_INFO_FW_VCN 0x0e
663 /* Subquery id: Query GFX RLC SRLC firmware version */
664 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
665 /* Subquery id: Query GFX RLC SRLG firmware version */
666 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
667 /* Subquery id: Query GFX RLC SRLS firmware version */
668 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
669 /* number of bytes moved for TTM migration */
670 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
671 /* the used VRAM size */
672 #define AMDGPU_INFO_VRAM_USAGE 0x10
673 /* the used GTT size */
674 #define AMDGPU_INFO_GTT_USAGE 0x11
675 /* Information about GDS, etc. resource configuration */
676 #define AMDGPU_INFO_GDS_CONFIG 0x13
677 /* Query information about VRAM and GTT domains */
678 #define AMDGPU_INFO_VRAM_GTT 0x14
679 /* Query information about register in MMR address space*/
680 #define AMDGPU_INFO_READ_MMR_REG 0x15
681 /* Query information about device: rev id, family, etc. */
682 #define AMDGPU_INFO_DEV_INFO 0x16
683 /* visible vram usage */
684 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
685 /* number of TTM buffer evictions */
686 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
687 /* Query memory about VRAM and GTT domains */
688 #define AMDGPU_INFO_MEMORY 0x19
689 /* Query vce clock table */
690 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
691 /* Query vbios related information */
692 #define AMDGPU_INFO_VBIOS 0x1B
693 /* Subquery id: Query vbios size */
694 #define AMDGPU_INFO_VBIOS_SIZE 0x1
695 /* Subquery id: Query vbios image */
696 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
697 /* Query UVD handles */
698 #define AMDGPU_INFO_NUM_HANDLES 0x1C
699 /* Query sensor related information */
700 #define AMDGPU_INFO_SENSOR 0x1D
701 /* Subquery id: Query GPU shader clock */
702 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
703 /* Subquery id: Query GPU memory clock */
704 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
705 /* Subquery id: Query GPU temperature */
706 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
707 /* Subquery id: Query GPU load */
708 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
709 /* Subquery id: Query average GPU power */
710 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
711 /* Subquery id: Query northbridge voltage */
712 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
713 /* Subquery id: Query graphics voltage */
714 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
715 /* Subquery id: Query GPU stable pstate shader clock */
716 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
717 /* Subquery id: Query GPU stable pstate memory clock */
718 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
719 /* Number of VRAM page faults on CPU access. */
720 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
721 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
723 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
724 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
725 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
726 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
728 struct drm_amdgpu_query_fw {
729 /** AMDGPU_INFO_FW_* */
732 * Index of the IP if there are more IPs of
737 * Index of the engine. Whether this is used depends
738 * on the firmware type. (e.g. MEC, SDMA)
744 /* Input structure for the INFO ioctl */
745 struct drm_amdgpu_info {
746 /* Where the return value will be stored */
747 __u64 return_pointer;
748 /* The size of the return value. Just like "size" in "snprintf",
749 * it limits how many bytes the kernel can write. */
751 /* The query request id. */
761 /** AMDGPU_HW_IP_* */
764 * Index of the IP if there are more IPs of the same
765 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
772 /** number of registers to read */
775 /** For future use, no flags defined so far */
779 struct drm_amdgpu_query_fw query_fw;
792 struct drm_amdgpu_info_gds {
793 /** GDS GFX partition size */
794 __u32 gds_gfx_partition_size;
795 /** GDS compute partition size */
796 __u32 compute_partition_size;
797 /** total GDS memory size */
798 __u32 gds_total_size;
799 /** GWS size per GFX partition */
800 __u32 gws_per_gfx_partition;
801 /** GSW size per compute partition */
802 __u32 gws_per_compute_partition;
803 /** OA size per GFX partition */
804 __u32 oa_per_gfx_partition;
805 /** OA size per compute partition */
806 __u32 oa_per_compute_partition;
810 struct drm_amdgpu_info_vram_gtt {
812 __u64 vram_cpu_accessible_size;
816 struct drm_amdgpu_heap_info {
817 /** max. physical memory */
818 __u64 total_heap_size;
820 /** Theoretical max. available memory in the given heap */
821 __u64 usable_heap_size;
824 * Number of bytes allocated in the heap. This includes all processes
825 * and private allocations in the kernel. It changes when new buffers
826 * are allocated, freed, and moved. It cannot be larger than
832 * Theoretical possible max. size of buffer which
833 * could be allocated in the given heap
835 __u64 max_allocation;
838 struct drm_amdgpu_memory_info {
839 struct drm_amdgpu_heap_info vram;
840 struct drm_amdgpu_heap_info cpu_accessible_vram;
841 struct drm_amdgpu_heap_info gtt;
844 struct drm_amdgpu_info_firmware {
849 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
850 #define AMDGPU_VRAM_TYPE_GDDR1 1
851 #define AMDGPU_VRAM_TYPE_DDR2 2
852 #define AMDGPU_VRAM_TYPE_GDDR3 3
853 #define AMDGPU_VRAM_TYPE_GDDR4 4
854 #define AMDGPU_VRAM_TYPE_GDDR5 5
855 #define AMDGPU_VRAM_TYPE_HBM 6
856 #define AMDGPU_VRAM_TYPE_DDR3 7
857 #define AMDGPU_VRAM_TYPE_DDR4 8
859 struct drm_amdgpu_info_device {
862 /** Internal chip revision: A0, A1, etc.) */
865 /** Revision id in PCI Config space */
868 __u32 num_shader_engines;
869 __u32 num_shader_arrays_per_engine;
871 __u32 gpu_counter_freq;
872 __u64 max_engine_clock;
873 __u64 max_memory_clock;
875 __u32 cu_active_number;
876 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
878 __u32 cu_bitmap[4][4];
879 /** Render backend pipe mask. One render backend is CB+DB. */
880 __u32 enabled_rb_pipes_mask;
882 __u32 num_hw_gfx_contexts;
885 /** Starting virtual address for UMDs. */
886 __u64 virtual_address_offset;
887 /** The maximum virtual address */
888 __u64 virtual_address_max;
889 /** Required alignment of virtual addresses. */
890 __u32 virtual_address_alignment;
891 /** Page table entry - fragment size */
892 __u32 pte_fragment_size;
893 __u32 gart_page_size;
894 /** constant engine ram size*/
896 /** video memory type info*/
898 /** video memory bit width*/
899 __u32 vram_bit_width;
900 /* vce harvesting instance */
901 __u32 vce_harvest_config;
902 /* gfx double offchip LDS buffers */
903 __u32 gc_double_offchip_lds_buf;
904 /* NGG Primitive Buffer */
905 __u64 prim_buf_gpu_addr;
906 /* NGG Position Buffer */
907 __u64 pos_buf_gpu_addr;
908 /* NGG Control Sideband */
909 __u64 cntl_sb_buf_gpu_addr;
910 /* NGG Parameter Cache */
911 __u64 param_buf_gpu_addr;
914 __u32 cntl_sb_buf_size;
915 __u32 param_buf_size;
917 __u32 wave_front_size;
918 /* shader visible vgprs*/
919 __u32 num_shader_visible_vgprs;
920 /* CU per shader array*/
922 /* number of tcc blocks*/
923 __u32 num_tcc_blocks;
924 /* gs vgt table depth*/
925 __u32 gs_vgt_table_depth;
926 /* gs primitive buffer depth*/
927 __u32 gs_prim_buffer_depth;
928 /* max gs wavefront per vgt*/
929 __u32 max_gs_waves_per_vgt;
931 /* always on cu bitmap */
932 __u32 cu_ao_bitmap[4][4];
933 /** Starting high virtual address for UMDs. */
934 __u64 high_va_offset;
935 /** The maximum high virtual address */
939 struct drm_amdgpu_info_hw_ip {
940 /** Version of h/w IP */
941 __u32 hw_ip_version_major;
942 __u32 hw_ip_version_minor;
944 __u64 capabilities_flags;
945 /** command buffer address start alignment*/
946 __u32 ib_start_alignment;
947 /** command buffer size alignment*/
948 __u32 ib_size_alignment;
949 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
950 __u32 available_rings;
954 struct drm_amdgpu_info_num_handles {
955 /** Max handles as supported by firmware for UVD */
956 __u32 uvd_max_handles;
957 /** Handles currently in use for UVD */
958 __u32 uvd_used_handles;
961 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
963 struct drm_amdgpu_info_vce_clock_table_entry {
973 struct drm_amdgpu_info_vce_clock_table {
974 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
975 __u32 num_valid_entries;
980 * Supported GPU families
982 #define AMDGPU_FAMILY_UNKNOWN 0
983 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
984 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
985 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
986 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
987 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
988 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
989 #define AMDGPU_FAMILY_RV 142 /* Raven */
991 #if defined(__cplusplus)